Patent Application
20200411470
This application claims the priority benefit of Taiwan Application No. 108122494, filed on Jun. 27, 2019. The entirety of the above-mentioned patent application is hereby incorporated by reference herein and made a part of this specification.
The present invention relates to a novel method for manufacturing chip semiconductor packages, and more particularly, to a novel method for manufacturing attached single small-size and array type chip semiconductor packages.
In a conventional semiconductor packaging process, after a lead frame is packaged by epoxy resin 100, outer pins 101 are typically left uncovered at both ends of a chip to facilitate subsequent soldering processes. There are various arrangements for the outer pins, some of which are shown in
The present invention provides a packaging method for an attached single small-size and array type chip semiconductor component, comprising: providing a die including a positive electrode and a negative electrode, and providing a circuit board with thin- or thick-film circuits on both sides thereof, reserving two or more connection endpoints in advance on both sides of the circuit board, and then vertically connecting the circuits on the top and bottom sides by hole drilling and electroplating; performing a baking process to bond the positive and negative electrodes of the die with the thin- or thick-film circuits using a conductive adhesive, covering the entire surface with an insulating encapsulant by a process such as lamination, coating, scraping, etc., and performing curing on the insulating encapsulant; performing dicing at locations other than the die to form a package structure without any outer pins to complete the manufacturing of a single small-size chip semiconductor; and forming a forward, reverse or bidirectional chip semiconductor component depending on the configuration of the die.
In the packaging method for an attached single small-size and array type chip semiconductor component of the present invention, the die includes one upper electrode and one bottom electrode, one upper electrode and two bottom electrodes, two upper electrodes and one bottom electrode, two bottom electrodes, one upper electrode and a plurality of bottom electrodes, a plurality of upper electrodes and one bottom electrode, etc.
The present invention provides a packaging method for an attached single small-size and array type chip semiconductor component, comprising: providing a die including a positive electrode and a negative electrode, and providing a circuit board with thin- or thick-film circuits on both sides thereof, reserving two or more connection endpoints in advance on both sides of the circuit board, vertically connecting the circuits on the top and bottom sides by hole drilling and electroplating; performing a baking process to connect the positive and negative electrodes of the die with the thin- or thick-film circuits using a conductive adhesive; and coating a surface of an upper cover plate with an adhesive for bonding the upper cover plate with the die, filling the inner space with an insulating encapsulant, and performing curing on the insulating encapsulant.
In the packaging method for an attached single small-size and array type chip semiconductor component of the present invention, the upper cover plate can be a ceramic plate (e.g. an alumina plate, an aluminum nitride plate, etc.), a plastic plate (e.g. made of PE, PP, PC, polyamidamine, engineering plastics, etc.), a composite board (e.g. a carbon fiber board, a fiberglass board, etc.), etc., and a heat dissipating plate can also be attached to increase heat dissipation.
In the packaging method for an attached single small-size and array type chip semiconductor component of the present invention, the circuit board with the thin- or thick-film circuits on both sides thereof further includes array type outer electrodes with double-side interconnections.
The present invention provides a packaging method for an attached single small-size and array type chip semiconductor component, comprising: providing a die including three electrodes, and providing at least two circuit boards with thin- or thick-film circuits on both sides of each of the circuit boards; performing a baking process to bond the three electrodes of the die with the thin- or thick-film circuits using a conductive adhesive; and filling the inner space with an insulating encapsulant, and performing curing on the insulating encapsulant.
In the packaging method for an attached single small-size and array type chip semiconductor component of the present invention, the packaged attached single small-size and array type chip semiconductor component has a configuration in which current flowing into one input and out of two outputs or a configuration of “forward plus ground lead”, “reverse plus ground lead” and “bidirectional plus ground lead”.
The present invention provides a packaging method for an attached single small-size and array type chip semiconductor component, comprising: providing a die including a positive electrode and a negative electrode, and providing at least two circuit boards with thin- or thick-film circuits on both sides of each of the circuit boards; performing a baking process to bond the positive and negative electrodes of the die with the thin- or thick-film circuits using a conductive adhesive; filling the inner space with an insulating encapsulant, and performing curing on the insulating encapsulant; forming an end electrode on one end after dicing by a process such as coating, silver coating, a thin-film manufacturing process, etc., such that the end electrode on the one end is interconnected with an electrode contact already in place to complete the manufacturing of a single small-size chip semiconductor; and performing an electroplating process to form a single SMD-type semiconductor chip component.
The present invention provides a packaging method for an attached single small-size and array type chip semiconductor component, comprising: providing a die including three electrodes, and providing at least two circuit boards with thin- or thick-film circuits on both sides of each of the circuit boards; performing a baking process to connect the three electrodes of the die with the thin- or thick-film circuits using a conductive adhesive; filling the inner space with an insulating encapsulant, and performing curing on the insulating encapsulant; forming end electrodes on two ends after dicing by a process such as coating, silver coating, a thin-film manufacturing process, etc., such that the end electrodes on the two ends are interconnected with electrode contacts already in place to complete the manufacturing of a single small-size three-electrode chip semiconductor; and performing an electroplating process to form a single SMD-type semiconductor chip component.
In the packaging method for an attached single small-size and array type chip semiconductor component of the present invention, the circuit board with the thin- or thick-film circuits on both sides thereof further includes array type outer electrodes of a double-sided interconnection configuration, and a single side of the circuit board further includes horizontally lead out electrodes at two ends, forming end electrodes on the two ends after dicing by a process such as coating, silver coating, a thin-film manufacturing process, etc., such that the two end electrodes are interconnected with the electrode contacts already in place.
In the packaging method for an attached single small-size and array type chip semiconductor component of the present invention, the thin- or thick-film circuits of the circuit board are manufactured on a ceramic plate (e.g. an alumina plate, an aluminum nitride plate, etc.), a plastic plate (e.g. made of PE, PP, PC, polyamidamine, engineering plastics, etc.), a composite board (e.g. a carbon fiber board, a fiberglass board, etc.), etc., or printed on a heat dissipating plate to increase heat dissipation.
In order to fully understand the objectives, features and technical effects of the present invention, the present invention is explained in details by way of various embodiments below in conjunction with the attached drawings.
The present invention includes the use of circuit board(s) with double-side interconnections alone or the simultaneous use of a circuit board with single-side interconnections and another circuit board with double-side interconnections for connecting between a semiconductor chip and electrodes. The circuits can be formed by a thin-film manufacturing process, a thick-film printing process, or the like on a ceramic plate (e.g. an alumina plate, an aluminum nitride plate, etc.), a plastic plate (e.g. made of PE, PP, PC, polyamidamine, engineering plastics, etc.), a composite board (e.g. a carbon fiber board, a fiberglass board, etc.), etc. The configuration of a circuit board with single-side interconnections includes reserving two or more connection endpoints on a single side of the circuit board and leading the circuits out horizontally to the sides. On the other hand, the configuration of a circuit board with double-side interconnections includes reserving two or more connection endpoints on both sides of the circuit board, vertically connecting the top and bottom circuit through the hole drilling and electroplating processes, and the circuits on the inner layer are used as inner electrodes for connecting with a semiconductor die, while the circuits on the outer layer are used as outer electrodes for connecting with a SMT board.
Lead-free conductive paste (e.g. silver paste, silver palladium paste, palladium paste, platinum paste, copper paste, nickel paste, aluminum paste, tin paste, tin lead paste, etc.) is dispensed on two or more connection endpoints, and a semiconductor die is placed on the conductive adhesive. Positioning in the dispensing and die placement processes can both be carried out using a CCD to accurately placing the semiconductor die on reserved electrodes for connecting the semiconductor die with thin- or thick-film circuits. Two or more electrodes of the semiconductor die can be interconnected with the reserved inner electrodes to satisfy packaging for single small-size semiconductor dies (e.g. 01005, 0201, 0402 etc.) or array type semiconductor dies (e.g. 0204, 0306, 0405, 0508, 0510, 0612).
An insulating encapsulant is laid across the entire surface by a method such as lamination, coating, scraping, filling, etc., wherein lamination and coating can be repeated a plurality of times to build up the insulating encapsulant to a certain thickness, and scraping and filling can also be repeated one or two times to achieve a certain thickness of the insulating encapsulant. After the insulating encapsulant is cured, dicing can be carried out. If the configuration of the circuit board with double-side interconnections is used, an attached single small-size or array type semiconductor component (or packaged product) is formed after dicing. On the other hand, if the configuration of both circuit boards with single-side and double-side interconnections is used, inner electrodes lead out to the sides have to be interconnected with outer electrodes after dicing through a process such as coating, silver coating, a thin-film manufacturing process, etc. An attached single small-size or array type semiconductor component (or packaged product) can then be formed after electroplating.
A packaging and manufacturing method for a single small-size chip semiconductor including the use of a circuit board with double-side interconnections only is shown: (1) As shown in
A packaging and manufacturing method for a single small-size chip semiconductor including a cover plate and the use of a circuit board with double-side interconnections only is shown: (1) As shown in
A packaging and manufacturing method for a single small-size chip semiconductor including three electrodes and the use of circuit boards with double-side interconnections only is shown: (1) As shown in
A packaging and manufacturing method for a single small-size chip semiconductor including the use of both a circuit board with single-side interconnection and a circuit board with double-side interconnections is shown: (1) As shown in
A packaging and manufacturing method for a single small-size chip semiconductor including three electrodes and both a circuit board with single-side interconnection and a circuit board with double-side interconnections is shown: (1) As shown in
A packaging and manufacturing method for an array type chip semiconductor including the use of a circuit board with double-side interconnections only is shown: (1) A plurality of connection endpoints are arranged in an array on the inner and outer layers of a double-sided circuit board. The circuits on the top and bottom sides are connected vertically through hole drilling and electroplating to form 2×2 (791), 2×3 (792), 2×4 (793) array type outer electrodes. (2) Packaging is performed using the method described in Embodiment 1 or 2, thereby completing the manufacturing of an array type (e.g. 0204, 0306, 0405, 0508, etc.) chip semiconductor, as shown in
A packaging and manufacturing method for an array type chip semiconductor including the use of both a circuit board with single-side interconnection and a circuit board with double-side interconnections is shown: (1) The configuration of the circuit board with the double-side interconnection includes allowing a plurality of connection endpoints to be arranged in an array on the inner and outer layers of a double-sided circuit board. The circuits on the top and bottom sides are connected vertically through hole drilling and electroplating to form 2×2 (891), 2×3 (892), 2×4 (893) array type outer electrodes. The configuration of the circuit board with single-side interconnection includes leading the circuit on the inner layer of a single-sided circuit board horizontally out to the end(s), for example, shown by reference numerals 894, 895 and 896. (2) Packaging is performed using the method described in Embodiment 5. After dicing, two end electrodes are formed through a process such as coating, silver coating, a thin-film manufacturing process, etc., and these two end electrodes are connected with the electrode contacts already in place, for example, shown by reference numerals 897, 898 and 899. After electroplating, an array type (e.g. 0204, 0306, 0405, 0508, etc.) chip semiconductor can be formed, as shown in
In conclusion, a plurality of packaging methods for attached single small-size and array type chip semiconductor components can be provided by the present invention.
The present invention has been disclosed in the preferred embodiment above. However, it can be appreciated by one of ordinary skill in the art that these embodiments are illustrative rather than limitations of the scope of the present invention. It should be noted that the above embodiments can be modified and replaced with equivalents thereof without departing from the scope of the present invention. Therefore, the scope claimed of the present invention should only be defined by the following claims.
| Number | Date | Country | Kind |
|---|---|---|---|
| 108122494 | Jun 2019 | TW | national |
