Patent Application
20180226372
The present invention to package Lire and manufacturing method thereof.
In recent years, flip-chip and ball grid array techniques have been increasingly used to connect an integrated circuit (IC) chip to an interconnection substrate such as printed circuit boards and to a package substrate. In flip-chip bonding an IC chip component to an interconnection substrate or printed circuit board plural (e.g., an array) solder balls (also known as “solder bumps”) are formed on a surface of a component, typically the IC chip component, and the component with the solder bumps is brought to face another component to be bonded. The two components are then heated (such as in a furnace) to reflow the solder bumps between the two components (heat the solder bumps first, then allow the solder bumps to be cooled down), thereby establishing electrical connections between respective terminals of the two components.
However, a reflow process often results in a high temperature that affects the performance of the components. Thus, to meet requirements for higher quality and reliability, advanced package forming methods and structures are needed to be developed.
An embodiment of the present disclosure provides a method for manufacturing a package structure. The method includes providing a semiconductor substrate.; forming an under bump metallurgy layer on the semiconductor substrate; forming a dielectric layer on the semiconductor substrate; forming an opening in the dielectric layer; forming at least one bump in the opening of the dielectric layer; removing the dielectric layer; and performing a compression process to the bump.
An embodiment of the present disclosure provides a package structure, the package structure includes a semiconductor substrate, an under bump metallurgy layer, and at least one bump. The under bump metallurgy layer is disposed on the semiconductor substrate. The bump is disposed on the under bump metallurgy layer, and the bump includes a first portion and a second portion disposed under the first portion, in which a top surface of the first portion comprises a flat portion and a rounded portion.
It is to be understood that both the foregoing general description and the following detailed description are by examples, and are intended to provide further explanation of the invention as claimed.
Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It is noted that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion:
The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.
Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” upper and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatiall relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.
The semiconductor substrate 12 may include semiconductor material, such as silicon (Si), germanium (Ge), or silicon germanium (SiGe); a compound semiconductor including silicon carbide, gallium arsenic, gallium phosphide, indium phosphide, indium arsenide, and/or indium antimonide; an alloy semiconductor including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and/or GaInAsP; or combinations thereof. Other substrates, such as multi-layered or gradient substrates, may also be used. The active devices, such as transistors, diodes, capacitors, resistors, etc., may be formed in and/or on the semiconductor substrate 12 and may be interconnected by interconnect structures formed by, for example, metallization patterns in one or more dielectric layers in the semiconductor substrate 12 to form integrated circuits.
The integrated circuits may be logic dies (e.g., central processing unit, microcontroller, etc.), memory dies (e.g., dynamic random access memory (DRAM) die, static random access memory (SRAM) the, etc.), power management dies (e.g., power management integrated circuit (PMIC) die), radio frequency (RF) dies, sensor dies, micro-electro-mechanical-system (MEMS) dies, signal processing dies (e.g., digital signal processing (DSP) die), front-end dies (e.g., analog front-end (AFE) dies), the like, or a combination thereof.
A bond pad 14 is formed on a top surface of the semiconductor substrate 12 for establishing electrical connections to external circuits. In an example of forming the bond pad 14, a seed layer (not shown) is formed over the semiconductor substrate 12. In some embodiments, the seed layer is a metal layer, which may be a single layer or a composite layer including plural sub-layers formed from different materials. In some embodiments, the seed layer may be a titanium layer and a copper layer over the titanium layer. The, seed layer may be formed using, for example, physical vapor deposition (PVD) or the like. A photo resist is then formed and patterned on the seed layer. The photo resist may be formed by spin coating or the like and may be exposed to light for patterning,. The pattern of the photo resist defines the bond pad 14. The patterning forms openings through the photo resist to expose the seed layer. A conductive material is formed in the openings of the photo resist and on the exposed portions of the seed layer. The conductive material may be formed by plating, such as electroplating or electroless plating, or the like. The conductive material may include a metal, such as copper, titanium, tungsten, aluminum, or the like. Then, the photo resist and portions of the seed layer on which the conductive material is not formed are removed. The photo resist may be removed by a proper asking or stripping process, using, for example, oxygen plasma or the like. Once the photo resist is removed, exposed portions of the seed layer are removed, by using an proper etching process, such as wet or dry etching. The remaining portions of the seed layer and conductive material form the bond pad 14.
Referring to
Referring to
Referring to
The dielectric layer 34 is then patterned to form an opening 38 to expose portions of the under bump metallurgy 26. The opening 38 defines a position of the bump to be subsequently formed. The patterning may be performed by a proper process such as exposing the dielectric layer 34 to light when the dielectric layer 34 is a photo-sensitive material, or for example, anisotropic etching.
Reference is made to
Generally, the bump 40 has a first portion 40A and a second portion 40B disposed below the first portion 40A, in which the first portion 40A protruds from the top surface 34S of the dielectric layer 34, and the second portion 40B is embedded in the dielectric layer 34. More particularly,since the first portion 40A protrudes from the top surface 34S of the dielectric layer 34 parts of the first portion 40A may further be formed over the top surface 34S of the dielectric layer 34. Thus, a width of the first portion 40A is greater than that of the second portion 40B.
In some embodiments, the thickness of the dielectric layer 34 is carefully controlled. For example, if the dielectric layer 34 is a photoresist layer, the thickness of the dielectric layer 34 may be in the range between about 30 pm and about 40 pm, but the present disclosure is not limited thereto. The reason for tightly controlling the thickness of the dielectric layer 34 is that, for achieving a fine-pitched bump formation, a dielectric layer (e.g. a photoresist layer) of a reasonably small thickness is required to achieve high imaging resolution. It is known that for example, during a photolithography process, the thicker the photoresist layer is the poorer accuracy the imaging process has. To maintain a reasonable accuracy in the imaging process on the dielectric layer 34, reasonably thin dielectric layer 34 is required, thus resulting in a mushroom configuration of the bump 40 deposited therein.
Referring to
After the dielectric layer 34 is removed, the under bump metallurgy 26 is etched away by using the bump 40 as a mask in a suitable process, such as a wet etching process. Thus, portions of the under bump metallurgy 26 under the dielectric layer 34 (shown in
As shown in
On the other hand, the top surface of the first portion 40A is substantially a round shape. The sidewall of the second portion 40B is substantially perpendicular to the semiconductor substrate 12. Accordingly, the sidewall of the second portion 40B of the bump 40 are shown as substantially straight lines in a cross-sectional view.
Referring to
It should be noted that the plate 52 should be harder than the bump 40, such that the bump 40 may be reformed to a shape corresponding to the profile of the plate 52, such as the flat surface 52S. In some embodiments, the material of the plate 52 has a larger Young's modulus than the material of the bump 40. In the present embodiment, the flat surface 52S of the plate 52 is substantially parallel to the longitudinal direction of the semiconductor substrate 12.
As described above, the bump 40 may be formed from conductive metal such as solder, copper, aluminum, gold, nickel, silver, palladium, tin, the like, or a combination thereof. In the compression process 50, due to the malleability of metal, the bump 40 is deformed and may extend laterally. As a result, the bump 40 includes an extension portion 40E. The extension portion 40E is defined as the shape change between the original bump 40 (shown by the dash line) and the deformed bump 40 (shown by the solid line). In some embodiments, the extension portion 40E is evenly distributed on the opposite sides of the bump 40. In the present embodiment, the extension portion 40E is present at the first portion 40A and the second portion 40B of the bump 40. That is, both the first portion 40A and the second portion 406 of the bump 40 extend during the compression process 50.
It should be understood that, the shape of the deformed bump 40 (the solid line) is merely used for explanation and the present disclosure is not limited thereto. The shape of the deformed bump 40 (or the extension portion 40E) may be varied according to actual situations. Also the condition of the compression process 50, such as the material of the bump, the shape of the plate, or the downward force of the compression process, may be controlled to obtain a desired profile of the bump.
Referring to 1H, after the compression process 50 (shown in
The first portion 40A and the second portion 406 of the final bump 40 have a third width W3 and a fourth width W4, respectively. The third width W3 is greater than the fourth width W4. It should be noted that the fourth width W4 is the average width of the second portion 40B. Further, due to the extension of the bump, the third width W3 is greater than the first width W1 (the original width of the first portion 40A shown in
On the other hand, the first portion 40A of bump 40 has a top surface 42, in which the top surface 42 further includes a flat portion 42A and a rounded portion 42B. The fiat portion 42A is formed according to the flat surface 52S of the plate 52 shown in
Referring to
A compression process 50 is applied to the package structure 10. More particularly, the compression process 50 is applied to the top surface of the bump 40. The compression process 50 includes providing a plate 52. The plate 52 may be controlled by a tool, such that the plate 52 is moved toward the package structure 10 and further deform the profile of the top surface of the bump 40 by providing a downward strength to the bump 40. In this embodiment, the plate 52 has a flat surface 52S, in which the flat surface 52S faces and contacts the top surface of bump 40 and followed with a downward force, so as to form a flat surface on the bump 40. The top surface of the bump 40 is partially in contact with the plate 52, thereby forming a flat portion at a center, and forming a rounded portion at an edge.
It should be noted that the plate 52 should be harder than the bump 40, such that the bump 40 may be deformed to a shape corresponding to the profile of the plate 52, such as the flat surface 52S. In some embodiments, the material of the plate 52 has a larger Young's modulus than the material of the bump 40. In the present embodiment, the fiat surface 52S of the plate 52 is substantially parallel to the longitudinal direction of the semiconductor substrate 12.
As described above, the bump 40 may be made of conductive metal such as solder, copper, aluminum, gold, nickel, silver, palladium, tin, the like, or a combination thereof. In the compression process 50, due to, the malleability of metal, the bump 40 is reformed and may extend laterally. As a result, the bump 40 includes an extension portion 40E. The extension portion 40E is defined as the shape change between the original bump 40 (shown by the dash line) and the reformed bump 40 (shown by the solid line). In some embodiments, the extension portion 40E is evenly distributed on the opposite sides of the bump 40. In the present embodiment, since the second portion 40B is confined by the dielectric layer 34, the extension portion 40E is present only at the first portion 40A of the bump 40.
Referring to 2B, after the compression process 50 (shown in
The first portion 40A and the second portion 40B of the final bump 40 have a third width W3 and a fourth width W4, respectively. The third width W3 is greater than the fourth width W4. Further, due to the extension of the bump, the third width W3 is greater than the first width W1 (the original width of the first portion 40A shown in
On the other hand, the first portion 40A of the bump 40 has a top surface 42 in which the top surface 42 further includes a flat portion 42A and rounded portion 42B. The fiat portion 42A is formed according to the flat surface 52S of the plate 52 shown in
Referring to
Although the present invention has been described in considerable detail with reference to certain embodiments thereof, other embodiments are possible. Therefore, the spirit and scope of the appended claims should not be limited to the description of the embodiments contained herein.
It will be apparent to those skilled in the art that various modifications and variations can be made to the structure of the present invention without departing from the scope or spirit of the invention. In view of the foregoing, it is intended that the present invention cover modifications and variations of this invention provided they fall within the scope of the following claims.
