Patent Application
20240363562
The present application relates to the technical field of chip packaging, in particular a packaging structure for large-size chips adapted to small-size packages and a processing method thereof.
With the development of the semiconductor industry, on one hand, the performance, power and other parameters of chips have been greatly enhanced with the increase in the size of chips; on the other hand, the miniaturization of devices requires the package size of products to be increasingly smaller. There is a certain conflict between the two: how to package a chip with a larger size within a smaller size of package to meet higher performance demands.
Currently, in common packaging structures of products, as shown in
In light of the above problems, the present application provides a packaging structure for large-size chips adapted to small-size packages, allowing for the packaging of larger-size chips within smaller packages without complex via connections.
In a first aspect, the present invention provides a packaging structure for large-size chips adapted to small-size packages, including a frame, a first solder pad cavity and a second solder pad cavity located in the frame, and a chip cavity located above the first solder pad cavity, a channel opened on the proximal side of the frame. The first solder pad cavity partly extends above part of the second solder pad cavity, and is spaced apart from the second solder pad cavity. The first solder pad cavity and the second solder pad cavity are intersected and misaligned. The channel is located on the same left or right side of the two solder pad cavities (on one side of the two solder pad cavities), with the inner wall of the channel being a metallized hole wall.
Preferably, the first solder pad cavity, the second solder pad cavity, and the chip cavity are respectively adapted to the first solder pad, the second solder pad, and the chip.
Optionally, the first solder pad cavity comprises a first pad bottom cavity and a first pad body cavity located above the first pad bottom cavity, wherein the first pad body cavity extends above the second solder pad cavity.
Optionally, the cross-sectional area of the first pad body cavity is greater than the cross-sectional area of the first pad bottom cavity.
Optionally, the second solder pad cavity comprises a second pad bottom cavity and a second pad body cavity located above the second pad bottom cavity, wherein the second pad body cavity is connected to the channel.
Optionally, the first pad body cavity extends above the pad bottom cavity.
Optionally, the first pad body cavity and the second pad body cavity are laterally spaced apart from each other.
Optionally, the first pad body cavity and the second pad bottom cavity are longitudinally spaced apart from each other.
Optionally, an electrical connection wire is provided between the chip cavity and the channel.
In a second aspect, the present invention provides a processing method for the above packaging structure for large-size chips adapted to small-size packages, characterized in comprising the following steps:
Optionally, after the step of processing by electroplating to form the first pad body cavity of the first solder pad cavity, the following step is further comprised:
Forming the second pad body cavity of the second solder pad cavity by laser ablation combined with electroplating processing based on the second solder pad initial cavity.
Optionally, in the step of drilling a hole on the same left or right side of the two solder pads and on the proximal edge of the frame to form a channel, and metallizing the inner wall of the channel to form a metallized hole wall, the inner wall of the channel is subjected to electroless copper plating to form the metallized hole wall.
Optionally, in the step of drilling a hole on the same left or right side of the two solder pads and on the proximal edge of the frame to form a channel, and metallizing the inner wall of the channel to form a metallized hole wall, the inner wall of the channel is subjected to sputtering to form the metallized hole wall.
Optionally, in the step of drilling a hole on the same left or right side of the two solder pads and on the proximal edge of the frame to form a channel, and metallizing the inner wall of the channel to form a metallized hole wall, the inner wall of the channel is subjected to electroplating to form the metallized hole wall.
Optionally, in the step of drilling a hole on the same left or right side of the two solder pads (on one side of the two solder pads) and on the proximal edge of the frame to form a channel, and metallizing the inner wall of the channel to form a metallized hole wall, the channel is shaped by processing a through-hole using a high-power ultraviolet laser cutting process with argon gas as the auxiliary gas.
By providing a channel with a metallized hole wall on the proximal side of the packaging structure, the packaging structure for large-size chips adapted to small-size packages provided in the present application effectively saves internal space within the packaging structure, provides more space for the chip inside the packaging structure, effectively increases the proportion of the chip within the packaging structure to 60%-70% compared to traditional packaging structures, and meets the processing needs for large-size chips adapted to small-size packages.
A detailed description of the embodiments of the present application is provided below by combining with the drawings, which will make the technical solutions of the present application and other advantageous effects obvious.
Wherein the components in the drawings are labeled as:
The present invention provides a processing method for the above packaging structure for large-size chips adapted to small-size packages, comprising the following steps:
In an example, as shown in
As shown in
In an example, in the step of drilling a hole on the same left or right side of the two solder pads (on one side of the two solder pads) and on the proximal edge of the frame to form a channel 50, and metallizing the inner wall of the channel 50 to form a metallized hole wall 51, the inner wall of the channel 50 is subjected to electroless copper plating, sputtering or electroplating to form the metallized hole wall 51.
A clear and complete description of the technical solutions in the examples of the present application is provided below by combining with the drawings in the examples of the present application. Obviously, the described examples are only part of the examples in the present application, rather than all of them. Based on the examples in the present application, the other examples obtained by those skilled in the art without inventive efforts all fall within the protection scope of the present invention.
In the description of the present application, it should be understood that the terms “first” and “second” are used for descriptive purposes only and cannot be understood as indicating or implying the relative importance or implying the number of the indicated technical features. Thus, features limited with “first” and “second” can explicitly or implicitly include one or more of said features. In the description of the present application, the term “multiple” means two or more, unless otherwise specifically limited.
In the description of the present invention, it should be noted that unless otherwise explicitly defined and limited, terms such as “installing” “linking” and “connecting” should be broadly understood. For example, they can refer to fixed connections or detachable connections, or integral connections; they can be mechanical connections or electrical connections or can communicate with each other; they can be direct connections or indirect connections through an intermediate medium, and can be internal connections between two elements or interactions between two elements. For those ordinarily skilled in the art, they can understand the specific meanings of the above terms in the present application according to specific circumstances.
The following disclosure provides many different embodiments or examples to realize the different structures of the present application. To simplify the disclosure of the present application, specific examples of components and settings are described below. Of course, they are merely illustrative and are not intended to limit the present application. Furthermore, reference numbers and/or reference letters may be repeated in different examples of the present application. Such repetition is for the purpose of simplification and clarity, and does not indicate the relationship between the various embodiments and/or settings under discussion. Additionally, the present application provides examples of various particular processes and materials, but those ordinarily skilled in the art can realize the application of other processes and/or the use of other materials.
It is necessary to elaborate on the background for the creation of the invention of the present application before introducing the technical solutions of the present application.
With the development of the semiconductor industry, the performance, power and other parameters of chips are continuously improved and the sizes of chips also get larger and larger. However, with the miniaturization of electronic devices, there is a certain conflict between the increasing size of chips and the requirement for smaller package size. Therefore, it is necessary to solve the problem of packaging a larger-size chip within a smaller package.
In light of this, the present application provides a packaging structure for large-size chips adapted to small-size packages, which can package larger-size chips under the premise of reducing current package size.
According to
Wherein the first solder pad cavity 12, the second solder pad cavity 22, and the chip cavity 41 are respectively used to place the first solder pad, the second solder pad, and the chip.
Wherein the metallized hole wall 51 is defined as the inner wall of the channel 50, which is made of metallic materials. In other examples of the present application, the inner wall of the channel 50 only needs to have electrical conductivity.
Wherein the proximal side refers to the area close to the outer edge of the packaging structure 100.
As stated above, according to the present application, the intersection and misalignment are defined as two solder pad cavities in non-contact intersection in the horizontal direction and being spaced apart in the vertical direction. More exactly speaking, the first solder pad cavity 12 partly extends above part of the second solder pad cavity 22, and is spaced apart from the second solder pad cavity 22.
As stated above, “large-size” in the large-size chips adapted to small-size packages refers to the size relative to the package in the prior art; the “small-size” refers to the size relative to the chip in the package in the prior art. They are comparisons of sizes for the same object, not comparisons between the size of the package and the size of the chip.
By providing a channel 50 with a metallized hole wall 51 on the proximal side of the packaging structure 100, the packaging structure for large-size chips adapted to small-size packages provided in the present application realizes electrical connection between the solder pad and chip within the package through the channel, replaces the electrical connection wiring manners of multi-layer wiring and via connection, effectively saves internal space within the packaging structure 100, provides more space for the chip inside the packaging structure 100, effectively increases the proportion of the chip within the packaging structure 100 to 60%-70% compared to traditional packaging structures 100, and meets the processing needs for large-size chips adapted to small-size packages.
In an example, the channel 50 can be realized as two channels, each positioned on either side of the first and second solder pads, and both located near the proximal side of the packaging structure 100.
Multiple solder pads and chips are electrically connected through the channel 50 with metallized hole wall 51. The chips are electrically connected to the metallized hole wall 51, and the metallized hole wall 51 is electrically connected to the second solder pad. Compared to the existing complex multi-layer wiring method, the processing technology is simpler, does not require multi-layer wiring, is more efficient and has a lower production cost. The packaging structure for large-size chips adapted to small-size packages provided in the present application realizes the electrical connection between the chips and multiple solder pads through the electrical connection between the metallized hole wall 51 of the channel 50 on the proximal side of the packaging structure 100. The structure is simple and compact, with a rational and effective design.
As stated above, the proportion refers to the ratio of the main surface area of the chip to the cross-sectional area of the packaging structure 100.
In an example, the first solder pad cavity 12 comprises a first pad bottom cavity 121 and a first pad body cavity 122 located above the first pad bottom cavity 121, wherein the first pad body cavity 122 extends above the second solder pad cavity 22.
In an example, the first pad body cavity 122 part extends above the second solder pad cavity 22, and the cross-sectional area of the first pad bottom cavity 121 is smaller than that of the first pad body cavity 122. Compared to the existing chip packaging structure 100, the arrangement of equal cross-sectional areas of the pad bottom cavity and the pad body cavity of the first solder pad cavity 12 saves space occupied by the pad bottom. At the same time, the larger first pad body cavity 122 provides a sufficient mounting surface for soldering and mounting larger chips on the top surface of the first solder pad. The first pad body cavity 122 partly extends above the second solder pad cavity 22, which effectively reduces the overall width of the first solder pad, the second solder pad and the chip, and is conducive to the realization of the miniaturization of the overall structure of the packaging structure 100.
In an example, the cross-sectional area of the first pad body cavity 122 is greater than the cross-sectional area of the first pad bottom cavity 121.
In an example, according to the requirement for the size of the chip in the packaging structure 100, the second solder pad cavity 22 can be configured with the pad bottom cavity and the pad body cavity being equally wide and straight, or it can be arranged with the pad bottom cavity and the pad body cavity being unequal in width with uneven edges. When the second solder pad cavity 22 is arranged with the pad bottom cavity and the pad body cavity being equally wide and edges aligned, it is suitable for the first pad body cavity 122 to extend more above the second solder pad cavity 22 to provide a larger area for chip mounting. When the second solder pad cavity 22 is configured to have the pad bottom cavity and the pad body cavity of unequal width or with uneven edges, the second pad cavity 22 includes a second pad bottom cavity 221 and a second pad body cavity 222 located above the second pad bottom cavity 221. The second pad body cavity 222 is connected to the channel 50, and the first pad body cavity 122 partly extends above the second pad bottom cavity 221. This configuration is suitable for mounting relatively small chips. Meanwhile, the second pad body cavity 222 is interconnected with the metallized hole wall 51 of the channel 50, which is used for the electrical connection between the second solder pad and the metallized hole wall 51.
In an example, the first pad body cavity 122 and the second pad body cavity 222 are laterally spaced apart from each other; and the first pad body cavity 122 and the second pad bottom cavity 221 are longitudinally spaced apart from each other.
In a more concrete example, considering parameters such as the maximum particle size φ of the conventional plastic packaging material EMC filler, and the minimum creepage distance L of the product design, the lateral spacing X≥Min. (φ, L), and the longitudinal spacing Y≥Min. (φ, L).
In an example, an electrical connection wire 42 is provided between the chip cavity 41 and the channel 50, which is used for electrically connecting the chip and the metalized hole wall 51 of the channel 50.
Based on the same inventive concept, the present invention provides a processing method for the above packaging structure for large-size chips adapted to small-size packages, comprising the following steps:
In an example, as shown in
As shown in
In an example, in the step of drilling a hole on the same left or right side of the two solder pads (on one side of the two solder pads) and on the proximal edge of the frame to form a channel 50, and metallizing the inner wall of the channel 50 to form a metallized hole wall 51, the inner wall of the channel 50 is subjected to electroless copper plating, sputtering or electroplating to form the metallized hole wall 51.
In an example, in the step of drilling a hole on the same left or right side of the two solder pads (on one side of the two solder pads) and on the proximal edge of the frame to form a channel 50, and metallizing the inner wall of the channel 50 to form a metallized hole wall 51, the channel 50 is shaped by drilling a hole using an ultraviolet laser cutting process with argon gas as the auxiliary gas.
Since multiple chips and multiple pads are obtained from a single PCB board during production and processing, to obtain the packaging structure for large-size chips adapted to small-size packages in the present application, it is necessary to cut and process the entire PCB to obtain multiple packaging structures 100. Therefore, in an example, the processing method provided by the present application also includes a cutting process, which specifically comprises the following step:
Arranging and cutting the packaging structure 100 on the PCB board as shown in
In an example, as shown in
In an example, as shown in
In an example, to avoid hole-copper separation in channel 50 during cutting, a high-power ultraviolet (UV) laser cutting process with argon gas as the auxiliary gas can be used for cutting and processing. High-power ultraviolet laser can achieve precise and fine cutting of thin copper substrates, and has the advantages of narrow kerfs, slight thermal zone impacts, and high-quality kerfs, etc.
The chip and wiring structure inside the single packaging structure 100 are shown in FIGS. 3, 13, and 14. Depending on requirements for the electrical connection in the packaging structure 100, the left end surface of the first solder pad can be implemented as in electrical connection not in contact with the metallized hole wall 51 of the left channel 50, as shown in
In an example, the proportion of the chip itself in the package can be further increased by saving the area on the chip side of the package. That is, by using the single-sided drilling interconnection structure of the packaging structure 100, the proportion of the chip itself in the package can be further increased, up to nearly 80 to 90%.
The above examples are merely better embodiments of the present invention, but the protection scope of the present invention is not limited to this. Any change or replacement easily conceived by persons skilled in the art within the technical scope disclosed by the present invention should be covered within the protection scope of the present invention
By providing a channel with a metallized hole wall on the proximal side of the packaging structure, the packaging structure obtained by a processing method for the above packaging structure for large-size chips adapted to small-size packages, comprising the following steps:
| Number | Date | Country | Kind |
|---|---|---|---|
| 202210099768.3 | Jan 2022 | CN | national |
The present application is a Continuation Application of PCT Application No. PCT/CN2023/072053 filed on Jan. 13, 2023, which claims the benefit of Chinese Patent Application No. 202210099768.3 filed on Jan. 27, 2022. All the above are hereby incorporated by reference in their entirety.
| Number | Date | Country | |
|---|---|---|---|
| Parent | PCT/CN2023/072053 | Jan 2023 | WO |
| Child | 18764147 | US |
