1. Field of the Invention
The present invention relates to a patterning method, an exposure system, a computer readable storage medium, and a method of manufacturing a device.
2. Description of the Related Art
Recently, as semiconductor integrated circuits such as ICs and LSIs, and liquid crystal panels have become smaller in size and higher in integration degree, exposure apparatuses such as semiconductor exposure apparatuses have become higher in resolution and performance. In overlaying originals such as masks and reticles on substrates such as semiconductor substrates and glass substrates, in particular, a technique for overlaying originals on substrates on the order of nanometers is expected to be developed.
An overlay inspection and optimization method in an exposure method will be described next.
The measurement result obtained by the overlay inspection apparatus is used for not only the above inspection of a product but also for overlay optimization. An alignment offset (correction value) which corrects the overlay error measured by the overlay inspection apparatus is calculated and used as an offset when exposure is performed in a subsequent semiconductor manufacturing process. In this manner, feeding back overlay error caused in a previous manufacturing step will optimize an overlay.
On the other hand, with miniaturization of semiconductor integrated circuits and the like, techniques of forming finer patterns have been proposed. As one such technique, there is available double patterning (to be referred to as DP hereinafter), which is a technique of forming a desired pattern by performing exposure and edge formation twice each, by using different originals.
An outline of DP will be described with reference to
A major characteristic of this method is that when overlay is properly performed in two exposure processes, a pattern line width L becomes uniform, as shown in
As described above, in manufacturing semiconductor integrated circuits and liquid crystal panels, an original and a substrate are accurately overlaid by using the method including global alignment. In addition, overlay inspection and optimization are performed by using an overlay inspection apparatus. These make it possible to achieve a sufficiently high overlay accuracy.
In DP as a method of miniaturizing semiconductor integrated circuits and the like, using the method shown in
The present invention reduces variations in the line widths of patterns in patterning that forms the edge of a pattern on a substrate in two steps.
According to an aspect of the present invention, there is provided a method of forming a pattern on a first substrate by forming a first edge of the pattern on the first substrate through formation of a first resist pattern by coating the first substrate with a first resist, exposing the first resist to light, and developing the first resist, forming a second edge of the pattern on the first substrate through formation of a second resist pattern by coating the first substrate with a second resist, exposing the second resist to light, and developing the second resist, the method comprising measuring a line width of the pattern formed on the first substrate, and determining, based on the measured line width, a correction value which corrects information for positioning the first substrate in the forming of the second edge so as to reduce variations in the line width, wherein a second edge is formed on a second substrate when positioning the second substrate in accordance with information corrected by using the determined correction value.
Further features of the present invention will become apparent from the following description of exemplary embodiments with reference to the attached drawings.
If the line width of the pattern has not reached the standard value of a product, the substrate or a lot including the substrate is determined as a defective product. A substrate or lot determined as a defective product is subjected to a rework process, whereas a substrate or lot determined as a non-defective product proceeds to the next manufacturing step. The measurement result obtained by the measurement device 5 is used for not only the above determination of a product but also overlay optimization. A determination unit 6 which determines a correction value (alignment offset) (to be described later) determines, based on the line width measured by the measurement device 5, an alignment offset as a correction value which corrects information for positioning a substrate in exposure for the formation of a second edge. The determined alignment offset is used as an offset (correction value) at the time of exposure in the same step in subsequent patterning. Positioning (overlay) of the substrate is optimized by feeding back the correction value based on the line width of the pattern generated in the previous step. This optimizes the positioning of the substrate based on the line width of the pattern.
An example of an exposure system 1 according to the present invention will be described with reference to
The exposure apparatus 4 exposes the substrate to light while overlaying a pattern of an original on the substrate based on the alignment offset sent from the controller 3. The measurement device 5 is, for example, a known scanning electron microscope with a length measurement function (a length measurement SEM or CD-SEM). The scanning electron microscope with the length measurement function can acquire an electron beam image of a minute region of the substrate and measure the line width of the pattern formed on the substrate. The measurement device 5 measures the line width of a pattern of a resist (photoresist) on a substrate which is developed by the developing apparatus 7a after being exposed to light by the exposure apparatus 4, and the line width of the pattern having undergone a process such as etching based on the resist pattern. The determination unit 6 calculates and determines an alignment offset which corrects overlay at the time of exposure (an offset at the time of exposure) based on the line width of the pattern measured by the measurement device 5. The determination unit 6 can be implemented by a known computer.
This embodiment will exemplify the exposure system 1 as a system in which the exposure apparatus 4, the measurement device 5, the determination unit 6, and the like are connected to each other via the internal communication network 2. The exposure apparatus 4 in the exposure system 1 can be an exposure apparatus including a measurement unit and a determination unit in addition to an exposure unit.
An example in which the present invention is applied to a method of forming a pattern on a substrate by double patterning (DP) will be described in detail next.
In step S101, the coating apparatus 7d coats the substrate with the first resist. Step S102 is the first exposure step. In this step, the exposure apparatus 4 exposes the first resist to light. Step S103 is the first developing step. In this step, the developing apparatus 7a forms the first resist pattern by developing the first resist exposed to light in the first exposure step. “Step A” in
Step S105 is the first etching step. The etching apparatus 7b forms a first edge of the pattern by etching a layer 1002, on which the pattern is to be formed, by using the first resist pattern developed in the first developing step, as indicated by “step B” in
In step S106, the coating apparatus 7d applies (i.e., coats substrate) the second resist on the substrate on which the first edge is formed. Step S107 is the second exposure step (i.e., perform second exposure). In this step, the exposure apparatus 4 exposes the second resist to light. In the second exposure step, the alignment offset which has already been determined by the determination unit 6 is transferred to the exposure apparatus 4, which in turn exposes the substrate to light while positioning it upon reflection of the transferred alignment offset. Step S108 is the second developing step (i.e., perform second development). In this step, the developing apparatus 7a forms the second resist pattern by developing the second resist. “Step C” in
Step S109 is the second etching step. The etching apparatus 7b forms a second edge of the pattern by etching the layer 1002, on which the pattern is to be formed, by using the second resist pattern developed in the second developing step, as indicated by “step D” in
Step S110 is the line width inspection step. In this step, the measurement device 5 measures the line width of the pattern formed on the substrate through the first and second steps, and the determination unit 6 inspects the measured line width. The determination unit 6 calculates and determines an alignment offset which corrects information for positioning the substrate in the second exposure step in subsequent DP. Using the alignment offset calculated and determined in the line width inspection step in this manner for DP for another substrate will optimize overlay and improve the uniformity of pattern line widths.
The details of the line width inspection step of step S110 will be described next with reference to
Step S202 is the line width determination step, in which the determination unit 6 calculates uniformity from a plurality of measured values obtained in step S201, and determines whether the uniformity falls within a predetermined standard value. When determining that the uniformity of the line widths has not reached the standard value, the determination unit 6 determines that the wafer or the lot including the wafer is a defective product. A wafer or lot determined as a defective product is subjected to a rework process (not shown). A wafer or lot determined as a non-defective product proceeds to the next manufacturing step.
Step S203 is the determination step, in which the determination unit 6 calculates and determines an alignment offset so as to reduce variations in line width based on the plurality of measured values obtained in step S201. In the determination step, the determination unit 6 calculates a line width error from each measured value first. Assume that in this case, as shown in
An example of a statistical process will be described in detail next, in which the determination unit 6 performs statistical calculation as in the method used in global alignment, and statistically processes the calculated line width error, thereby calculating an alignment offset as an overlay correction value for correcting a line width error. The statistical process is constituted by the following two processes. In the first statistic process, the determination unit 6 calculates line width error statistics in each measurement shot 303 based on a line width error in each measurement shot 303. In the second statistical process, the determination unit 6 calculates (estimates) the line width error statistics of all the shots from the line width error statistics in each measurement shot 303 calculated in the first statistical process, and determines the calculated statistics as an alignment offset.
The first statistical process will be described first. In the first statistical process, the determination unit 6 approximately assumes that a designed value (Xi, Yi) of a measurement position at shot coordinates and a measured line width error (Px, Py) approximately have the relationship represented by linear polynomials (1) and (2) given below. The determination unit 6 calculates, from these polynomials, a shift component (Sx[i], Sy[i]), a magnification component (Mx[i], My[i]), and a rotation component (Rx[i], Ry[i]) as the statistics of line width errors in a selected measurement shot i as the coefficients of these polynomials. More specifically, the determination unit 6 calculates the statistics of line width errors in the measurement shot i as the coefficients of polynomials (1) and (2) by a known least squares method using measured line width errors.
P
x(X,Y)=Sx[i]Mx[i]X+Rx[i]Y (1)
P
y(X,Y)=Sy[i]My[i]X Ry[i]Y (2)
The second statistical process will be described next. The determination unit 6 calculates the statistics of line width errors in all of a plurality of shot regions from the statistics of the line width errors in each measurement shot i obtained in the first statistical process.
The determination unit 6 assumes that a designed position (x, y) at the substrate coordinates of the center of an arbitrary shot region and a shift component (Sx, Sy), magnification component (Mx, My), and rotation component (Rx, Ry) in the shot region approximately have the relationship represented by arbitrary-order polynomials (3) to (8). The determination unit 6 obtains polynomials (3) to (8) for calculating the statistics of line width errors in all shot regions. More specifically, the determination unit 6 calculates polynomial coefficients asx to jsx, asy to jsy, amx to jmx, amy to jmy, arx to jrx, and ary to jry based on the line width errors Sx[i], Sy[i], Mx[i], My[i], Rx[i], and Ry[i] in each measurement shot i. The determination unit 6 calculates coefficients of polynomials (3) to (8) by using a known least squares method.
S
x(xi,yi)=asx+bsxxi+csxyi+dsxxi2+esxxiyi+fsxyi2+gsxxi3+hsxxi2yi+isxxiyi2+jsxyi3 . . . (3)
S
y(xi,yi)=asy+bsyxi+csyyi+dsyxi2+esyxiyi+fsyyi2+gsyxi3+hsyxi2yi+isyxiyi2+jsyyi3 . . . (4)
M
x(xi,yi)=amx+bmxxi+cmxyi+dmxxi2+emxxiyi+fmxyi2+gmxxi3+hmxxi2yi+imxxiyi2+jmxyi3 . . . (5)
M
y(xi,yi)=amy+bmyxi+cmyyi+dmyxi2+emyxiyi+fmyyi2+gmyxi3+hmyxi2yi+imyxiyi2+jmyyi3 . . . (6)
R
x(xi,yi)=arx+brxxi+crxyi+drxxi2+erxxiyi+frxyi2+grxxi3+hrxxi2yi+irxxiyi2+jrxyi3 . . . (7)
m
x(xi,yi)=ary+bryxi+cryyi+dryxi2+eryxiyi+fryyi2+gryxi3+hryxi2yi+iryxiyi2+jryyi3 . . . (8)
Finally, the determination unit 6 calculates a statistics in each shot region by substituting the substrate coordinate positions of the center of each shot region into polynomials (3) to (8) whose coefficients have been calculated, and determines the calculated statistics as an alignment offset for an overlay correction value.
The above embodiment has exemplified the case in which resist pattern overlay is inspected by performing overlay inspection after the first developing step. However, the overlay of patterns formed on the substrate may be inspected by performing the overlay inspection step after the first etching step. The embodiment has also exemplified the case in which the line width of a formed pattern is inspected by performing line width inspection after the second etching step. However, the line width of a resist pattern on the substrate may be inspected by performing line width inspection after the second developing step.
As an example of calculating an alignment offset, this embodiment has exemplified the method of calculating a correction value based on a shift component, a magnification component, and a rotation component in each shot region. It is possible to use, as a simpler method, a method of calculating at least one of a shift component, a magnification component, and a rotation component, for example, using only a shift component, in each shot region as a correction value by using a different statistical process than that used in wafer alignment. As described above, the determination step is not limited to the above statistical process and the correction value calculated in the above manner.
As described above, this embodiment can be expected to improve the uniformity of the line widths of patterns by performing overlay optimization based on the line widths of the patterns formed in DP.
In addition, using a program that stores the contents of step S203 can cause the computer in the exposure system to execute processes such as calculating and determining an alignment offset based on the information generated by the exposure system, for example, the measured values of line widths.
In addition, devices can be manufactured by using the exposure system according to this embodiment. In this case, devices are manufactured through a step of forming a pattern on a substrate by using the above exposure system and other known steps. The devices can be semiconductor integrated circuit devices, liquid crystal display devices, and the like. The substrate can be a wafer, a glass plate, and the like. The known steps can be, for example, oxidation, film formation, deposition, doping, planarization, dicing, bonding, and packaging steps.
While the present invention has been described with reference to exemplary embodiments, it is to be understood that the invention is not limited to the disclosed exemplary embodiments. The scope of the following claims is to be accorded the broadest interpretation so as to encompass all such modifications and equivalent structures and functions.
This application claims the benefit of Japanese Patent Application No. 2008-275924, filed Oct. 27, 2008, which is hereby incorporated by reference herein in its entirety.
Number | Date | Country | Kind |
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2008-275924 | Oct 2008 | JP | national |