Patent Application
20230223200
N/A
The present disclosure addresses fabrication of a capacitor film stack within a printed circuit board (PCB), which enables multiple discrete capacitors to be formed within the capacitor film stack. Fabrication of the capacitor film stack includes using two different types of materials for the anodes and cathodes of the capacitor film stack. The use of different types of materials allows for selective etching and the eventual connection of an anode without the connection of a corresponding cathode at a given location and conversely, connection of a cathode without the connection of a corresponding anodes at a different location.
The present disclosure describes deploying capacitor film stacks within the layers of a printed circuit board (PCB). Both a stack formed from large continuous films and stacks formed from segmented films are disclosed. Both of these configurations reduce the need for discrete capacitor devices and improve the performance of the PCB assembly.
Various embodiments of the present disclosure teach a capacitor constructed with electrode conductors formed with at least two different materials. By deploying two materials, one for the anodes and another for the cathodes, the conductors can be selectively etched for ease of fabrication and selective connection.
The accompanying drawings, where like reference numerals refer to identical or functionally similar elements throughout the separate views, together with the detailed description below, are incorporated in and form part of the specification, and serve to further illustrate embodiments of concepts that include the claimed disclosure, and explain various principles and advantages of those embodiments.
The methods and systems disclosed herein have been represented where appropriate by conventional symbols in the drawings, showing only those specific details that are pertinent to understanding the embodiments of the present disclosure so as not to obscure the disclosure with details that will be readily apparent to those of ordinary skill in the art having the benefit of the description herein.
The PCB 7 utilizes circuit traces 8 to make electrical connections from one component to another. The circuit traces 8 are typically located on the top and bottom sides of the PCB 7. It is common to utilize many layers of substrates and many layers of circuit traces 8 to connect the circuit devices. To facilitate the connections between the multiple layers, PCB's often utilize vias 9. The vias 9 are used to electrically connect traces 8 from one PCB layer to another. Conductive pads 10 are used to facilitate the mechanical and electrical connections of the electronic devices to the circuit traces 9. Some complex boards may have over ten layers of substrates and traces. Some of the layers may include a “ground plane” or a “power plane” (not shown). The power or ground planes provide efficient distribution of either power or ground connections to the various components. The planes may be connected by the vias or component leads as prescribed by the circuit design and the configuration of the circuit devices in a given PCB. The planes offer a low impedance connection between devices. Most often the ground plane is spaced from the power plane with “core” or “prepreg” substrate materials. The substrates are typically fabricated from a fiberglass epoxy material, and range in thickness from 50 um to over 100 um. The substrate material used between ground or power planes do have dielectric properties and are not conductive. The sandwich of the power plane and the ground plane with the dielectric core of the substrate creates a small amount of capacitance.
Capacitance in a device allows for the storage of electrical charge. The ability to store charge is measured in Farads. A small PCB assembly with high-speed ICs or power regulation ICs would more than likely require discrete capacitors that would be assembled to the PCB. The discrete capacitors might need to provide hundreds or thousands of micro-Farads of capacitance in multiple locations throughout the PCB assembly. Small capacitors may only have a fraction of a micro-Farad in capacitance. Larger capacitors may have a Farad or more. The equation for capacitance is based on the geometry and physical characteristics of a capacitor (as shown in
C (Farads)=e0×k×[(L×W)/T]×Nc
e0: The permittivity of free space, a physical constant=8.85×10−12 m−3 kg−1 s4 A2
k: The dielectric constant of the dielectric layers 22, unitless
L: The length of the layers in meters
W: The width of the layers in meters
T: The thickness of the dielectric layer in meters
Nc: number of active dielectric layers
It should be noted that for efficient PCB construction, it is generally desirable to have capacitors with a large amount of capacitance (Farads) within as small a package as is possible.
The permittivity of free space is a physical constant and is the same for all capacitors. The dielectric constant, k, is a property of the dielectric material used in the dielectric layers. Dielectric constants k for dielectric materials range from around 4 for silicon dioxide (SiO2) to greater than 2000 for strontium titanium oxide. One skilled in the art of dielectric materials would be readily able to engineer the selection of the dielectric for a particular application of a capacitor. It is generally preferable for the geometry of the capacitor to be minimized. Length, width, and thickness should be as small as possible. Larger and thicker capacitors not only require more real estate within a PCB but utilize more material, which increases cost. The number of layers, Nc, also affects the cost and to a lesser degree size of the component.
An example calculation of the capacitance created by the dielectric between a current art ground plane and power plane is; for k=10, L=0.1 m, W=0.1 m, t=0.0001 m (100 micrometers) and n=1, the capacitance is 8.85e-9 Farads (8.85 nanoFarads). If the thickness is reduced to t=0.00000001 m (10 nanometers) and the number of layers increased to n=50 the capacitance would be 4.42e-3 (4,420 microFarads or 4,420,000 nanoFarads), an increase of 500,000×. This increase in capacitance can be realized by deploying the disclosed invention within a PCB.
As mentioned above, discrete capacitors are a type of component that is commonly incorporated on a PCB. The PCB assembly disclosed herein does not show any discrete capacitors, as the function of discrete capacitor components is integrated within the layers of the PCB 7.
Referring again to
Referring now to
The capacitor film stack 22 is formed from a plurality of sandwiched layers including in order a ground metal film 31, a dielectric film 30, a voltage metal film 32, and another dielectric film 30. This pattern of layers can be repeated many times.
Preferred thicknesses of the dielectric films range from a few nanometers to approximately a micron. From the equation above and the examples disclosed above, it is apparent that a thinner dielectric layer provides greater capacitance. There are two limiting factors in reducing thickness; manufacturability and operating voltage. Current PCB substrate layers are typically not less than 50 micrometers in thickness. Some advanced materials allow substrates to be made that are slightly thinner than 1 micron. With current semiconductor manufacturing processing, dielectric films that are one atomic layer thick can be produced. These films are <1 nanometer thick. Using these significantly thinner films as the capacitor film 30 greatly increases the resultant capacity. There is a minimum thickness required to ensure that the dielectric film 30 does not break down due to the applied voltage across it. Generally, for SiO2 one nanometer of thickness is required for every volt applied across the dielectric. The applied voltage is the potential difference between the voltage metal film 32 and the ground metal film 31. The operating voltage of many of today's high-speed electronic devices and circuits range from slightly less than one volt to up to 6 volts. With the use of known semiconductor processes and related types of processes, devices utilizing the technology disclosed herein can be fabricated with dielectric films much thinner than those of the current art. The use of thousands or even hundreds of thousands of nanometers of dielectric material used in current art can be replaced with only a few nanometers of films constructed with the technology disclosed herein. The metal film layers, ground and voltage, are driven by manufacturability and electrical performance requirements. With the current art, the thicknesses of those layers range from a few microns to tens of microns in thickness. With the technology discussed herein, the thickness of the metal films can be greatly reduced, to tens of nanometers in thickness. The thickness limitations would be established by the electrical requirements of the subject circuit.
The materials used for the voltage metal films 32 and for the ground metal films 31 are distinctly different. This allows for selective etching of the layers, to provide necessary electrical connection points. In some embodiments, the ground metal films 31 are etched back with an etchant that only attacks the ground metal films 31, and is non-reactive toward the voltage metal films 32 and the dielectric films 30.
The lower left corner of
Referring now to the upper right corner of
The metal films can be etched back from the isolation ring 64 to provide the desired isolation. The bottom film 21′ does connect the main capacitor area 62 with the electrically isolated capacitor 60. As mentioned above, the bottom film 21′ is not electrically conductive. Depending on manufacturing requirements, the bottom film 21′ may or may not be present.
In
As demonstrated by the calculations above, the amount of capacitance created by the capacitor stack 13 can be significant, in many cases more than is required for the task at hand. Most PCB assemblies employ discrete capacitors. Electronically isolated capacitors 60 can serve the purpose of current art discrete capacitor devices. By adjusting the size of the area of the electronically isolated capacitor 60, the capacitance can be adjusted for a specific purpose. The capacitor stack 13′ is shown with only two electrically isolated capacitors 62. In most assemblies, many more capacitors 62 would be deployed, from hundreds to thousands.
Referring to
A preferred process to manufacture the preferred embodiment would be to:
1. Deposit a film stack of alternating layers of dielectric, and two different types of metals on top of the bottom substrate. This stack may have tens or hundreds of layers. A top substrate may be added for manufacturability and protection but is not required.
2. Create holes in the stack created in step 1. These holes would correspond to the locations of the vias. These holes would be slightly larger than the metal vias created later in the process.
3. Selectively etch back the voltage films and ground films with different chemistries. A chemistry that etches the ground metal would be applied to the holes that require voltage connection. A different chemistry that etches the voltage metal would be applied to the holes that require ground connection. The feed through holes would be etched with both chemistries.
4. Plate the hole with metal to connect the voltage film and the ground films.
5. Assemble the film within or to other PCB layers. Create holes in the assembly the same size as or slightly smaller than the plated metal in step 3.
6. Finish the fabrication with current PCB fabrication processes.
The description of the present disclosure has been presented for purposes of illustration and description, but is not intended to be exhaustive or limited to the present disclosure in the form disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the present disclosure. Exemplary embodiments were chosen and described in order to best explain the principles of the present disclosure and its practical application, and to enable others of ordinary skill in the art to understand the present disclosure for various embodiments with various modifications as are suited to the particular use contemplated.
While this technology is susceptible of embodiment in many different forms, there is shown in the drawings and will herein be described in detail several specific embodiments with the understanding that the present disclosure is to be considered as an exemplification of the principles of the technology and is not intended to limit the technology to the embodiments illustrated.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the technology. As used herein, the singular forms “a”, “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises” and/or “comprising,” when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.
It will be understood that like or analogous elements and/or components, referred to herein, may be identified throughout the drawings with like reference characters. It will be further understood that several of the Figures are merely schematic representations of the present disclosure. As such, some of the components may have been distorted from their actual scale for pictorial clarity.
Reference throughout this specification to “one embodiment” or “an embodiment” means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the present invention. Thus, the appearances of the phrases “in one embodiment” or “in an embodiment” or “according to one embodiment” (or other phrases having similar import) at various places throughout this specification are not necessarily all referring to the same embodiment. Furthermore, the particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. Furthermore, depending on the context of discussion herein, a singular term may include its plural forms and a plural term may include its singular form. Similarly, a hyphenated term (e.g., “on-demand”) may be occasionally interchangeably used with its non-hyphenated version (e.g., “on demand”), a capitalized entry (e.g., “Software”) may be interchangeably used with its non-capitalized version (e.g., “software”), a plural term may be indicated with or without an apostrophe (e.g., PE's or PEs), and an italicized term (e.g., “N+1”) may be interchangeably used with its non-italicized version (e.g., “N+1”). Such occasional interchangeable uses shall not be considered inconsistent with each other.
It is noted at the outset that the terms “coupled,” “connected”, “connecting,” “electrically connected,” etc., are used interchangeably herein to generally refer to the condition of being electrically/electronically connected. Similarly, a first entity is considered to be in “communication” with a second entity (or entities) when the first entity electrically sends and/or receives (whether through wireline or wireless means) information signals (whether containing data information or non-data/control information) to the second entity regardless of the type (analog or digital) of those signals. It is further noted that various Figures (including component diagrams) shown and discussed herein are for illustrative purpose only, and are not drawn to scale.
While specific embodiments of, and examples for, the system are described above for illustrative purposes, various equivalent modifications are possible within the scope of the system, as those skilled in the relevant art will recognize. For example, while processes or steps are presented in a given order, alternative embodiments may perform routines having steps in a different order, and some processes or steps may be deleted, moved, added, subdivided, combined, and/or modified to provide alternative or sub-combinations. Each of these processes or steps may be implemented in a variety of different ways. Also, while processes or steps are at times shown as being performed in series, these processes or steps may instead be performed in parallel, or may be performed at different times.
