Photolithography is utilized in the fabrication of semiconductor devices to transfer a pattern onto a wafer. Based on various integrated circuit (IC) layouts, patterns are transferred from a photomask to a surface of the wafer. The photomasks, also called reticles, are made of quartz or glass with one or more metallic materials deposited on one side to prevent light penetration. As dimensions decrease and density in IC chips increases, resolution enhancement techniques, such as optical proximity correction (OPC), off-axis illumination (OAI), double dipole lithography (DDL) and phase-shift mask (PSM), are developed to improve depth of focus (DOF) and therefore to achieve a better pattern transfer onto the wafer.
Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It is noted that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.
The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components, values, operations, materials, arrangements, or the like, are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. Other components, values, operations, materials, arrangements, or the like, are contemplated. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.
Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.
As semiconductor device feature sizes have decreased to be smaller than a wavelength of light used in photolithography processes, the ability of manufacturing the minimum feature size, also called critical dimensions (CD), become sensitive to optical fringing of light passing through a photomask or a reticle. Because of constructive and destructive interference effects, also referred to as diffraction, photoresist at an edge of a defined pattern is exposed under undesired light, resulting in a distortion in a pattern transferred to a wafer. In order to enhance a resolution during the image transfer, a phase shift mask (PSM) is used to shift a phase of selected light passing through the photomask or the reticle by π (180 degrees), thereby the undesired light is scattered or offset by the destructive interference. Removing the undesired light helps to improve the precision of the image transfer. Typically, the PSM is categorized into an alternating PSM or an attenuated PSM. The alternating PSM induces the phase shift of light by adjusting a thickness of a clear region. The attenuated PSM allows a small percentage of light to penetrate through a dark region. In some instances, each PSM includes molybdenum silicide (MoSi) as a phase shifter. Defects such as crystal haze and particles are generated after a series process including UV exposure, baking and cleaning by sulfuric acid and ammonia, thereby causing a greater CD error and decreasing manufacturing yield.
In some embodiments, in order to reduce a growth of crystal haze, a combination of a semiconductor layer, such as silicon, and a dielectric layer, such as silicon dioxide, is used in place of MoSi. In some embodiments, the phase shifter includes from 2 to 12 semiconductor/dielectric layer pairs. Based on a control of etch selectivities, such a phase shifter has an improved profile during an etch process and a reduced CD loss during the photolithography process. In some embodiments, a bottom layer of the phase shifter has a relatively lower etch rate during the etch process. As a result, an unetched protrusion is formed between the phase shifter and a transparent substrate. The unetched protrusion enhances a physical damage resistance of the phase shifter to a subsequent clean process.
In operation 114, at least one first dielectric layer and at least one second semiconductor layer are deposited, in an alternating fashion, over the first semiconductor layer. When more than one second semiconductor layer is deposited, in some embodiments, each of the second semiconductor layers includes the same material. In some embodiments, at least one second semiconductor layer is different from the first semiconductor layer or another second semiconductor layer. In some embodiments, each of the at least one second semiconductor layer includes the same material as the first semiconductor layer. For example, the first semiconductor layer includes silicon and the at least one second semiconductor layer includes germanium. In some embodiments, the formation process of the second semiconductor layer includes plasma-enhanced CVD (PECVD), high-density plasma CVD (HDPCVD), low pressure CVD (LPCVD) or another suitable process.
In some embodiments, the at least one first dielectric layer includes a single dielectric layer. In some embodiments, the at least one first dielectric layer includes multiple dielectric layers adjacent one another, for example, a silicon nitride layer and a silicon oxide layer without an intervening semiconductor layer. In some embodiments, the formation of the at least one first dielectric layer includes the same deposition process as that used to form the second semiconductor layer. In some embodiments, the formation of the at least one first dielectric layer includes a different deposition process from that used to form the second semiconductor layer. For example, the first dielectric layer uses a CVD process and the second semiconductor layer uses an atomic layer deposition (ALD) process. In some embodiments, each of the at least one first dielectric layer is formed by the same process. In some embodiments, at least one of the first dielectric layer is formed by a different process from another. In some embodiments, each of the at least one first dielectric layer has a same material. In some embodiments, at least one of the at least one first dielectric layer has a different material from another of the at least one first dielectric layer. In some embodiments, each of the at least one first dielectric layer is a single dielectric layer. In some embodiments, each of the at least one first dielectric layer includes multiple dielectric layers adjacent one another. In some embodiments, at least one of the at least one first dielectric layer is a single dielectric layer and another of the at least one first dielectric layer includes multiple dielectric layers adjacent one another.
In operation 116, a second dielectric layer is deposited over the at least one first dielectric layer and the at least one second semiconductor layer. In some embodiments, the second dielectric layer includes the same material as each of the at least one first dielectric layer. In some embodiments, the second dielectric layer includes a different material from at least one of the at least one the first dielectric layer. In some embodiments, the formation of the second dielectric layer is the same as that used to form the at least one first dielectric layer. In some embodiments, the formation of the second dielectric layer is different from that used to form the at least one first dielectric marital. For example, second dielectric layer uses a CVD process and the at least one first dielectric uses an ALD process. Based on the photolithographic parameters, a thickness and a refraction index of the phase shifter is determined by selecting the material and formation of the first semiconductor layer, the at least one second semiconductor layer, the at least one first dielectric layer and the second dielectric layer.
Phase shifter 220 includes a first semiconductor layer 222, a first dielectric layer 224, a second semiconductor layer 226 and a second dielectric layer 228. In some embodiments, photomask 200 includes one or more semiconductor layers or dielectric layers stacked between second semiconductor layer 226 and second dielectric layer 228 in an alternating fashion. In some embodiments, including layers 222-228, phase shifter 220 has from 2 to 12 semiconductor/dielectric pairs, collectively referred to as pairs P. If a quantity of pairs P is too small, a sidewall of a subsequently etched phase shifter 220 will have a notch or have a tapered shape, in some instances. If a quantity of pairs P is too great, a cost of manufacturing phase shifter 220 will increase without a significant increase in functionality, in some instances.
In some embodiments, first semiconductor layer 222, second semiconductor layer 226 and other semiconductor layers within phase shifter 220, collectively referred to as semiconductor layers S, independently include silicon, germanium, silicon germanium, silicon carbide or another suitable material. In some embodiments, first dielectric layer 224, second dielectric layer 228 and other dielectric layers within phase shifter 220, collectively referred to as dielectric layers D, independently include silicon dioxide, silicon nitride, silicon oxynitride or another suitable material. In some embodiments, each layer of dielectric layer D includes a single layer. In some embodiments, each layer of dielectric layers D includes multiple layers, for example, a combination of silicon dioxide and silicon nitride. The quantity of pairs P and the material selected for semiconductor layers S and for dielectric layers D are adjustable based on various parameters required in the photolithography process, such as transmittance, optical density, refractive index or critical dimension (CD) loss. In at least one embodiment where each layer of semiconductor layers S is silicon, each layer of dielectric layer D includes silicon dioxide or silicon nitride. The formation of phase shifter 220 includes a deposition process, such as ALD or CVD.
In some embodiments, a thickness of each semiconductor layer S independently ranges from about 1 nm to about 5 nm. If the thickness is too small, phase shifter 220 will suffer more damage during the subsequent clean or etch process, in some instances. If the thickness is too great, a transmittance of phase shifter 220 will decrease, in some instances. In some embodiments, each of semiconductor layer S has the same thickness. In some embodiments, at least one of semiconductor layer S has a different thickness from another semiconductor layer. In some embodiments, a thickness of each dielectric layer D independently ranges from about 10 nm to about 20 nm. If the thickness of a dielectric layer is too great, a sidewall of the subsequently etched phase shifter 220 will be irregular, in some instances. If the thickness of a dielectric layer is too small, an optical property of phase shifter 220 will be hard to control, in some instances. In some embodiments, each of dielectric layer D has the same thickness. In some embodiments, at least one of dielectric layer D has a different thickness from another dielectric layer. In some embodiments, when photomask 200 is an attenuated PSM, a total transmission rate incident light of phase shifter 220 ranges of from about 6% to 18%, in some instances. If the transmission rate is too great or too small, an intensity amplitude of phase-shifted light will be too much or insufficient, so the resolution enhancement of the image to be transferred will decrease, in some instances. Based on the inherent physical property and etching method, semiconductor layers S have a lower etch rate than dielectric layer D. For example, during a dry etch process, because silicon endures greater ion bombardments than silicon dioxide or silicon nitride, silicon has a lower etch rate than silicon dioxide or silicon nitride. Therefore, the sidewall profile is improved because of a multilayer structure with a combination of silicon and silicon dioxide/silicon nitride. In some embodiments, a ratio of etch rates between dielectric layer D and semiconductor layer S ranges from about 1.5 to about 2.5. If the ratio is too great, a loss of dielectric layer D will increase resulting in distortion of the image to be transferred, in some instances. If the ratio is too small, a manufacturing cost of photomask 200 will increase, in some instances.
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In some embodiments, under an exposure energy of around 48,000 Joules, compared to layout designed patterns, an undesired CD growth of photomask 200 is smaller than 0.1 nm and an undesired CD loss of photomask 200 is smaller than 0.1 nm. In some embodiments, under an exposure energy of around 8,000 Joules, each photomask 200 is able to produce at least 25,000 wafers.
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One of ordinary skill in the art would understand that photomasks 200-400 will undergo further processing to complete fabrication. For example, in at least one embodiment, a third mask layer is formed over the photomask to define a third pattern. As another example, a passivation layer is optionally deposited over photomasks 200-400 after operation 130 or 140 or (depending on various designs of photomasks) to repair defects generated during the manufacturing process.
The insertion of semiconductor layers with a relatively lower etch rate than dielectric layers helps keep a sidewall profile of phase shifter, resulting in an improved CD pattern during the photolithography process. In addition, a transmittance of the phase shifter is adjustable by various combinations of the semiconductor layer and dielectric layer. Further, comparing to molybdenum silicide-based material, the semiconductor layer, such as silicon, and the dielectric layer, such as silicon dioxide, help reduce CD increase caused by oxidation and reduce a risk of haze caused during clean process. Moreover, an un-etched protrusion of the bottom semiconductor layer enhances a damage resistance caused by a wet clean process, resulting in a reduced manufacturing cost and production yield.
One aspect of this description relates to a method of fabricating a photomask. The method includes depositing a phase shifter over a light transmitting substrate, depositing a shading layer over the light transmitting substrate, and removing a portion of the shading layer and a portion of the phase shifter to expose a portion of the light transmitting substrate. The phase shifter having at least two semiconductor layers and at least two dielectric layers.
Another aspect of this description relates to a method of fabricating a reticle. The method includes depositing a bottom silicon layer over a transparent substrate, depositing at least one silicon/dielectric pair over the bottom silicon layer, depositing a top dielectric layer over the at least one silicon/dielectric pair, depositing an opaque layer over the top dielectric layer, and removing a portion of the opaque layer, a portion of the top dielectric layer, a portion of the at least one silicon/dielectric pair and the bottom silicon layer to expose a portion of the transparent substrate.
Still another aspect of this description relates to a PSM. The PSM includes a light transmitting substrate, and a phase shifter over the light transmitting substrate. The phase shifter has from 2 to 12 pairs of semiconductor layers and dielectric layers stacked in an alternating fashion.
The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.
Number | Name | Date | Kind |
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20080020299 | Lee | Jan 2008 | A1 |
Number | Date | Country | |
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20180149960 A1 | May 2018 | US |
Number | Date | Country | |
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62427643 | Nov 2016 | US |