Patent Application
20240186136
Integrated circuit devices continue to shrink in size, and with this shrinkage, manufacturing processes for these devices implement surfaces with relatively high aspect ratios (i.e., a ratio of the height to width of a surface, such as a trench). These high aspect ratio surfaces present challenges for conformal deposition of materials, such as adhesion promotion materials.
Integrated circuit devices continue to shrink in size, and with this shrinkage, manufacturing processes for these devices implement surfaces with relatively high aspect ratios (i.e., a ratio of the height to width of a surface, such as a trench). These high aspect ratio surfaces present challenges for conformal deposition of materials, such as adhesion promotion materials. Current techniques may implement surface roughening or deposition of relatively thick adhesive layers on the surfaces to promote adhesion (e.g., of a metal to the surface). However, thick adhesive layers create thermal resistance, intensifying heat accumulation issues within the device. Furthermore, surface roughening reduces the efficiency of the devices for high-speed input/output (HSIO) applications.
Embodiments of the present disclosure address these or other issues by providing methods and materials for improving adhesion of smooth (or rough) surfaces, which may be helpful for high aspect ratio surfaces in integrated circuit devices. For example, certain embodiments may implement a vacuum-based vapor deposition technique (e.g., initiated chemical vapor deposition (iCVD)) of polymers onto a smooth organic, inorganic, metal, or glass surfaces, to go between the surface and a dielectric material. The polymers may function as an adhesive/adhesion promotion layer between the surface and the dielectric material. When used as an adhesion layer, the polymer materials may provide very strong covalent bonding at the interface between two materials, such as a metal and dielectric, leading to little or no delamination of the metal. In addition, the polymer can act as stress buffer layer, due to the relatively high elongation and mechanical properties of polymers. Furthermore, by using a thin film polymer, there may be no added heat transfer resistance due to sub-20 nm thickness feasibility with the polymer. The polymer materials may also have a high chemical stability, as well as high thermal/mechanical stability, which makes them good candidates for use in integrated circuit manufacturing. In certain instances, no additional curing step may be needed, as the curing/crosslinking of the polymer may occur at the same time as a dielectric material (e.g., ABF) is being conditioned.
In addition, vacuum-based vapor deposition methods such as iCVD provide several advantages. For example, iCVD is the only known method for controlled thin-film (e.g., from sub-10 nm to micron) deposition of polymeric materials at low temperatures. Moreover, the iCVD deposition rate is significantly faster compared to other conformal deposition techniques, such as ALD and PVD techniques. In addition, iCVD reactants, including the monomer and initiator, are made of abundant and cost-effective elements. Further, since reaction in iCVD may begin on a substrate surface (e.g., glass, metal etc.), creating a chemical bonding to the surface is feasible. Hence, iCVD or similar techniques may enable very strong adhesion between the deposited polymer and the underlying surface that is independent of surface roughness. Additionally, vacuum-based deposition techniques, often used at working pressure between 50-500 m Torr, may rely on continuous delivery of the reactants, which enables conformal and controlled deposition of material in tortuous and patterned substrates. Thus, iCVD of polymers may enable a uniform conformal deposition of high aspect ratio and three-dimensional (3D) features, e.g., in integrated circuit devices with such features.
Embodiments herein may be detected in devices using one or more of FTIR, Raman spectroscopy, AFM, AFM-IR, TEM, and XPS. Moreover, depending on the film thickness, in addition to the mentioned techniques, X-SEM and X-EDS can be used to detect the material/films. Specifically, films deposited through iCVD may be uniquely detectable by measuring their initiator content by XPS or FTIR. During thin film deposition through iCVD, polymer chains are terminated/capped by initiator radicals; hence, depending on the monomer/initiator ratio, there may be some initiator content remaining in the final deposited film, allowing detection through their bonding states (e.g., XPS or FTIR).
As previously described, embodiments herein may implement a conformal deposition of polymeric thin films on either smooth or rough metal (e.g., copper), glass, or inorganic (e.g., SiNx) surfaces, e.g., to function as an adhesion promotion layer and/or as stress buffer layer or low-loss dielectric. The polymer materials may be deposited using a vacuum-based vapor deposition technique such as iCVD, which may enable a thin conformal deposition of the polymers, with a thickness ranging from sub-10 nm to 5 um, on both planar and high aspect ratio surfaces, e.g., the trenches 104 as shown in
The polymeric layer 202 may be formed using a vacuum-based vapor deposition technique, such as initiated chemical vapor deposition (iCVD). In an iCVD process, a monomer and an initiator are flowed into a vacuum chamber (e.g., simultaneously) where they contact resistively heated filaments. The initiator breaks down into radicals, beginning a free-radical polymerization of the monomer at the substrate surface. During this process, the free radicals and activated monomers can crate chemical bonding to active sites on the substrate (e.g., 100). This provides an opportunity for grafting the polymer to the substrate 100. Also, due to the nature of free radical polymerization occurring during the iCVD process, dangling bonds may be left on the top surface of deposited thin film 202, providing grafting sites for the next layer (e.g., a metal layer deposited next). Example initiators may include chemicals like tert-butyl peroxide (TBPO) for PGMA or Perfluoro butane sulfonyl fluoride (PBSF) for PTFE, and example monomers that may be used may be typically are made of carbon, nitrogen, oxygen, hydrogen, and other abundant elements, which make them relatively inexpensive.
The example process 300 begins with forming metal pillars and/or traces 304 on a substrate 302. The substrate 302 may be made of an organic material or a glass material (e.g., silica or SOG) in certain embodiments. Thereafter, a layer 306 of polymer material (e.g., PGMA in the example shown) is deposited on the surface of the metal 304. The polymer material layer 306 may be deposited using a vacuum-based vapor deposition technique such as iCVD, which can enable grafting of the deposited polymer to the underlying metal, and to a material later deposited on top. Such a deposition technique may allow for a conformal deposition of the polymer on the surface of the metal pillars/traces. An iCVD process may be performed, for example, by depositing a monomer on a surface of the metal pillars/traces and then flowing an initiator material that, e.g., based on thermal activation, causes polymerization of the monomer on the surface of the metal pillars/traces.
After the polymeric layer 306 is deposited, a dielectric material 308 is then deposited on the polymeric layer 306. The resulting material stack 310 is then heated, which functions to cure the dielectric build-up material 308 and also crosslink the polymer material in the layer 306, e.g., as shown in
The example process 400 begins with the formation of holes 403 within a substrate 402. The substrate 402 may one made of an organic, inorganic, or glass material (including silica or SOG). The holes 403 may form the basis for metal vias (e.g., 408) in the substrate. In some embodiments, the substrate 402 may be plasma treated, which can aid in the adhesion of the polymeric layer 404, which is thereafter deposited on the substrate 402 as shown. The polymeric layer may be deposited using a using a vacuum-based vapor deposition technique such as iCVD, as described above, and may include any suitable polymer material, such as those described above. The layer 404 may act as a buffer layer for stress (e.g., due to CTE mismatches) between the substrate 402 and metal (e.g., 406, 407, 408) or between the substrate 402 and a dielectric (e.g., 411, 412) deposited thereafter, and/or as an adhesion promotion layer for aiding adhesion between the metal (e.g., 406, 407, 408) or dielectric (e.g., 411, 412) deposited thereafter. After the metal 406, 407, 408 has been deposited, additional polymeric layers 409, 410 are deposited on the metal, e.g., to act as an adhesion promotion layer between the metal and the dielectrics 411, 412 deposited thereafter (as shown).
The build-up layers 506 are formed on the top and bottom sides of the core 502, with build-up layers 506A on the top side of the glass core 502 and the build-up layers 506B on bottom side of the core 502. The layers 506 may be made from a traditional dielectric material in certain embodiments. The layers 506 include metal pillars, vias, and/or traces as shown to electrically couple the solder bumps 508 at the top of the package substrate 500 with the pads 510 at the bottom of the substrate. In certain instances, for example, an integrated circuit die may be coupled to a top side of the package substrate 500 and connect to the solder bumps 508, and the package substrate 500 may be coupled to a circuit board (e.g., a motherboard, main board, etc.) via the pads 510 at the bottom of the package substrate 500. For instance, the package substrate 500 may be incorporated into the system 700 of
In addition, there is a bridge component 614 located in the build-up layers 606A that electrically couples the first IC die 612A with the second IC die 612B. The bridge component 614 may include passive and/or active components to interconnect the IC dies 612. The bridge component 614 may be an Intel® embedded multi-die interconnect bridge (EMIB) in certain embodiments. In certain instances, the multi-die package 600 may be coupled to a circuit board (e.g., a motherboard, main board, etc.) via the pads 610 at the bottom of the package 600. For instance, the package 600 may be incorporated into the system 710 of
Similar to the system 700, the system 710 also includes a circuit board 712, which may be implemented as a motherboard or main board of a computer system in some embodiments. The system 710 also includes a multi-die package 714, which includes multiple integrated circuits/dies (e.g., 706), and interconnections between the dies in one or more metallization layers. The multi-die package 714 may include, for example, one or more silicon interposers, one or more silicon bridges embedded in the package substrate (e.g., an Intel® embedded multi-die interconnect bridge (EMIB)), or combinations thereof.
The main circuit boards 710, 712 may provide electrical connections to other components of a computer system, e.g., memory, storage, network interfaces, peripheral devices, power supplies, etc. The main circuit board may include one or more traces and circuit components to provide interconnects between such computer system components.
The integrated circuit device 900 may include one or more device layers 904 disposed on the die substrate 902. The device layer 904 may include features of one or more transistors 940 (e.g., metal oxide semiconductor field-effect transistors (MOSFETs)) formed on the die substrate 902. The transistors 940 may include, for example, one or more source and/or drain (S/D) regions 920, a gate 922 to control current flow between the S/D regions 920, and one or more S/D contacts 924 to route electrical signals to/from the S/D regions 920. The transistors 940 may include additional features not depicted for the sake of clarity, such as device isolation regions, gate contacts, and the like. The transistors 940 are not limited to the type and configuration depicted in
Returning to
The high-k dielectric material may include elements such as hafnium, silicon, oxygen, titanium, tantalum, lanthanum, aluminum, zirconium, barium, strontium, yttrium, lead, scandium, niobium, and zinc. Examples of high-k materials that may be used in the gate dielectric include, but are not limited to, hafnium oxide, hafnium silicon oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate. In some embodiments, an annealing process may be carried out on the gate dielectric to improve its quality when a high-k material is used.
The gate electrode may be formed on the gate dielectric and may include at least one p-type work function metal or n-type work function metal, depending on whether the transistor 940 is to be a p-type metal oxide semiconductor (PMOS) or an n-type metal oxide semiconductor (NMOS) transistor. In some implementations, the gate electrode may consist of a stack of two or more metal layers, where one or more metal layers are work function metal layers and at least one metal layer is a fill metal layer. Further metal layers may be included for other purposes, such as a barrier layer.
For a PMOS transistor, metals that may be used for the gate electrode include, but are not limited to, ruthenium, palladium, platinum, cobalt, nickel, conductive metal oxides (e.g., ruthenium oxide), and any of the metals discussed below with reference to an NMOS transistor (e.g., for work function tuning). For an NMOS transistor, metals that may be used for the gate electrode include, but are not limited to, hafnium, zirconium, titanium, tantalum, aluminum, alloys of these metals, carbides of these metals (e.g., hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide, and aluminum carbide), and any of the metals discussed above with reference to a PMOS transistor (e.g., for work function tuning).
In some embodiments, when viewed as a cross-section of the transistor 940 along the source-channel-drain direction, the gate electrode may consist of a U-shaped structure that includes a bottom portion substantially parallel to the surface of the die substrate 902 and two sidewall portions that are substantially perpendicular to the top surface of the die substrate 902. In other embodiments, at least one of the metal layers that form the gate electrode may simply be a planar layer that is substantially parallel to the top surface of the die substrate 902 and does not include sidewall portions substantially perpendicular to the top surface of the die substrate 902. In other embodiments, the gate electrode may consist of a combination of U-shaped structures and planar, non-U-shaped structures. For example, the gate electrode may consist of one or more U-shaped metal layers formed atop one or more planar, non-U-shaped layers.
In some embodiments, a pair of sidewall spacers may be formed on opposing sides of the gate stack to bracket the gate stack. The sidewall spacers may be formed from materials such as silicon nitride, silicon oxide, silicon carbide, silicon nitride doped with carbon, and silicon oxynitride. Processes for forming sidewall spacers are well known in the art and generally include deposition and etching process steps. In some embodiments, a plurality of spacer pairs may be used; for instance, two pairs, three pairs, or four pairs of sidewall spacers may be formed on opposing sides of the gate stack.
The S/D regions 920 may be formed within the die substrate 902 adjacent to the gate 922 of individual transistors 940. The S/D regions 920 may be formed using an implantation/diffusion process or an etching/deposition process, for example. In the former process, dopants such as boron, aluminum, antimony, phosphorous, or arsenic may be ion-implanted into the die substrate 902 to form the S/D regions 920. An annealing process that activates the dopants and causes them to diffuse farther into the die substrate 902 may follow the ion-implantation process. In the latter process, the die substrate 902 may first be etched to form recesses at the locations of the S/D regions 920. An epitaxial deposition process may then be carried out to fill the recesses with material that is used to fabricate the S/D regions 920. In some implementations, the S/D regions 920 may be fabricated using a silicon alloy such as silicon germanium or silicon carbide. In some embodiments, the epitaxially deposited silicon alloy may be doped in situ with dopants such as boron, arsenic, or phosphorous. In some embodiments, the S/D regions 920 may be formed using one or more alternate semiconductor materials such as germanium or a group III-V material or alloy. In further embodiments, one or more layers of metal and/or metal alloys may be used to form the S/D regions 920.
Electrical signals, such as power and/or input/output (I/O) signals, may be routed to and/or from the devices (e.g., transistors 940) of the device layer 904 through one or more interconnect layers disposed on the device layer 904 (illustrated in
The interconnect structures 928 may be arranged within the interconnect layers 906-910 to route electrical signals according to a wide variety of designs; in particular, the arrangement is not limited to the particular configuration of interconnect structures 928 depicted in
In some embodiments, the interconnect structures 928 may include lines 928a and/or vias 928b filled with an electrically conductive material such as a metal. The lines 928a may be arranged to route electrical signals in a direction of a plane that is substantially parallel with a surface of the die substrate 902 upon which the device layer 904 is formed. For example, the lines 928a may route electrical signals in a direction in and out of the page and/or in a direction across the page from the perspective of
The interconnect layers 906-910 may include a dielectric material 926 disposed between the interconnect structures 928, as shown in
A first interconnect layer 906 (referred to as Metal 1 or “M1”) may be formed directly on the device layer 904. In some embodiments, the first interconnect layer 906 may include lines 928a and/or vias 928b, as shown. The lines 928a of the first interconnect layer 906 may be coupled with contacts (e.g., the S/D contacts 924) of the device layer 904. The vias 928b of the first interconnect layer 906 may be coupled with the lines 928a of a second interconnect layer 908.
The second interconnect layer 908 (referred to as Metal 2 or “M2”) may be formed directly on the first interconnect layer 906. In some embodiments, the second interconnect layer 908 may include via 928b to couple the lines 928 of the second interconnect layer 908 with the lines 928a of a third interconnect layer 910. Although the lines 928a and the vias 928b are structurally delineated with a line within individual interconnect layers for the sake of clarity, the lines 928a and the vias 928b may be structurally and/or materially contiguous (e.g., simultaneously filled during a dual-damascene process) in some embodiments.
The third interconnect layer 910 (referred to as Metal 3 or “M3”) (and additional interconnect layers, as desired) may be formed in succession on the second interconnect layer 908 according to similar techniques and configurations described in connection with the second interconnect layer 908 or the first interconnect layer 906. In some embodiments, the interconnect layers that are “higher up” in the metallization stack 919 in the integrated circuit device 900 (i.e., farther away from the device layer 904) may be thicker that the interconnect layers that are lower in the metallization stack 919, with lines 928a and vias 928b in the higher interconnect layers being thicker than those in the lower interconnect layers.
The integrated circuit device 900 may include a solder resist material 934 (e.g., polyimide or similar material) and one or more conductive contacts 936 formed on the interconnect layers 906-910. In
In some embodiments in which the integrated circuit device 900 is a double-sided die, the integrated circuit device 900 may include another metallization stack (not shown) on the opposite side of the device layer(s) 904. This metallization stack may include multiple interconnect layers as discussed above with reference to the interconnect layers 906-910, to provide conductive pathways (e.g., including conductive lines and vias) between the device layer(s) 904 and additional conductive contacts (not shown) on the opposite side of the integrated circuit device 900 from the conductive contacts 936.
In other embodiments in which the integrated circuit device 900 is a double-sided die, the integrated circuit device 900 may include one or more through silicon vias (TSVs) through the die substrate 902; these TSVs may make contact with the device layer(s) 904, and may provide conductive pathways between the device layer(s) 904 and additional conductive contacts (not shown) on the opposite side of the integrated circuit device 900 from the conductive contacts 936. In some embodiments, TSVs extending through the substrate can be used for routing power and ground signals from conductive contacts on the opposite side of the integrated circuit device 900 from the conductive contacts 936 to the transistors 940 and any other components integrated into the die 900, and the metallization stack 919 can be used to route I/O signals from the conductive contacts 936 to transistors 940 and any other components integrated into the die 900.
Multiple integrated circuit devices 900 may be stacked with one or more TSVs in the individual stacked devices providing connection between one of the devices to any of the other devices in the stack. For example, one or more high-bandwidth memory (HBM) integrated circuit dies can be stacked on top of a base integrated circuit die and TSVs in the HBM dies can provide connection between the individual HBM and the base integrated circuit die. Conductive contacts can provide additional connections between adjacent integrated circuit dies in the stack. In some embodiments, the conductive contacts can be fine-pitch solder bumps (microbumps).
Additionally, in various embodiments, the electrical device 1000 may not include one or more of the components illustrated in
The electrical device 1000 may include one or more processor units 1002 (e.g., one or more processor units). As used herein, the terms “processor unit”, “processing unit” or “processor” may refer to any device or portion of a device that processes electronic data from registers and/or memory to transform that electronic data into other electronic data that may be stored in registers and/or memory. The processor unit 1002 may include one or more digital signal processors (DSPs), application-specific integrated circuits (ASICs), central processing units (CPUs), graphics processing units (GPUs), general-purpose GPUs (GPGPUs), accelerated processing units (APUs), field-programmable gate arrays (FPGAs), neural network processing units (NPUs), data processor units (DPUs), accelerators (e.g., graphics accelerator, compression accelerator, artificial intelligence accelerator), controller cryptoprocessors (specialized processors that execute cryptographic algorithms within hardware), server processors, controllers, or any other suitable type of processor units. As such, the processor unit can be referred to as an XPU (or xPU).
The electrical device 1000 may include a memory 1004, which may itself include one or more memory devices such as volatile memory (e.g., dynamic random access memory (DRAM), static random-access memory (SRAM)), non-volatile memory (e.g., read-only memory (ROM), flash memory, chalcogenide-based phase-change non-voltage memories), solid state memory, and/or a hard drive. In some embodiments, the memory 1004 may include memory that is located on the same integrated circuit die as the processor unit 1002. This memory may be used as cache memory (e.g., Level 1 (L1), Level 2 (L2), Level 3 (L3), Level 4 (L4), Last Level Cache (LLC)) and may include embedded dynamic random access memory (eDRAM) or spin transfer torque magnetic random access memory (STT-MRAM).
In some embodiments, the electrical device 1000 can comprise one or more processor units 1002 that are heterogeneous or asymmetric to another processor unit 1002 in the electrical device 1000. There can be a variety of differences between the processing units 1002 in a system in terms of a spectrum of metrics of merit including architectural, microarchitectural, thermal, power consumption characteristics, and the like. These differences can effectively manifest themselves as asymmetry and heterogeneity among the processor units 1002 in the electrical device 1000.
In some embodiments, the electrical device 1000 may include a communication component 1012 (e.g., one or more communication components). For example, the communication component 1012 can manage wireless communications for the transfer of data to and from the electrical device 1000. The term “wireless” and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communications channels, etc., that may communicate data through the use of modulated electromagnetic radiation through a nonsolid medium. The term “wireless” does not imply that the associated devices do not contain any wires, although in some embodiments they might not.
The communication component 1012 may implement any of a number of wireless standards or protocols, including but not limited to Institute for Electrical and Electronic Engineers (IEEE) standards including Wi-Fi (IEEE 802.11 family), IEEE 802.16 standards (e.g., IEEE 802.16-2005 Amendment), Long-Term Evolution (LTE) project along with any amendments, updates, and/or revisions (e.g., advanced LTE project, ultra mobile broadband (UMB) project (also referred to as “3GPP2”), etc.). IEEE 802.16 compatible Broadband Wireless Access (BWA) networks are generally referred to as WiMAX networks, an acronym that stands for Worldwide Interoperability for Microwave Access, which is a certification mark for products that pass conformity and interoperability tests for the IEEE 802.16 standards. The communication component 1012 may operate in accordance with a Global System for Mobile Communication (GSM), General Packet Radio Service (GPRS), Universal Mobile Telecommunications System (UMTS), High Speed Packet Access (HSPA), Evolved HSPA (E-HSPA), or LTE network. The communication component 1012 may operate in accordance with Enhanced Data for GSM Evolution (EDGE), GSM EDGE Radio Access Network (GERAN), Universal Terrestrial Radio Access Network (UTRAN), or Evolved UTRAN (E-UTRAN). The communication component 1012 may operate in accordance with Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Digital Enhanced Cordless Telecommunications (DECT), Evolution-Data Optimized (EV-DO), and derivatives thereof, as well as any other wireless protocols that are designated as 3G, 4G, 5G, and beyond. The communication component 1012 may operate in accordance with other wireless protocols in other embodiments. The electrical device 1000 may include an antenna 1022 to facilitate wireless communications and/or to receive other wireless communications (such as AM or FM radio transmissions).
In some embodiments, the communication component 1012 may manage wired communications, such as electrical, optical, or any other suitable communication protocols (e.g., IEEE 802.3 Ethernet standards). As noted above, the communication component 1012 may include multiple communication components. For instance, a first communication component 1012 may be dedicated to shorter-range wireless communications such as Wi-Fi or Bluetooth, and a second communication component 1012 may be dedicated to longer-range wireless communications such as global positioning system (GPS), EDGE, GPRS, CDMA, WiMAX, LTE, EV-DO, or others. In some embodiments, a first communication component 1012 may be dedicated to wireless communications, and a second communication component 1012 may be dedicated to wired communications.
The electrical device 1000 may include battery/power circuitry 1014. The battery/power circuitry 1014 may include one or more energy storage devices (e.g., batteries or capacitors) and/or circuitry for coupling components of the electrical device 1000 to an energy source separate from the electrical device 1000 (e.g., AC line power).
The electrical device 1000 may include a display device 1006 (or corresponding interface circuitry, as discussed above). The display device 1006 may include one or more embedded or wired or wirelessly connected external visual indicators, such as a heads-up display, a computer monitor, a projector, a touchscreen display, a liquid crystal display (LCD), a light-emitting diode display, or a flat panel display.
The electrical device 1000 may include an audio output device 1008 (or corresponding interface circuitry, as discussed above). The audio output device 1008 may include any embedded or wired or wirelessly connected external device that generates an audible indicator, such speakers, headsets, or earbuds.
The electrical device 1000 may include an audio input device 1024 (or corresponding interface circuitry, as discussed above). The audio input device 1024 may include any embedded or wired or wirelessly connected device that generates a signal representative of a sound, such as microphones, microphone arrays, or digital instruments (e.g., instruments having a musical instrument digital interface (MIDI) output). The electrical device 1000 may include a Global Navigation Satellite System (GNSS) device 1018 (or corresponding interface circuitry, as discussed above), such as a Global Positioning System (GPS) device. The GNSS device 1018 may be in communication with a satellite-based system and may determine a geolocation of the electrical device 1000 based on information received from one or more GNSS satellites, as known in the art.
The electrical device 1000 may include another output device 1010 (or corresponding interface circuitry, as discussed above). Examples of the other output device 1010 may include an audio codec, a video codec, a printer, a wired or wireless transmitter for providing information to other devices, or an additional storage device.
The electrical device 1000 may include another input device 1020 (or corresponding interface circuitry, as discussed above). Examples of the other input device 1020 may include an accelerometer, a gyroscope, a compass, an image capture device (e.g., monoscopic or stereoscopic camera), a trackball, a trackpad, a touchpad, a keyboard, a cursor control device such as a mouse, a stylus, a touchscreen, proximity sensor, microphone, a bar code reader, a Quick Response (QR) code reader, electrocardiogram (ECG) sensor, PPG (photoplethysmogram) sensor, galvanic skin response sensor, any other sensor, or a radio frequency identification (RFID) reader.
The electrical device 1000 may have any desired form factor, such as a hand-held or mobile electrical device (e.g., a cell phone, a smart phone, a mobile internet device, a music player, a tablet computer, a laptop computer, a 2-in-1 convertible computer, a portable all-in-one computer, a netbook computer, an ultrabook computer, a personal digital assistant (PDA), an ultra mobile personal computer, a portable gaming console, etc.), a desktop electrical device, a server, a rack-level computing solution (e.g., blade, tray or sled computing systems), a workstation or other networked computing component, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a stationary gaming console, smart television, a vehicle control unit, a digital camera, a digital video recorder, a wearable electrical device or an embedded computing system (e.g., computing systems that are part of a vehicle, smart home appliance, consumer electronics product or equipment, manufacturing equipment). In some embodiments, the electrical device 1000 may be any other electronic device that processes data. In some embodiments, the electrical device 1000 may comprise multiple discrete physical components. Given the range of devices that the electrical device 1000 can be manifested as in various embodiments, in some embodiments, the electrical device 1000 can be referred to as a computing device or a computing system.
Illustrative examples of the technologies described throughout this disclosure are provided below. Embodiments of these technologies may include any one or more, and any combination of, the examples described below. In some embodiments, at least one of the systems or components set forth in one or more of the preceding figures may be configured to perform one or more operations, techniques, processes, and/or methods as set forth in the following examples.
Example 1 is an apparatus comprising: a substrate; metal pillars on a first side of the substrate; a polymeric layer conformally on the metal; and a dielectric layer on the polymeric layer.
Example 2 includes the subject matter of Example 1, wherein the polymeric layer comprises one or more of Polytetrafluoroethylene (PTFE), Poly(Glycidyl Methacrylate) (PGMA), poly (1,3,5-trimethyl-1,3,5-trivinyl cyclotrisiloxane) (pV3D3), poly(1,3,5,7-tetravinyl-1,3,5, 7-tetramethylcyclotetrasiloxane) (pV4D4), and poly(1H, 1H,2H,2H-perfluorodecyl acrylate (pPFDA).
Example 3 includes the subject matter of Example 1 or 2, wherein the substrate is a glass substrate that comprises Silicon and Oxygen.
Example 4 includes the subject matter of any one of Examples 1-3, wherein the polymeric layer is a first polymeric layer, and the apparatus further comprises a second polymeric layer between the substrate and the metal pillars.
Example 5 includes the subject matter of Example 4, wherein the second polymeric layer comprises one or more of Polytetrafluoroethylene (PTFE), Poly(Glycidyl Methacrylate) (PGMA), poly (1,3,5-trimethyl-1,3,5-trivinyl cyclotrisiloxane) (pV3D3), poly(1,3,5,7-tetravinyl-1,3,5, 7-tetramethylcyclotetrasiloxane) (pV4D4), and poly(1H, 1H,2H,2H-perfluorodecyl acrylate (pPFDA).
Example 6 is an integrated circuit package substrate comprising: a core layer; metal vias electrically coupling a first side of the core layer and a second side of the core layer; and a polymeric layer between the metal vias and the core layer.
Example 7 includes the subject matter of Example 6, wherein the polymeric layer comprises one or more of Polytetrafluoroethylene (PTFE), Poly(Glycidyl Methacrylate) (PGMA), poly (1,3,5-trimethyl-1,3,5-trivinyl cyclotrisiloxane) (pV3D3), poly(1,3,5,7-tetravinyl-1,3,5, 7-tetramethylcyclotetrasiloxane) (pV4D4), and poly(1H, 1H,2H,2H-perfluorodecyl acrylate (pPFDA).
Example 8 includes the subject matter of Example 6 or 7, wherein the polymeric layer is a first polymeric layer, and the integrated circuit package substrate further comprises: a build-up layer on the core layer comprising a dielectric material in contact with one or more of the metal vias in the core layer; and a second polymeric layer between the dielectric material and one or more of the metal via in the core layer.
Example 9 includes the subject matter of Example 8, wherein the second polymeric layer comprises one or more of Polytetrafluoroethylene (PTFE), Poly(Glycidyl Methacrylate) (PGMA), poly (1,3,5-trimethyl-1,3,5-trivinyl cyclotrisiloxane) (pV3D3), poly(1,3,5,7-tetravinyl-1,3,5, 7-tetramethylcyclotetrasiloxane) (pV4D4), and poly(1H,1H,2H,2H-perfluorodecyl acrylate (pPFDA).
Example 10 is an integrated circuit device comprising the integrated circuit package substrate of any one of Examples 6-9 and an integrated circuit die coupled to the package substrate.
Example 11 is a computing system comprising a main circuit board and the integrated circuit device of Example 10.
Example 12 is a method comprising: forming a plurality of holes in a substrate (e.g., a glass substrate or a substrate and comprises Silicon and Oxygen); depositing a polymer material on the sidewalls of the holes (e.g., using a vacuum-based vapor deposition process); and depositing a metal in the holes.
Example 13 includes the subject matter of Example 12, wherein the polymer material comprises one or more of Polytetrafluoroethylene (PTFE), Poly(Glycidyl Methacrylate) (PGMA), poly (1,3,5-trimethyl-1,3,5-trivinyl cyclotrisiloxane) (pV3D3), poly(1,3,5,7-tetravinyl-1,3,5, 7-tetramethylcyclotetrasiloxane) (pV4D4), and poly(1H, 1H,2H,2H-perfluorodecyl acrylate (pPFDA).
Example 14 includes the subject matter of Example 12 or 13, wherein the vacuum-based vapor deposition process is an initiated chemical vapor deposition process.
Example 15 includes the subject matter of any one of Examples 12-14, further comprising curing the polymer material.
Example 16 includes the subject matter of Example 15, wherein curing the polymer material comprising heating the polymer material between 100-200° C.
Example 17 includes the subject matter of any one of Examples 12-16, further comprising: depositing a polymer material on a surface of the substrate; and depositing a metal on the polymer layer on the surface of the substrate.
Example 18 includes the subject matter of Example 17, wherein the polymer material on the surface of the substrate comprises one or more of Polytetrafluoroethylene (PTFE), Poly(Glycidyl Methacrylate) (PGMA), poly (1,3,5-trimethyl-1,3,5-trivinyl cyclotrisiloxane) (pV3D3), poly(1,3,5,7-tetravinyl-1,3,5,7-tetramethylcyclotetrasiloxane) (pV4D4), and poly(1H, 1H,2H,2H-perfluorodecyl acrylate (pPFDA).
Example 19 includes the subject matter of Example 17 or 18, wherein the polymer material on the surface of the substrate is deposited using an initiated chemical vapor deposition process.
Example 20 includes the subject matter of any one of Examples 12-19, further comprising: depositing a polymer material on the metal; and depositing a dielectric on the polymer layer on the metal.
Example 21 is a product made from the method of any one of Examples 12-20.
In the above description, various aspects of the illustrative implementations have been described using terms commonly employed by those skilled in the art to convey the substance of their work to others skilled in the art. However, it will be apparent to those skilled in the art that the present disclosure may be practiced with only some of the described aspects. For purposes of explanation, specific numbers, materials, and configurations have been set forth to provide a thorough understanding of the illustrative implementations. However, it will be apparent to one skilled in the art that the present disclosure may be practiced without all of the specific details. In other instances, well-known features have been omitted or simplified in order not to obscure the illustrative implementations.
For the purposes of the present disclosure, the phrase “A and/or B” means (A), (B), or (A and B). For the purposes of the present disclosure, the phrase “A, B, and/or C” means (A), (B), (C), (A and B), (A and C), (B and C), or (A, B and C).
The terms “over,” “under,” “between,” “above,” and “on” as used herein may refer to a relative position of one material layer or component with respect to other layers or components. For example, one layer disposed over or under another layer may be directly in contact with the other layer or may have one or more intervening layers. Moreover, one layer disposed between two layers may be directly in contact with the two layers or may have one or more intervening layers. In contrast, a first layer “on” a second layer is in direct contact with that second layer. Similarly, unless explicitly stated otherwise, one feature disposed between two features may be in direct contact with the adjacent features or may have one or more intervening features.
The above description may use the phrases “in an embodiment,” or “in embodiments,” which may each refer to one or more of the same or different embodiments. Furthermore, the terms “comprising,” “including,” “having,” and the like, as used with respect to embodiments of the present disclosure, are synonymous.
The term “coupled with,” along with its derivatives, may be used herein. “Coupled” may mean one or more of the following. “Coupled” may mean that two or more elements are in direct physical or electrical contact. However, “coupled” may also mean that two or more elements indirectly contact each other, but yet still cooperate or interact with each other, and may mean that one or more other elements are coupled or connected between the elements that are said to be coupled with each other. The term “directly coupled” may mean that two or more elements are in direct contact.
In various embodiments, the phrase “a first feature formed, deposited, or otherwise disposed on a second feature” may mean that the first feature is formed, deposited, or disposed over the second feature, and at least a part of the first feature may be in direct contact (e.g., direct physical and/or electrical contact) or indirect contact (e.g., having one or more other features between the first feature and the second feature) with at least a part of the second feature. Further, as used herein, the phrase “located on” in the context of a first layer or component located on a second layer or component may refer to the first layer or component being directly physically attached to the second part or component (no layers or components between the first and second layers or components) or physically attached to the second layer or component with one or more intervening layers or components. Additionally, as used herein, the term “adjacent” may refer to layers or components that are in physical contact with each other. That is, there is no layer or component between the stated adjacent layers or components. For example, a layer X that is adjacent to a layer Y refers to a layer that is in physical contact with layer Y.
Where the disclosure recites “a” or “a first” element or the equivalent thereof, such disclosure includes one or more such elements, neither requiring nor excluding two or more such elements. Further, ordinal indicators (e.g., first, second, or third) for identified elements are used to distinguish between the elements, and do not indicate or imply a required or limited number of such elements, nor do they indicate a particular position or order of such elements unless otherwise specifically stated.
