Patent Application
20200090736
A variety of techniques have been developed to increase the overall processing speed of computer systems. Vast improvements in integrated circuit processing technologies have contributed to the ability to increase computer processing speeds and memory capacity, thereby contributing to the overall improved performance of computer systems. The ability to produce integrated circuits with deep sub-micron features enables the density of electrical components, such as transistors to also increase.
Static random-access memory (SRAM) is a type of semiconductor memory that uses bi-stable latching circuitry to store binary bits of data. SRAM cells have the advantage of holding data without requiring a refresh. SRAM is still volatile in the sense that data is eventually lost when the memory is not powered. The smallest memory-array unit of a SRAM chip is the subarray, consisting of rows and columns. An addressed cell is at the intersection of a specified row and column address. In SRAM terminology the rows are named word lines and the columns are named bit lines. Bit lines are typically “metallic” conductors perpendicular to the word lines and are physically connected to the source/drains of the cell-transistors. In other words, the bit lines are the lines through which information is written/read to/from the memory cells.
Modern processors operate at relatively low voltages for some workloads to save power. Additionally, modern processors operate at higher voltages to support higher clock speeds for other workloads. To operate embedded memory arrays at low voltages, modern processors often implement a write assist technique using a common method that preserves cell stability called negative bit line boost. However, if the SRAM array operates at too high of a voltage, the voltage across transistors in the bit cells connected to each column multiplexed bit line pair may cause reliability issues such as time-dependent dielectric breakdown, hot carrier injection negative bias temperature instability, positive bias temperature instability, etc.
In the following description, the use of the same reference numerals in different drawings indicates similar or identical items. Unless otherwise noted, the word “coupled” and its associated verb forms include both direct connection and indirect electrical connection by means known in the art, and unless otherwise noted any description of direct connection implies alternate embodiments using suitable forms of indirect electrical connection as well.
As will be described below in one form, a write driver includes a first and a second write driver and a control circuit. When a true data signal is in a first logic state, the first write driver provides a true write data signal to an output at a high voltage. The first write driver provides the true write data signal at a ground voltage when the true data signal is in a second logic state and a negative bit line enable signal is inactive. When the true data signal is in the second logic state and the negative bit line enable signal is active the first write driver provides a voltage below the ground voltage. The second write driver provides a complement write data signal to an output at the high voltage when a complement data signal is in the first logic state. When the complement data signal is in the second logic state and the negative bit line enable signal is inactive the second write driver provides a complement write data signal to the output at the ground voltage. The second write data driver provides a complement write data signal to the output at the voltage below the ground voltage when the complement data signal is in the second logic state and the negative bit line enable signal is active. The control circuit provides the negative bit line enable signal in an active state when a power supply voltage is below a first threshold. Additionally, the control circuit provides the negative bit line enable signal in an inactive state when the power supply voltage is above a second threshold that is higher than the first threshold.
In another form, there is described a method for selectively boosting a differential bit line voltage on a bit line pair in a memory device. Access requests are received at the memory device. The memory device operates according to an initial power supply voltage. In response to detection of a change of a power supply voltage, a selection is made between enabling and disabling a negative bit line enable signal to the memory device. The selection is based at least in part on the power supply voltage. When the initial power supply voltage is below a first threshold the negative bit line enable signal is generated in response to detection of an active operating power state. Additionally, the negative bit line enable signal is generated in response to detecting an inactive operating power state when the initial power supply voltage is above a second threshold that is higher than the first threshold. A selected bit line of a bit line pair is driven to a negative voltage, in response to the negative bit line enable signal.
In yet another form, a memory includes true and complement bit lines forming a bit line pair. The true and complement bit lines are coupled to a plurality of memory cells. A write driver couples to the true and complement bit lines. Each memory cell, of the plurality of memory cells, stores a memory bit according to a differential voltage between the true and complement bit lines when the memory cell is selected during a write cycle. The write driver includes a first write driver, a second write driver, and a control circuit. The first write driver provides a true write data signal to the true bit line at a high voltage when a true data signal is in a first logic state. When the true data signal is in a second logic state and a negative bit line enable signal is inactive, the first write driver provides a true write data signal to the true bit line at a ground voltage. In response to the true data signal being in the second logic state and the negative bit line enable signal being active, the first write driver provides a true write data signal to the true bit line at a voltage below the ground voltage. The second write data driver provides a complement write data signal to the complement bit line at the high voltage when a complement data signal is in the first logic state. When the complement data signal is in the second logic state and the negative bit line enable signal is inactive the second write data driver provides a complement write data signal to the complement bit line at the ground voltage. The second write data driver provides a complement write data signal to the complement bit line at the voltage below the ground voltage when the complement data signal is in the second logic state and the negative bit line enable signal is active. The control circuit provides the negative bit line enable signal in an active state when a power supply voltage is below a first threshold. When the power supply voltage is above a second threshold higher than the first threshold the control circuit provides the negative bit line enable signal in an inactive state.
CPU core complex 110 includes a CPU core 112 and a CPU core 114. In this example, CPU core complex 110 includes two CPU cores, but in other embodiments CPU core complex 110 can include an arbitrary number of CPU cores. Each of CPU cores 112 and 114 is bidirectionally connected to a system management network (SMN), which forms a control fabric, data fabric 150. Each of CPU cores 112 and 114 is capable of providing memory access requests to interconnect 150. Each of CPU cores 112 and 114 may be unitary cores, or may further be a core complex with two or more unitary cores sharing certain resources such as caches.
Graphics core 120 is a high performance graphics processing unit (GPU) capable of performing graphics operations such as vertex processing, fragment processing, shading, texture blending, and the like in a highly integrated and parallel fashion. Graphics core 120 is bidirectionally connected to the SMN and to data fabric 150 and is capable of providing memory access requests to data fabric 150.
APU 100 may either support a unified memory architecture in which CPU core complex 110 and graphics core 120 share the same memory space, or a memory architecture in which CPU core complex 110 and graphics core 120 share a portion of the memory space, while graphics core 120 also uses a private graphics memory not accessible by CPU core complex 110.
Display engines 130 render and rasterize objects generated by graphics core 120 for display on a monitor. Graphics core 120 and display engines 130 are bi-directionally connected to a common memory management hub 140 for uniform translation into appropriate addresses in a connected memory system, and IOMMU 140 is bi-directionally connected to data fabric 150 for generating such memory accesses and receiving read data returned from the memory system.
Data fabric 150 includes a crossbar switch for routing memory access requests and memory responses between any memory accessing agent and memory controllers 190. It also includes a system memory map, defined by BIOS, for determining destinations of memory accesses based on the system configuration, as well as buffers for each virtual connection.
Peripheral controllers 162 is bi-directionally connected to input/output hub 176. Peripheral controllers 162 can include, for example a USB controller and a SATA interface controller. These two controllers are merely exemplary of peripheral controllers that may be used in APU 100.
Peripheral bus controllers 170 is bi-directionally connected to an input/output (I/O) hub 176 and to the SMN bus. Peripheral bus controllers 170 can include, for example, a system controller or “Southbridge” (SB) and a PCIe controller. I/O hub 176 bi-directionally connects to data fabric 150.
SMU 180 is a local controller that controls the operation of the resources on APU 100 and synchronizes communication among them. SMU 180 is the central thermal and power management controller for a data processing system that utilizes APU 100. SMU 180 includes power management firmware 182 and power manager 184. SMU 180 manages power-up sequencing of the various processors on APU 100 and controls multiple off-chip devices via reset, enable and other signals. SMU 180 includes one or more clock sources not shown in
Memory controller system 190 includes a set of memory controllers 192 and 194. Memory controllers 192 and 194 are bidirectionally connected to SMN bus 210. A host interface bidirectionally connects memory channel controller 190 to data fabric 150 over a scalable data port (SDP).
APU 100 also implements various system monitoring functions and detects various power management events. In particular, one system monitoring function is the operating voltage at given power states. For example, SMU 180 receives a supply voltage level to be used by a memory device at given power states. Accordingly, SMU 180 selectively enables the negative bit line signal during a descending voltage or disables the negative bit line for an ascending voltage. Further, in one embodiment, SMU 180 selectively reduces the negative bit line voltage as the supply voltage increases to the memory device. Consequently, SMU 180 is able to adaptively determine how much negative bit line is utilized, based on both the power state of the memory and the measured supply voltage, as discussed further below.
CPU core 212 has a bidirectional port connected to a first bidirectional port of shared L2 cache 220 over a bidirectional bus. CPU core 216 has a bidirectional port connected to a second bidirectional port of shared L2 cache 220 over a bidirectional bus. Shared L2 cache 220 has a third bidirectional port connected to a first bidirectional port of L3 cache and memory controller 222 over a bidirectional bus. Main memory controller 228 has a second bidirectional port connected to main memory over a bidirectional bus. In the illustrated embodiment, L2 cache 220 is shared between CPU core 212 and 216. In another embodiment, each CPU core 212 and 216 independently utilize a separate L2 cache. Further, other L2 cache and L3 cache configurations can be utilized in the operations of data processor 200.
In the example of
In operation, power management logic 304 changes P-states based, in part, on the utilization of processors associated with APU 100, for example, CPU core 112 and a CPU core 114. Power management logic 304 controls the sequencing of frequency and supply voltage (VDD) changes to effect the P-state changes. When increasing P-states, power management logic 304 increases the VDD accordingly, and then systematically increases the frequency. Device tree 305 provides a first threshold voltage (V1) and a second threshold voltage (V2) to power management logic 304. Device tree 305 is a data structure that describes the operating parameters of hardware components associated with APU 100. In one embodiment, SMU 302 periodically measures or polls for the operating voltage associated with the memory. Based on the measurement, power management logic 304 generates logic to control register 340. The logic to control register 340 enables assertion of negative bit line enable (NEGBLEN) signal in response to detecting an inactive operating power state when VDD is above a second threshold that is higher than the first threshold. Responsively, control register 340 provides a digital control signal, or NEGBLEN signal, to the memory that drives a selected bit line of a bit line pair within the memory to a negative voltage during write cycles. The memory can be, for example at least one of L1 cache 214, 218 and L2 cache 220, and L3 cache (and memory controller) 222.
In one embodiment, voltage regulator 330 outputs the initial power supply voltage, VDD, to memory, based on logic provided by power management logic 304. Power management logic 304 selects between enabling and disabling the NEGBLEN signal, to the memory device based at least in part on voltage transitions associated with VDD. Power management logic 304 provides the NEGBLEN signal (to be asserted via control register 340) in the active state when VDD is between V1 and V2. In response to a transition from the low voltage to the high voltage, power management logic 304 provides the negative bit line in an inactive state. In one embodiment V1 and V2 are predetermined threshold voltages. In another embodiment, V1 and V2 are a dynamically determined voltage. Power management logic 304 operates as a control circuit for selectively providing the negative bit line enable signal. The control circuit applies the negative bit line enable signal in an active state when VDD is below a first threshold. The control circuit applies the NEGBLEN signal in an inactive state when VDD is above a second threshold that is higher than the first threshold. The control circuit provides the negative bit line enable signal during write operations, enabling a non-asserted bit line voltage to lower below ground voltage during the write operations. Selectively enabling assertion of the NEGBLEN signal when the power supply voltage and operating frequency is low enough rather than at high operating voltages and turbo frequencies advantageously protects the memory device from voltage spikes and thereby mitigates degradation of the circuit. Further switching NEGBLEN signal off during the higher turbo frequencies/voltages and on for low frequencies/voltages diminishes circuit reliability complications in the memory device. In still another embodiment, to maintain V1 and V2 >0, and avoid hysteresis switching NEGBLEN on/off close to a single threshold, a Schmitt trigger or other single-threshold solution is utilized.
First write data driver 403 includes a NOR gate 404 that has a first input for receiving a true data signal, “wdt”. NOR gate 404 has a second input for receiving the negative bit line enable signal, “NEGBLEN”, and an output. First write data driver 403 also includes an inverter 408 that has an input for receiving the true data signal and an output. A pulldown transistor 406 has an input for receiving the power supply voltage, a gate connected to the output of NOR gate 404, and a drain forming an output of first write data driver 403. A pullup transistor 410 has a source connected to the drain of pulldown transistor 406. Further, pullup transistor 410 has a gate connected to the output of inverter 408, and a drain for receiving the ground voltage.
Second write data driver 405 includes a NOR gate 420 that has a first input for receiving compliment data signal, “wdc”. NOR gate 420 has a second input for receiving the negative bit line enable signal, and an output. Second write driver also includes an inverter 416. Inverter 416 has an input for receiving the compliment data signals, and an output. A pulldown transistor 422 has a source for receiving the power supply voltage, a gate connected to the output of NOR gate 420, and a drain forming the output of second write data driver 405. Further, pullup transistor 418 has a gate connected to the output of inverter 416, and a drain for receiving the ground voltage.
Negative charge pump 423 includes, in part, a delay driver that includes buffer 412 and inverter 414. Buffer 412 has an input for receiving the negative bit line enable signal, and an output. Inverter 414 has an input for receiving the output of buffer 412, and an output that forms the output of the delay driver. A capacitor 426 has a first terminal connected to the output of the delay driver, and a second terminal. A multiplexer, which includes a first multiplexer transistor 423 and a second multiplexer transistor 428. First multiplexer transistor 424 has a source connected to the output of first write data driver 403. Further, first multiplexer transistor 424 has a gate connected to the output of inverter 408, and a drain connected to the second terminal of capacitor 426. Second multiplexer transistor 428 has a source connected to the output of second write data driver 405. Second multiplexer transistor 428 has a gate connected to the output of inverter 416, and a drain connected to the second terminal of capacitor 426. The multiplexer is for selectively coupling the power supply voltage at the second terminal of capacitor 426 to a respective one of the output of first write data driver 403 and second write data driver 405 in response to values of the true, “wdt”, and complement, “wdc” data signals.
A bit line transistor 434 has a source connected to the output of first write driver 403, and a gate for receiving a write compliment signal (wrcs). The drain of bit line transistor 434 connects to true bit line 450. A complimentary bit line transistor 432 has a source connected to the output of second write data driver 405. Complimentary bit line transistor 432 has a gate for receiving the wrcs and a drain that connects to complimentary bit line 452. Memory cells 440a-n are a plurality of memory cells that connect to true bit line 450 and complement bit line 452.
In general, power management logic 304 asserts the NEGBLEN signal during a write cycle. The NEGBLEN signal dynamically lowers the bit line voltage below ground voltage during predetermined operating power states. Based on assertion of the NEGBLEN signal, write driver 402 provides a boost voltage to the memory cell in an active state when a power supply voltage is below a first threshold. The control circuit provides the negative bit line voltage to the memory cell in an inactive state when the power supply voltage is above a second threshold that is higher than the first threshold. Each memory cell stores a memory bit according to a differential voltage between true bit line 450 and complement bit line 452 pairs when selected during a write cycle.
In operation, in response to receiving a request for write operation to a memory cell (440a-n), the NEGBLEN signal asserts. When the NEGBLEN signal asserts first write data driver 403, second write data driver 405, and charge pump 423 receive the NEGBLEN signal from SMU 302. One of true bit line 450 and complement bit line 452 remains high as a precharged bit line, and the other bit line (in the pair) pulls low. Responsively, the write driver that pulls low turns off. For example, in response to a one bit on the input of NOR gate 404, pulldown transistor 406 receives a zero input at the gate, deactivating pulldown transistor 406 and turning off write driver 403. Concurrently, a rising edge at the gate of capacitor 426 initiates a switch capacitor event, or charge injection, that pulls the respective bit line, compliment bit line 452 to a voltage that is below VSS. Accordingly, a boost voltage is applied across the transmission gate of compliment bit line 452 as gate-to-source voltage (VGS), and is high enough to generate a voltage difference that is greater than VSS. When the voltage of compliment bit line 452 is below VSS, second write driver 405 can efficiently write to memory cell 440a.
In one embodiment, programmable bit line boost logic circuit 400 manages the amount of boost voltage a bit line receives when power management logic 304 asserts the NEGBLEN signal. In response to the VGS at a respective bit line going below VSS, the respective memory cell (e.g. 440a-440n) operates in a safe voltage range as long as VSS is below a predetermined “low” voltage. In response to a predetermined “high” VSS, the respective memory cell experiences reliability issues. Programmable bit line boost logic circuit 400 enables charge pump 423 to selectively manage the boost voltage so that the voltage input across the respective memory cell advantageously protects the memory cell from failing. Charge pump 423 controls how much voltage is generated across a respective memory cell based on the value of capacitor 426. Therefore, the value of capacitor 426 is selected to decrease the boost voltage when VSS is at a predetermined high voltage and increase the boost voltage when VSS is at a predetermined low voltage. In another embodiment, when VSS is highest, there is no boost voltage generated to the respective bit line. In one embodiment, true bit line 450 and compliment bit line 452 are driving 6T SRAM bit cells. In another embodiment, true bit line 450 and compliment bit line 452 drive 8T SRAM bit cells. Programmable bit line boost logic circuit 400 detects a write operation at a respective memory cell (440a). True bit line 450 stays precharged, while compliment bit line 452 pulls low. In response to the NEGBLEN signal being asserted inverter 416 turns off, if there is a “1” on NOR gate 420, transistor 418 is deactivated. The NEGBLEN signal passes to negative charge pump 423. A rising edge at second write data driver 405 creates a falling edge at negative charge pump 423 initiating a charge injection that couples compliment bit line 452 below VSS. True bit line 450 stays high. Once compliment bit line 452 is low memory cell 440a is written to.
Memory devices such as memory cell 440a selectively experience a voltage difference that is greater than VDD. A voltage difference greater than VDD is not disruptive to a cell when VDD is a low voltage. However, at a high VDD the voltage difference may cause reliability issues to ensue. Selectively asserting the NEGBLEN signal at low voltages and disabling the NEGBLEN signal at high voltages advantageously enables safe and reliable operation of SRAM memory cells for a broad range of voltages.
In one embodiment, first write data driver 403 provides wdt signal 506 to the output at a high voltage when wdt signal 506 is in a first logic state. When wdt signal 506 is in a second logic state and NEGBLEN signal 509 is inactive, first write data driver 403 provides wdt signal 506 to the output at a ground voltage. First write data driver 403 provides wdt signal 506 to the output at a voltage below the ground voltage when wdt signal 506 is in the second logic state and NEGBLEN signal 509 is active. Second write data driver 405 provides wdc signal 508 to the output at the high voltage when wdc signal 508 is in the first logic state. When wdc signal 508 is in the second logic state and NEGBLEN signal 509 is inactive, second write data driver 405 provides wdc signal 508 to the output at the ground voltage. Second write data driver 405 provides wdc signal 508 to the output at the ground voltage and at the voltage below the ground voltage when wdc signal 508 is in the second logic state and NEGBLEN signal 509 is active. Negative charge pump 423, connected at the output of first write data driver 403 and second write data driver 405 selectively provides a negative bit line voltage signal to true bit line 450 and complement bit line 452 pairs, leaving a second bit line of the bit line pair in a precharged state.
In another embodiment, there is a charge of VDD to zero volts across capacitor 426. In response to power management logic 304 asserting a high NEGBLEN signal 509 (input “1”), the high signal passes through buffer 412 and inverter 414 and outputs a low (output “0”) signal at capacitor 426. Consequently, nble x signal 516 goes low and capacitor 426 resists the instantaneous change in voltage. To maintain the voltage difference across the plates of capacitor 426, capacitor 426 pulls the respective node below ground. The signal activity is illustrated in
Referring now to
In one embodiment, the memory device has a maximum rated operating voltage, Vmax 606, and a minimum rated operating voltage, Vmin 612. Vmax 606 and Vmin 612 are predetermined voltages. Power management logic 304 enables the NEGBLEN signal to be asserted at low voltages and disables the NEGBLEN signal at high voltages. At a middle voltage range (between first voltage threshold 610 and second voltage threshold 608), where bit cells do not require a write assist to write data, enabling the NEGBLEN signal will not enable a voltage across the memory cell to exceed Vmax 606. Accordingly, the cross-over region 630, at a point such as intermediate operational voltage 620, is a safe region to disable the NEGBLEN signal when ascending from Vmin 612 to Vmax 606. Similarly, intermediate operational voltage 640, is a safe region to enable the NEGBLEN signal when descending from Vmax 606 to Vmin 612. Further, cross-over region 630 implements a voltage gap that enables hysteresis when switching to avoid continuously toggling NEGBLEN in the event that power supply voltage 614 is in close proximity to a single threshold.
In one embodiment, negative chare pump 423 is modified to provide a programmable charge pump circuit, charge pump 700. Granularity is achieved by modifying the capacitors and inverters of negative charge pump 423 to have multiple capacitors attached to a shared node and controlled by separate signals. The separate signals can be, for example, static signals, fuse signals, or signals controlled by SMU 302. In operation AND gates 724, 726, and 728 can enable or disable the assertion of the negative bit line signal based on control signals respectively input to AND gates 724, 726, and 728. As shown, capacitors 704, 706, and 708 are fused. In another embodiment, capacitors 704, 706, and 708 can be dynamically controlled based on the control voltages input to AND gates 724, 726, and 728. Charge pump 700 determines the number of stages to selectively enable based on an operating power state. Charge pump 700 selectively enables a number of stages of a plurality of parallel connected charge pump stages based on a value of the power supply voltage. In still another embodiment, the capacitors (704, 706, and 708) of charge pump 700 are configured to generate a percentage of the supply voltage as the negative bit line voltage to the memory device.
Charge pump 700 selectively provides the negative bit line voltage to the memory device. A programmable charge pump provides the advantage of reducing the amount of negative bit line voltage as the supply voltage increases. Reducing the negative bit line voltage as the supply voltage increases provides added power savings given that many bit lines are written, and each separate bit line pair requires a negative bit line voltage.
Some or all of the method illustrated in
While particular embodiments have been described, various modifications to these embodiments will be apparent to those skilled in the art. Memory controller 192 and 194 may interface to other types of memory besides SRAM memory, such as high bandwidth memory (HBM), RAMbus™ DRAM (RDRAM), and the like. Further, while particular embodiments have been described within APU 100, various modifications to these embodiments will be apparent to those skilled in the art. For example, an artificial intelligence engine can replace GPU 120, or CPU core complex 110 can be implemented without the use of graphics core 120. Although specific details such as specific structures, elements, and connections have been presented herein, it is to be understood that the specific details presented need not be utilized to practice embodiments of the present disclosure. It is also to be understood that other embodiments may be utilized and that logical, architectural, programmatic, mechanical, electrical and other changes may be made without departing from general scope of the disclosure. Accordingly, it is intended by the appended claims to cover all modifications of the disclosed embodiments that fall within the scope of the disclosed embodiments.
