Patent Application
20170179049
The invention relates to a power grid balancing, and more particularly, to utilizing the packaging dam for power grid balancing.
A System in Package (“SiP”) is a semiconductor device in which one or more integrated circuits (“ICs” or “die”), typically of different functionalities, which otherwise would have been realized using a number of individual chips, are combined into a complete electronic system in a single package. These functions may be implemented through digital or analog components and may include passive components. They are implemented within a single chip which performs as a system or a sub-system with an equivalent interface as in individually-packaged ICs. A SiP may contain multiple dies which within a SiP may be stacked vertically on a substrate either face-to-face or bottom-to-face. The dies may contain power supply wires that are bonded to the package to receive the required power from outside the SiP.
Combining multiple ICs into a single package raises several issues. One of these issues is the efficient delivery of sufficient power into all the dies within the SiP. Dependent on the physical structure of the SiP, the availability of a sufficient amount of pads for power supply for every die and the connections to these pads may become a challenge. In many prior art systems, combining the dies face-to-face makes it a challenge to provide enough power delivery resources to the dies, especially to the one which does not have accessible pads on it and has its data and power signals routed over the other die to the external world. In such cases, significantly more wiring resources may be allocated for routing the necessary signals, especially for the power supplies due to their high count. In other prior art systems, combining the dies back-to-face requires through-silicon-via (TSV) connections, which are expensive and require more area on the die. As die area is a precious commodity, methods balancing the power and reducing the additional area required for power delivery wiring are desired.
The connections between the vertically-stacked dies within a SiP may be established using copper pillars. Copper is a popular material for integrated circuits, especially between the dies, due to its excellent thermal and electrical properties. Copper pillar interconnections are more reliable and less resistive and therefore their usage result in better performance in terms of timing and area.
A prior art SiP with multiple semiconductor ICs organized face-to-face is shown in
More recent technologies have very stringent rules on the permitted voltage drop in the supply grid. Accordingly, any additional impact by the power supply wiring may therefore result in severe issues, such as lower performance, higher power consumption and reliability issues. Voltage drop may be increased further by unbalanced power supply wiring or pad availability due to physical limitations and a non-uniform distribution of power consumption on the die to be supplied.
When combining multiple semiconductor integrated circuits in a SiP, sufficient and balanced power delivery needs to be ensured. The necessity of supplying one die over the second die may increase the level of unbalance in the power distribution network, which may negatively impact the voltage drop requirements for the supplied devices, since there is already some inherent voltage drop in the supply network. Therefore, an improved method and system for connecting the power connections on the larger die and for providing a mechanism to balance all the power supply over the multiple power supply wires is desired.
A more complete appreciation of the invention is provided by reference to the following detailed description of the appended drawings and figures. The following descriptions, in conjunction with the appended figures, enable a person having skill in the art to recognize the numerous advantages and features of the invention by understanding the various embodiments. These drawings are provided to facilitate the reader's understanding of the invention and shall not be considered limiting of the breadth, scope, or applicability of the invention. It should be noted that for clarity and ease of illustration these drawings are not necessarily made to scale. The following figures are utilized to best illustrate these features.
Some of the figures included herein illustrate various embodiments of the invention from different viewing angles. Although the accompanying descriptive text may refer to such views as “top,” “bottom” or “side” views, such references are merely descriptive and do not imply or require that the invention be implemented or used in a particular spatial orientation unless explicitly stated otherwise.
The figures are not intended to be exhaustive or to limit the invention to the precise form disclosed. It should be understood that the invention can be practiced with modification and alteration, and that the invention be limited only by the claims and the equivalents thereof.
A multiple die system-in-a-package is disclosed. Any of the multiple dies may be a semiconductor integrated circuit. Power and ground to the top die are supplied over the bottom die. In one embodiment, the power distribution for the bottom die is balanced through the implementation of the power and ground supply through the dam rings. The power distribution for the top die is received from the bottom die through the copper pillars and receiving cavities. The power and the ground connections of the bottom die are coupled to a dam formed from metal and surrounding the second die like a ring. The top and bottom dies are stacked together and may be permanently mounted together. The power and ground wires are coupled to the dam, wherein the power transmitted through the power and ground wires is distributed through the dam and metal connectors to the top die. The dam spreads the power distribution throughout each side of the top die, reducing resistance of the supply network and hence voltage drops and power surges.
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A power supply wire (not shown) is connected to the pads to provide power to the die 200. The pads are coupled to the dam 204, forming a power supply mesh surrounding the second die 305. The dam 204 is then coupled to the second die 305 on any side to provide power and ground to the second die 305. In one embodiment, the dam 204 is coupled to the second die 305 through multiple pairs of power and ground on a single side of the second die 305. In another embodiment, the coupling of the dam 204 through multiple pairs of power and ground are provided on all four sides of the second die 305. Through the use of the dam 204 as a power balancing apparatus, the power supply from the die 200 to the dam 204 to the second die 305 result in reduced voltage drop, and maintains a balanced power supply voltage across the different sides and regions of second die 305. Further, the dam 204 provides a more uniform power consumption for the second die 305.
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The pad of the first die is coupled to the dam in step 725. In another embodiment the pad of the first die is coupled to the dam during formation. The dam may be a single ring or may be a plurality of rings or sections. The dam may be coupled to only a single side of the first die or the dam may be coupled to multiple sides of the first die. In one embodiment, the dam is coupled to the first die on every side. Further, the dam may be coupled to a side of the first die in pairs, one for power and one for ground. Additionally, multiple pairs may be provided between the dam and each side of the first die. The method ends at 735.
Although the invention is described herein with reference to specific embodiments, various modifications and changes can be made without departing from the scope of the invention as set forth in the claims below. Accordingly, the specification and figures are to be regarded in an illustrative rather than a restrictive sense, and all such modifications are intended to be included within the scope of the invention. Any benefits, advantages, or solutions to problems that are described herein with regard to specific embodiments are not intended to be construed as a critical, required, or essential feature or element of any or all the claims.
From time-to-time, the invention is described herein in terms of these example embodiments. Description in terms of these embodiments is provided to allow the various features and embodiments of the invention to be portrayed in the context of an exemplary application. After reading this description, it will become apparent to one of ordinary skill in the art how the invention can be implemented in different and alternative environments. Unless defined otherwise, all technical and scientific terms used herein have the same meaning as is commonly understood by one of ordinary skill in the art to which this invention belongs.
The preceding discussion is presented to enable a person skilled in the art to make and use the invention. The general principles described herein may be applied to embodiments and applications other than those detailed below without departing from the spirit and scope of the invention as defined by the appended claims. The invention is not intended to be limited to the embodiments shown, but is to be accorded the widest scope consistent with the principles and features disclosed herein.
In addition, while a particular feature of the invention may have been disclosed with respect to only one of several embodiments, such feature may be combined with one or more other features of the other embodiments as may be desired. It is therefore, contemplated that the claims will cover any such modifications or embodiments that fall within the true scope of the invention.
The various diagrams may depict an example architectural or other configuration for the invention, which is done to aid in understanding the features and functionality that can be included in the invention. The invention is not restricted to the illustrated example architectures or configurations, but the desired features can be implemented using a variety of alternative architectures and configurations. Indeed, it will be apparent to one of skill in the art how alternative functional, logical or physical partitioning and configurations can be implemented to implement the desired features of the invention. Also, a multitude of different constituent module names other than those depicted herein can be applied to the various partitions. Additionally, with regard to flow diagrams, operational descriptions and method claims, the order in which the steps are presented herein shall not mandate that various embodiments be implemented to perform the recited functionality in the same order unless the context dictates otherwise.
Terms and phrases used in this document, and variations thereof, unless otherwise expressly stated, should be construed as open ended as opposed to limiting. As examples of the foregoing: the term “including” should be read as meaning “including, without limitation” or the like; the term “example” is used to provide exemplary instances of the item in discussion, not an exhaustive or limiting list thereof; the terms “a” or “an” should be read as meaning “at least one”, “one or more” or the like; and adjectives such as “conventional”, “traditional”, “normal”, “standard”, “known” and terms of similar meaning should not be construed as limiting the item described to a given time period or to an item available as of a given time, but instead should be read to encompass conventional, traditional, normal, or standard technologies that may be available or known now or at any time in the future. Likewise, where this document refers to technologies that would be apparent or known to one of ordinary skill in the art, such technologies encompass those apparent or known to the skilled artisan now or at any time in the future.
A group of items linked with the conjunction “and” should not be read as requiring that each and every one of those items be present in the grouping, but rather should be read as “and/or” unless expressly stated otherwise. Similarly, a group of items linked with the conjunction “or” should not be read as requiring mutual exclusivity among that group, but rather should also be read as “and/or” unless expressly stated otherwise. Furthermore, although items, elements or components of the invention may be described or claimed in the singular, the plural is contemplated to be within the scope thereof unless limitation to the singular is explicitly stated.
The presence of broadening words and phrases such as “one or more”, “at least”, “but not limited to” or other like phrases in some instances shall not be read to mean that the narrower case is intended or required in instances where such broadening phrases may be absent. The use of the term “module” does not imply that the components or functionality described or claimed as part of the module are all configured in a common package. Indeed, any or all of the various components of a module, whether control logic or other components, can be combined in a single package or separately maintained and can further be distributed across multiple locations.
Unless stated otherwise, terms such as “first” and “second” are used to arbitrarily distinguish between the elements such terms describe. Thus, these terms are not necessarily intended to indicate temporal or other prioritization of such elements.
Additionally, the various embodiments set forth herein are described in terms of exemplary block diagrams, flow charts and other illustrations. As will become apparent to one of ordinary skill in the art after reading this document, the illustrated embodiments and their various alternatives can be implemented without confinement to the illustrated examples. For example, block diagrams and their accompanying description should not be construed as mandating a particular architecture or configuration.
