Patent Application
20230411514
The present application is directed to a power semiconductor device.
Document WO 2014/204491 A1 refers to a low loss power SiC MOSFET.
U.S. Pat. No. 8,436,367 B1 refers to a SiC power vertical DMOS with increased safe operating area.
Documents US 2016/0064550 A1 provides an insulated gate type switching device which includes: a first region being of a first conductivity type; a body region being of a second conductivity type and in contact with the first region; a 30 second region being of the first conductivity type and separated from the first region by the body region; an insulating film being in contact with the first region, the body region and the second region; and a gate electrode facing the body region via the insulating film. The body region includes a first body region and a second body region. The first body region has a theoretical threshold level Vth larger than that of the second body region.
Documents US 2016/0225905 A1 and US 2020/0259012 A1 refer to semiconductor devices comprising a gate electrode.
A problem to be solved is to provide a power semiconductor device having an improved switching behavior.
Embodiments of the disclosure relate to a power semiconductor device as defined in the independent patent claim. Exemplary further developments constitute the subject matter of the dependent patent claims.
The power semiconductor device may be based on a wide bandgap material and comprises a gate electrode and a gate insulator that may fully or partially comprise a high-k material. The gate insulator has a varying dielectric capacitance which is, for example, larger at edges than in a central region. The wide bandgap material is for example, based on SiC.
By means of such a gate insulator, a lower resistance in an on-state of the device and also comparably short switching times can be maintained.
In at least one embodiment, the power semiconductor device comprises a semiconductor body having at least one source region. Further, the power semiconductor device comprises a gate electrode at the semiconductor body and a gate insulator between the semiconductor body and the gate electrode. At least one well region is located at the at least one source region and at the gate insulator. The gate insulator has a varying dielectric capacitance, the dielectric capacitance may be in each case a quotient of a total dielectric constant and of a geometric thickness of the gate insulator at a specific location thereof. The dielectric capacitance is larger at the at least one well region than in remaining regions of the gate insulator. Optionally, seen in cross-section, the gate insulator is composed of two first gate insulator regions having the larger dielectric capacitance and of a central, second gate insulator region having the smaller dielectric capacitance, the at least one well region is in direct contact only with the first gate insulator regions and not with the second gate insulator region.
In other words, the dielectric capacitance is Cdielectric=ε ε0/t, with ε being the relative dielectric constant, ε0 being the vacuum permittivity and t being the geometric thickness of the gate insulator. Cdielectric is lower on a junction field effect transistor region, JFET region for short, than on a channel region. The channel region may refer to a region where the at least one well region is close to the gate insulator, and the JFET region may refer to a central region of the gate electrode, seen in top view of the gate electrode.
The relative dielectric constant may also be referred to as relative permittivity, abbreviated ε or κ, respectively, or also simply referred to as k. The relative dielectric constant, for example, refer to the value measured at a temperature of 300 K and, for example, at a frequency of 1 kHz, but not limited to that.
Here and in the following, the term ‘gate insulator’ may refer to the insulator beneath the gate electrode, i.e between the gate electrode and the semiconductor body. For example, further electrically insulating material on top of the gate electrode, that is, on a side of the gate electrode remote from the semiconductor body, and the like may not be meant by the term ‘gate insulator’, but only the insulating material that ensures electric insulation immediately between the gate electrode and the semiconductor body.
The term ‘source region’ may refer both to a source in a field-effect transistor and to an emitter in a bipolar transistor.
Thus, the power semiconductor device can be a silicon carbide (short: SiC) metal-oxide-semiconductor field-effect transistor (short: MOSFET) or a SiC metal-insulator-semiconductor field-effect transistor (short: MISFET) with variable dielectric regions for improved switching behavior. For example, a power MOSFET based on silicon carbide material is described. The gate insulator is partially or completely formed with at least one high-k material. In addition, the gate insulator is divided into two sections: A first one overlapping a channel area, and a second one extending on a JFET region. The dielectric extending on the JFET region can be made with a different material and/or a different layer thickness, compared to the first one. The described gate structure allows to exploit the advantages of a high-k dielectric in conduction without slowing down the device switching.
Otherwise, using a high permittivity material increases a capacitance seen from a gate terminal, that would turn into slower switching speeds. Using the described two-zone gate insulator with different materials and/or thicknesses allows to decrease the gate capacitance.
Silicon carbide power semiconductor devices may replace their silicon-based counterparts, for example, in low voltage applications with voltages of 650 V to 1.2 kV. Even though the SiC market is mostly driven by low voltage devices, the use of ≥3.3 kV SiC power MOSFETs for medium voltage and high voltage systems, like traction applications, has also attracted more attention. Despite superior material's properties, there are still some issues that have to be tackled before the widespread use of SiC power devices in different applications. For example, most of the effort are focused on improving the quality of the gate dielectric/silicon carbide interface. It is known, indeed, that during the oxidation process to form the gate insulator, like SiO2, several interface trap states and defects are originated, that lay within the bandgap of SiC. These defects heavily degrade the inversion channel mobility due to charge trapping and Coulomb scattering mechanisms.
The use of high-k material for the gate insulator implies that, for the same applied voltage and dielectric thickness, the number of carriers in the inversion channel is higher. The result is a lower resistance between drain and source in a turned-on state, also referred to as RDS, ON. In addition, it has also been proven that high-k gate dielectrics provide high threshold voltage stability and lower interface states density. However, one drawback of high permittivity materials is that the gate capacitance, for example, the gate-source capacitance CGS and the gate-drain Miller capacitance CGD, has a higher value, which turns into lower switching speeds.
Herein, an improved structure for the gate insulator is described. Compared with a gate dielectric having a constant dielectric capacitance, the structure described herein is divided in different regions: the first insulator gate regions extend on the channel region and are formed, for example, with at least one high-k material; the second insulator gate region corresponds to the JFET area with different configurations: it can be formed with SiO2 having the same thickness like at the channel region, or it can be thicker and be formed either with SiO2 or a high-k material, or combinations thereof. Hence, one design feature of the device described herein is to have a lower dielectric capacitance of the gate insulator extending on the JFET area, so to further decrease the gate capacitance.
According to at least one embodiment, the semiconductor body is of SiC. However, the semiconductor body can alternatively be of Si or of a high-bandgap compound semiconductor material like Ga2O3 or GaN.
According to at least one embodiment, the power semiconductor device is a field-effect transistor or an insulated gate bipolar transistor, IGBT for short. For example, the power semiconductor device described herein is or is comprised in, for example, a MOS-based SiC trench device or planar device such as MOSFETs and IGBTs. Hence, the power semiconductor device is or can be present in, for example, a device selected from the group comprising or consisting of a metal-oxide-semiconductor field-effect transistor (MOSFET), a metal-insulator-semiconductor field-effect transistor (MISFET), an insulated-gate bipolar transistor (IGBT).
According to at least one embodiment, the gate insulator comprises a first material and a second material. The second material has a higher relative dielectric constant than the first material and can consequently be a high-k material. For example, the ratio between the relative dielectric constants of the second material and the first material varies between 1.2 and 5, for example, by at least a factor of 1.2 or by at least a factor of 1.5 or by at least a factor of 2.5 and/or by at most a factor of 4.5. For example, the first material is SiO2, and the second material is selected, for example, from the following group: Si3N4, Al2O3, Y2O3, ZrO2, HfO2, La2O3, Ta2O5, TiO2.
According to at least one embodiment, only the second material is present directly on the channel region, that is, directly on the well region. It is possible that the first, low-k material is applied only at locations distant from the well region so that the first material may be limited to the JFET region.
According to at least one embodiment, the second material is present as a continuous layer. Said continuous layer can completely extend between the gate electrode and the semiconductor body. Hence, there may be no direct, straight connection line between the gate electrode and the semiconductor body without running through the second material, that is, the high-k material.
According to at least one embodiment, the first material is located at a side of the second material remote from the semiconductor body. In this case, the second material can be in direct contact with the semiconductor body, and the first material may be distant from the semiconductor body and not in direct contact with the semiconductor body. For example, the second material is applied to the semiconductor body first as the continuous layer and then the first material is applied in a structured manner, or vice versa.
According to at least one embodiment, the continuous layer of the second material has a constant geometric layer thickness. The term ‘constant geometric layer thickness’ may tolerate thickness variations of at most 10% or of at most 5% of a maximum thickness of said layer. Hence, accidental thickness variations, for example, due to manufacturing tolerances, shall not be regarded as a varying thickness in the present context.
According to at least one embodiment, the second material is located at a side of the first material remote from the semiconductor body. In this case, both the first material and the second material can be in direct contact with the semiconductor body. For example, the first material is applied to the semiconductor body in a structured manner so that only part of the semiconductor body is covered by the first material in the later gate electrode region, and then the first material is applied, for example, as the continuous layer that may have a constant thickness in this case, too.
According to at least one embodiment, the gate insulator is of constant geometric thickness. In this case, the first material and the second material are located next to one another in a common plane. For example, both materials are applied directly on a top side of the semiconductor body with a constant thickness. For example, both materials are applied in a disjunctive and non-overlapping manner when seen in top view of the top side. The first and the second material may thus directly adjoin one another without overlapping each other. Otherwise, the first and second material may overlap, for example, due to a manufacturing process.
According to at least one embodiment, the gate insulator is of exactly one material. Hence, the gate insulator has a non-varying relative dielectric constant and consequently a varying geometric thickness.
According to at least one embodiment, the geometric thickness of the gate insulator is largest in a central part of the gate insulator, seen in cross-section. The term ‘cross-section’ may refer to a plane perpendicular to the top side of the semiconductor body and perpendicular to a direction of main extent of the gate electrode, for example, if the gate electrode is a strip electrode, seen in top view of the top side. The central part of the gate insulator is that region of the gate insulator, which is in direct contact to the drift layer.
According to at least one embodiment, the gate electrode is of planar configuration. Hence, the gate electrode is located on a top side of the semiconductor body and the top side is of planar fashion. In this case, neither the gate electrode nor the gate insulator penetrate in the semiconductor body.
According to at least one embodiment, the gate electrode is of trench configuration. In this case, the gate electrode extends into a trench of the semiconductor body. For example, the gate insulator covers side walls of trench and a bottom of the trench and the gate electrode is embedded in the gate insulator in the trench.
According to at least one embodiment, the gate electrode reaches deeper into the semiconductor body than the at least one well region and/or than the at least one source region. Consequently, the gate insulator, too, has a depth greater than a depth of the at least one well region and/or than the at least one source region. ‘Depth’ may refer to a direction running away and in perpendicular to the top side of the semiconductor body.
According to at least one embodiment, the at least one well region and/or the at least one source region directly adjoins the trench. Hence, the at least one well region and/or the at least one source region can be in direct contact with the gate insulator at the side walls of the trench.
According to at least one embodiment, the gate insulator is composed of two, or of more than two, first gate insulator regions having the larger dielectric capacitance and of one, or of at least one, central, second gate insulator region having the smaller dielectric capacitance. This applies, for example, seen in cross-section perpendicular to the top side of the semiconductor body through the gate electrode. Seen in said cross-section, the first gate insulator regions can be located at edges of the gate electrode, and the second gate insulator region can be located at a middle portion of the gate electrode.
According to at least one embodiment, for example, seen in cross-section perpendicular to the top side of the semiconductor body through the gate electrode, the at least one well region is in direct contact only with at least one of the first gate insulator regions and not with the second gate insulator region. Thus, the at least one well region can be limited to the respective first gate insulator region having the higher dielectric capacitance.
According to at least one embodiment, the semiconductor body further comprises a drift region. The drift region and the at least one source region can be of a first conductivity type, for example, of n-conducting type and therefore can be n-doped. For example, the at least one source region and the at least one well region are embedded in the drift region so that a bulk of the semiconductor body may be composed of the drift region. The drift layer may have a homogeneous doping concentration.
According to at least one embodiment, the at least one well region is of a second conductivity type different from the first conductivity type. For example, the at least one well region is of p-conducting type and thus is p-doped. It is possible that the at least one well region completely separates the respective source region from the drift region within the semiconductor body so that there is no direct contact between the respective source region and the drift region.
According to at least one embodiment, for example, seen in cross-section perpendicular to the top side of the semiconductor body through the gate electrode, the only region of the semiconductor body the second gate insulator region is in contact with is the drift region. Hence, the second gate insulator region may be distant from the at least one well region and form the at least one source region.
According to at least one embodiment, for example, seen in cross-section perpendicular to the top side of the semiconductor body through the gate electrode, the first gate insulator regions are in contact with the at least one source region and/or with the at least one well region as well as with the drift region. Hence, the first gate insulator regions can be close to all these three regions of the semiconductor body. However, a proportion of the first gate insulator regions in contact with the drift region is, for example, smaller that a proportion being in contact with the at least one source region and/or with the at least one well region.
According to at least one embodiment, the semiconductor further comprises a collector layer. The collector layer is of the same conductivity type as the well region. The collector layer may be located at a bottom side of the semiconductor body opposite the top side. There can be one collector layer for all the source regions. A collector electrode can be directly applied to the collector layer. If there is a collector layer, the power semiconductor device can be an IGBT.
According to at least one embodiment, the semiconductor further comprises at least one drain region. The drain region is of the same conductivity type as the at least one source region. For example, the drain region is a layer at the bottom side. For example, the drift region is located between the top side and the drain region. There can be one common drain region for all the source regions. A drain electrode may be in direct contact with the at least one drain region. If there is a drain region, the power semiconductor device can be a MOSFET or a MISFET. The drain layer has a higher doping concentration than the drift layer.
According to at least one embodiment, a proportion of the second gate insulator region along an interface of the gate electrode facing the semiconductor body is at least 20% or is at least 30% or at least 40% and/or at most 80% or at most 70% or at most 60% of an overall extent of said interface.
The interface may be a contact face between the gate insulator and the semiconductor body. The above-stated values apply, for example, seen in cross-section perpendicular to the top side of the semiconductor body, for example, along a shortest line across the gate electrode. If the gate electrode is of planar fashion, the interface may run along a straight line, and if the gate electrode is of trench design, the interface may be of U-shape when seen in cross-section.
According to at least one embodiment, seen in cross-section, the first gate insulator regions are located along the interface symmetrically around the second gate insulator region. Hence, there can be a line of mirror symmetry through the gate insulator concerning the design of the first and second gate insulator regions, seen in cross-section.
According to at least one embodiment, the geometric thickness of the overall gate insulator is at least 5 nm or at least nm or at least 100 nm. Alternatively or additionally, this geometric thickness is at most 1.5 μm or at most 0.8 μm or at most 0.5 μm.
According to at least one embodiment, the semiconductor body comprises at least one plug. For example, the plug is in direct contact to the source electrode to provide an electric contact with the at least one assigned well region. For example, the at least one plug and the at least one well region are of the same conductivity type, wherein the at least one plug can be doped more strongly.
According to at least one embodiment, the power semiconductor device comprises at least two of the source regions and a source electrode. The source electrode is in electric contact, for example, in direct contact, with the at least two of the source regions. Hence, said at least two source regions can be on the same electric potential. As an option, the source electrode may also be in direct contact with the at least one plug.
According to at least one embodiment, seen in cross-section perpendicular to the top side, the gate electrode is located between two of the at least two source regions. Hence, two source regions can be assigned to one gate electrode. The source regions may be arranged in a symmetric manner next to the respective gate electrode.
According to at least one embodiment, seen in cross-section perpendicular to the top side, the source electrode partially or completely covers the gate electrode on a side remote from the semiconductor body. The source electrode and the gate electrode are electrically insulated by one or more layers of one or more insulating materials. Hence, the source electrode can be a common electrode of the at least two assigned the source regions.
According to at least one embodiment, the power semiconductor device is of a cell design. This may mean that, seen in top view, the gate electrode is of, for example, but not limited to, square or nearly square shape. Otherwise, the power semiconductor device can be of a stripe design so that the gate electrode is considerably longer than wide. Both in the cell design and the stripe design, there can be a plurality of the gate electrodes.
According to at least one embodiment, the power semiconductor device is a power device. For example, the power semiconductor device is configured for a maximum current through the drain electrode or the collector layer of at least 1 A or of at least 20 A. Alternatively or additionally, the power semiconductor device is configured for a maximum voltage of at least 0.1 kV or of at least 0.6 kV or of at least 1.2 kV.
The power semiconductor device is, for example, for a power module in a vehicle to convert direct current from a battery to alternating current for an electric motor, for example, in hybrid vehicles or plug-in electric vehicles. Moreover, the power semiconductor device can be a fuse, for example, in a vehicle like a car. It is also possible that the power semiconductor device is used in an electric train or in railway systems, for example, as a converter.
A power semiconductor device is explained in greater detail below by way of exemplary embodiments with reference to the drawings. Elements which are the same in the individual figures are indicated with the same reference numerals. The relationships between the elements are not shown to scale, however, but rather individual elements may be shown exaggeratedly large to assist in understanding.
In
As an option, there are two plugs 25 at the top side 20 to provide electric contact with the well regions 22. For example, the source regions 21 as well as the well regions 22 are electrically contacted by a source electrode 31. The drain region 24 may electrically be contacted by a drain electrode 32.
For example, the source regions 21 and the drain region 24 are n+-doped and the drift region 23 is n−-doped; the well regions 22 are p-doped and the optional plugs 25 are p+-doped. Otherwise, the doping types could all be inverted.
For example, maximum doping concentrations of the source regions 21, the drain region 24 and the plugs are at least 1×1018 cm−3 or at least 5×1018 cm−3 or at least 1×1019 cm−3 and/or at most 5×1020 cm−3 or at most 2×1020 cm−3 or at most 1×1020 cm−3. Further, a maximum doping concentration of the well region 22 may be at least ×1016 cm−3 or at least 1×1017 cm−3 and/or at most 5×1019 cm−3 or at most 5×1018 cm−3. Depending on the voltage class of the power semiconductor device 1, a maximum doping concentration of the drift region 23 may be at least 1×1014 cm−3 or at least 5×1014 cm−3 or at least 1×1015 cm−3 and/or at most 1×1017 cm−3 or at most 5×1016 cm−3 or at most 1×1016 cm−3.
The semiconductor body 2 may be composed of a substrate and of an epitaxially grown semiconductor section, or only of an epitaxially grown semiconductor section. Depending on the presence of a substrate, for example, the substrate is included in the drain region 24, and the drift region 23 is grown on top thereof. A drift region thickness can range, for example, from 3 μm to 0.2 mm and/or a drain region thickness may be between 1 μm and 0.5 mm inclusive.
Moreover, the power semiconductor device 1 includes a gate electrode 3 at the top side 20 located between the well regions 22 at the drift region 23. For example, the gate electrode 3 is of a metal or of a highly conductive semiconductor material like poly-Si.
Between the gate electrode 3 and the semiconductor body 2, there is a gate insulator 4. The gate insulator 4 comprises two different zones, that is, two first gate insulator regions 41 and one second gate insulator region 42. The second gate insulator region 42 has a smaller dielectric capacitance than the first gate insulator regions 41. At every specific location of the gate insulator 4, the respective local dielectric capacitance refers to a quotient of a total dielectric constant and a local geometric thickness of a local material. In case of the planar design of
According to
The second gate insulator region 42 is in contact with the semiconductor body 2 only at the drift region 23 whereas the first gate insulator regions 41 touch the source regions 21, the well regions 22 and, for example, to a less proportion, the drift region 23. The first gate insulator regions 41 are arranged in a mirror symmetric manner next to the second gate insulator region 42. All the first gate insulator regions 41 and the second gate insulator regions 42 are located in a plane parallel to and directly on the top side 20.
Other than shown in
The gate electrode 3 and, thus, the gate insulator 4 may be of strip shape so that a length of the gate electrode 3 along a length direction G is larger than a width of the gate electrode 3. Otherwise, the power semiconductor device may be of a cell design so that the gate electrode 3 is of, but not limited to, square shape or approximately of square shape. The cross-sections below are perpendicular to the length direction G.
In the exemplary embodiment of
The overall stack of gate insulator 4 and gate electrode 3 together may be of constant thickness so that the gate electrode 3 may be of U-shape when seen in cross-section.
Otherwise, the same as to
In the exemplary embodiment of
Moreover, the power semiconductor device 1 can include a top gate insulator region 6 located at a side of the gate electrode 3 remote from the semiconductor body 2. The top gate insulator region 6 may electrically separate the source electrode 31 from the gate electrode 3. Such a top gate insulator region 6 can also be present in the power semiconductor devices 1 of
For example, the gate insulator 4 has an overall width W which is, for example, at least 1 μm and/or at most 20 μm. Along the top side 20, the second gate insulator region 42 has a width W2 and each one of the first gate insulator regions 41 have a width W1 so that W=W2+2×W1.
Otherwise, the same as to
According to
For example, seen in cross-section, the coating can have a trapezoidal shape so that it becomes narrower in the direction away from the top side 20. The overall stack of gate insulator 4 and gate electrode 3 together may be, for example, of constant thickness like in
Otherwise, the same as to
Also the gate insulator 4 of
Otherwise, the same as to
According to
Otherwise, the same as to
According to
At side walls 51 of the trench 5, there are the first gate insulator regions 41, and at a trench bottom 52 there is the second gate insulator region 42. Along the side walls 51, the first gate insulator regions 41 have a first length L1. A depth of the trench 5 corresponds to a sum of the first length L1 and a second length L2. A width of the trench 5 corresponds to a third length L3. For example, the length L2 is larger than a thickness of the first gate insulator regions 41, seen perpendicularly to the sidewall or the channel.
That is, seen in cross-section, an interface between the gate insulator 4 and the semiconductor body 2 has an overall length L=L1+L2+L3+L2+L1, whereas the second gate insulator region 42 has consequently a length L*=L2+L3+L2. At the trench bottom 52, a geometric thickness of the second gate insulator region 42 is L2.
The first and the second gate insulator regions 41, 42 can be of the same material, for example, of the second material M2.
Otherwise, the same as to
According to
Otherwise, the same as to
In the embodiment of
Otherwise, the same as to
According to
Otherwise, the same as to
In the embodiment of
Otherwise, the same as to
According to
Otherwise, the same as to
In the power semiconductor device 1 of
Otherwise, the same as to
In
Although the IGBT of
In
To prove the positive effect of the gate insulator design described herein, in
The curves C refer to the respective gate insulator 4 described above in context of
From
The invention described here is not restricted by the description given with reference to the exemplary embodiments. Rather, the invention encompasses any novel feature and any combination of features, including in particular any combination of features in the claims, even if this feature or this combination is not itself explicitly indicated in the claims or exemplary embodiments.
| Number | Date | Country | Kind |
|---|---|---|---|
| 21159962.6 | Mar 2021 | EP | regional |
This application is a continuation application of International Patent Application PCT/EP2022/052061, filed Jan. 28, 2022, which claims priority to European Patent Application No. 21159962.6, filed on Mar. 1, 2021, the contents of which are incorporated herein by reference.
| Number | Date | Country | |
|---|---|---|---|
| Parent | PCT/EP2022/052061 | Jan 2022 | US |
| Child | 18240304 | US |
