Patent Application
20230378280
The present disclosure relates to the technical field of high-frequency high-electron-mobility field effect transistors, particularly to a preparation method of a double-T-shaped gate based on double-layer passivation accurate etching.
High-electron-mobility transistors represented by AlGaN/GaN and GaAs/AlGaAs heterojunction structures feature high frequency, high speed, high voltage resistance, and high power and are widely used in the radio frequency microwave field. The gate preparation process greatly affects the high-frequency performance of the device. To obtain high-gain, low-noise, and high-speed radio frequency devices, the key requirement is to reduce the gate length. However, the reduction of the gate length increases the gate resistance, affecting the high-frequency performance of the device. At present, the T-shaped gate process has been recognized as the mainstream technology for the preparation of high-frequency devices. The short gate root ensures the high-frequency performance of the device, while the long gate cap reduces the gate resistance. Therefore, it is of great importance to study and optimize the preparation process of the T-shaped gate.
At present, the mainstream method of preparing the T-shaped gate is an electron beam lithography tri-layer photoresist process. This process is extremely tedious since it requires three times of exposure and development. Moreover, to prevent mixing between photoresist layers, multiple baking and development processes are needed to obtain a T-shaped gate pattern. With an increasingly high requirement on the reliability of radio frequency devices, the devices are not only required to have high frequency and high power but also required to have a weak current collapse effect. Therefore, there is an urgent need to improve the T-shaped gate process. A double-T-shaped gate is obtained by adding a gate cap on top of the T-shaped gate. The added gate cap not only reduces the gate resistance but also disperses the electric field in the gate-drain region, thereby increasing the device breakdown voltage and suppressing the virtual gate effect. However, the double-T gate process is more tedious and more difficult to control. Additionally, it is difficult to control the thickness of the gate root metal and the gate cap metal. There is an urgent need to design a preparation method to simplify the double-T-shaped gate process and improve the device's reliability.
To overcome the disadvantages and shortcomings of the prior art, the present disclosure provides a preparation method of a double-T-shaped gate based on double-layer passivation accurate etching.
This method implements the preparation of a double-T-shaped gate by accurately etching two passivation layers with a high selectivity ratio. The preparation process can reduce the gate resistance and passivate the radio frequency device, which increases the breakdown voltage while reducing the virtual gate effect and avoiding current collapse, thereby improving the device's reliability.
The present disclosure adopts the following technical solutions:
A preparation method of a double-T-shaped gate based on double-layer passivation accurate etching is provided.
A double-T-shaped gate includes a gate root, a lower gate cap, and a top gate cap from bottom to top. The bottom of the gate root is in contact with an epitaxial structure, and the sidewall of the gate root is in contact with the bottom passivation layer. The bottom of the lower gate cap is in contact with the upper surface of the bottom passivation layer, and the sidewall of the lower gate cap is in contact with the top passivation layer. The bottom of the top gate cap is in contact with the upper surface of the top passivation layer, and the sidewall of the top gate cap is in contact with air.
The preparation method specifically includes:
Further, the preparation method specifically includes the following steps:
Further, the width of the top gate cap is greater than the width of the lower gate cap, and the width of the lower gate cap is greater than the width of the gate root.
Further, the top passivation layer is SiO2, the bottom passivation layer is SiN, and the two passivation layers are grown using plasma-enhanced chemical vapor deposition (PECVD), low-pressure chemical vapor deposition (LPCVD), and atomic layer deposition (ALD). This method does not require particular thicknesses of the top passivation layer and the bottom passivation layer and maximizes the degree of freedom of the device structure design.
Further, the dry etching in S3 is plasma etching, and the etching atmosphere is a fluorinated gas.
Further, the width of the top gate cap exposure region is greater than the width of the lower gate cap exposure region, and the width of the lower gate cap exposure region is greater than the width of the gate root exposure region.
Further, the etching solution used in the wet etching in S5 is the BOE solution, which can hardly etch the SiN layer, thereby ensuring the accuracy of the gate root width.
Further, metal evaporation is implemented by physical vapor deposition with a metal lift-off process.
Further, the two passivation layers are grown using PECVD.
The present disclosure has the following beneficial effects:
The present disclosure is further described below by referring to the embodiments and accompanying drawings, but the implementations of the present disclosure are not limited thereto.
This embodiment provides a preparation method of a double-T-shaped gate based on double-layer passivation accurate etching and specifically provides a method for preparing a double-T-shaped gate AlGaN/GaN HEMT device based on double-layer passivation accurate etching. As shown in
The structure of the prepared product is shown in
Preferably, the etching in step (1) and step (2) is performed by inductively coupled plasma (ICP) etching with an etching gas of a mixture of Cl2 and BCl3, a pressure of 5 mTorr, an upper radio frequency power of 300 W, a lower radio frequency power of 50 W, and an etching time of 150 s and an etching time of 80 s, respectively.
Preferably, the source and drain metal electrodes in step (3) are made of an alloy of Ti, Al, Ni, and Au.
Preferably, the annealing in step (3) is performed in an atmosphere of N2 with an annealing temperature of 850° C., a temperature holding time of 30 s, and a heating rate of 15° C./s.
Preferably, the double passivation layers in step (4) are grown using PECVD, where the thicknesses of SiO2 and SiN are 50 nm and 200 nm, respectively.
Preferably, the gate root region in step (5) has a length of 100 nm.
Preferably, the dry etching in step (5) uses a gas of SF6 with a pressure of 5 mTorr, an upper radio frequency power of 300 W, a lower radio frequency power of 50 W, and an etching rate of 1 nm/s.
Preferably, the wet etching in step (6) uses a BOE solution.
Preferably, the lower gate cap region in step (6) has a length of 300 nm.
Preferably, the top gate cap region in step (7) has a length of 500 nm.
Preferably, the gate metal electrode in step (7) is composed of two metals: Ni and Au.
Preferably, the gate/source/drain metal electrode in step (9) is composed of two metals: Ni and Au.
The transfer characteristic curve and the output characteristic curve of the double-T-shaped gate AlGaN/GaN HEMT prepared in Embodiment 1 are shown in
Embodiment 2 provides a preparation method of a double-T-shaped gate based on double-layer passivation accurate etching, which is specified as follows:
Preferably, the etching in step (1) and step (2) is ICP etching with an etching gas of a mixture of Cl2 and BCl3, a pressure of 5 mTorr, an upper radio frequency power of 300 W, a lower radio frequency power of 50 W, and an etching time of 150 s and an etching time of 80 s respectively.
Preferably, the source and drain metal electrodes in step (3) are made of an alloy of Ti, Al, Ni, and Au.
Preferably, the annealing in step (3) is performed in an atmosphere of N2, with an annealing temperature of 850° C., a temperature holding time of 30 s, and a heating rate of 15° C./s.
Preferably, the passivation layers in step (4) are grown using LPCVD, where thicknesses of SiO2 and SiN are 200 nm and 50 nm respectively.
Preferably, the dry etching in step (5) uses a gas of SF6, with a pressure of 5 mTorr, an upper radio frequency power of 300 W, a lower radio frequency power of 50 W, and an etching rate of 1 nm/s.
Preferably, the wet etching in step (6) uses a BOE solution.
Preferably, the gate root region in step (5) has a length of 200 nm.
Preferably, the lower gate cap region in step (6) has a length of 400 nm.
Preferably, the top gate cap region in step (7) has a length of 600 nm.
Preferably, the gate metal electrode in step (7) is composed of two metals: Ni and Au.
Preferably, the gate/source/drain metal electrode in step (9) is composed of two metals: Ni and Au.
The transfer characteristic curve and the output characteristic curve of the double-T-shaped gate AlGaN/GaN HEMT prepared in this embodiment are similar to those in Embodiment 1, indicating that the device prepared according to this embodiment has stable performance.
The above embodiments are preferred implementations of the present disclosure, but the implementations of the present disclosure are not limited to these embodiments. Any other changes, modifications, substitutions, combinations, and simplifications made without departing from the spirit and principle of the present disclosure shall be equivalent replacement means and shall be included in the protection scope of the present disclosure.
| Number | Date | Country | Kind |
|---|---|---|---|
| 202110871188.7 | Jul 2021 | CN | national |
| Filing Document | Filing Date | Country | Kind |
|---|---|---|---|
| PCT/CN2022/108634 | 7/28/2022 | WO |
