Patent Application
20200051812
The present invention generally relates to fabrication methods and resulting structures for semiconductor devices. More specifically, the present invention relates to a method of addressing delamination between a silicon substrate and a dielectric in FinFET devices.
CMOS technology is used to construct integrated circuits such as microprocessors, microcontrollers, static random access memory (RAM) and other digital logic circuits. A basic component of CMOS designs is metal oxide semiconductor field effect transistors (MOSFETs).
A FinFET is a type of MOSFET. The FinFET is a double-gate or multiple-gate MOSFET device that mitigates the effects of short channels and reduces drain-induced barrier lowering. The term “fin” refers to the narrow channel between source and drain regions. Fins are typically formed from the silicon substrate on which the MOSFET is formed.
FinFET devices are fabricated by forming a set of fins on a substrate. Depending on device design, the number of fins varies from an array of multiple fins to an “isolated” single fin devices. The fins/devices are separated by shallow trench isolation (STI) recesses in the substrate (or STI regions), which are filled with a dielectric oxide.
One embodiment of the present invention is directed to a method for fabricating a semiconductor device is disclosed. The method of this embodiment includes: forming a plurality of fins from a substrate, the fins including nFET fins and pFET fins; forming a trench between the nFET fins and pFET fins; forming a silicon nitride (SiN) layer over the trench, the nFET fins and the pFET fins to create an intermediate device; and depositing with a high density plasma (HDP) process an HDP layer of silicon dioxide (SiO2) over the trench, the nFET fins and the pFET fins. The HDP process includes loading the intermediate device into a deposition chamber and introducing hydrogen (H2) gas and silane (SiH4) into the deposition chamber, wherein the H2 gas is not introduced into the deposition chamber before the SiH4 is introduced into the deposition chamber.
In another embodiment, a fabricating a semiconductor device includes: forming a plurality of fins from a substrate, the fins including nFET fins and pFET fins separated from one another; forming a silicon nitride (SiN) layer over the nFET fins and the pFET fins; forming a liner layer of SiO2 over the SiN layer with a non-HDP process to create an intermediate device; and depositing with a HDP process a HDP layer of SiO2 over the SiN layer. The HDP process includes loading the intermediate device into a deposition chamber and introducing hydrogen (H2) gas and silane (SiH4) into the deposition chamber, wherein the H gas is not introduced into the deposition chamber before the SiH4 is introduced into the deposition chamber.
In another embodiment, a method of fabricating a semiconductor device includes forming a plurality of fins from a substrate, the fins including nFET fins and pFET fins; forming a trench between the nFET fins and pFET fins, the trench including one or more fins; forming a silicon nitride (SiN) layer over the trench, the nFET fins and the pFET fins; forming a liner layer of SiO2 over the SiN layer with a non-high density plasma (HDP) process to create an intermediate device; and depositing with a high density plasma (HDP) process a HDP layer of silicon dioxide (SiO2) over the trench, the nFET fins and the pFET fins. The HDP process includes loading the intermediate device into a deposition chamber and introducing hydrogen (H2) gas and silane (SiH4) into the deposition chamber, wherein the H2 gas is not introduced into the deposition chamber before the SiH4 is introduced into the deposition chamber.
Additional technical features and benefits are realized through the techniques of the present invention. Embodiments and aspects of the invention are described in detail herein and are considered a part of the claimed subject matter. For a better understanding, refer to the detailed description and to the drawings.
The specifics of the exclusive rights described herein are particularly pointed out and distinctly claimed in the claims at the conclusion of the specification. The foregoing and other features and advantages of the embodiments of the invention are apparent from the following detailed description taken in conjunction with the accompanying drawings in which:
The diagrams depicted herein are illustrative. There can be many variations to the diagram or the operations described therein without departing from the spirit of the invention. For instance, the actions can be performed in a differing order or actions can be added, deleted or modified. Also, the term “coupled” and variations thereof describes having a communications path between two elements and does not imply a direct connection between the elements with no intervening elements/connections between them. All of these variations are considered a part of the specification.
In the accompanying figures and following detailed description of the described embodiments, the various elements illustrated in the figures are provided with two or three digit reference numbers. With minor exceptions, the leftmost digit(s) of each reference number correspond to the figure in which its element is first illustrated.
For the sake of brevity, conventional techniques related to semiconductor device and integrated circuit (IC) fabrication may or may not be described in detail herein. Moreover, the various tasks and process steps described herein can be incorporated into a more comprehensive procedure or process having additional steps or functionality not described in detail herein. In particular, various steps in the manufacture of semiconductor devices and semiconductor-based ICs are well known and so, in the interest of brevity, many conventional steps will only be mentioned briefly herein or will be omitted entirely without providing the well-known process details.
The phrase “semiconductor device” and variations thereof, are used in this detailed description to include any completed device or workpiece created during the formation of a completed device that can exploit the electronic properties of semiconductor materials. Example semiconductor devices include but are not limited to transistors and diodes.
Turning now to an overview of technologies that are more specifically relevant to aspects of the invention, High Density Plasma (HDP) silicon oxide (SiO2) is a dense, stable oxide desirable for STI fill, gap-fill, and other applications. In the case of FinFET devices, it is known that a thin liner is typically needed between a silicon substrate and the HDP SiO2 to prevent oxidation of the fin during deposition of the HDP SiO2. One type of liner that is typically used is formed of silicon nitride (SiN).
It has been discovered, however, that in the STI region or other large silicon surfaces, compressive stress from HDP SiO2, together with large amount of hydrogen and plasma damage on SiN during initial HDP deposition result in severe delamination in Si/SiN/HDP-SiO2 stack or Si/SiO2/SiN/HDP-SiO2 stack, often at Si/SiN interface (for Si/SiN/HDP-SiO2 stack) or at SiO2/SiN interface (for Si/SiO2/SiN/HDP-SiO2 stack).
Disclosed herein are two different approaches to reducing delamination. The two approaches can be used separately or in combination. The first manner in which delamination at Si/SiN can be overcome is by adding a protective thin, conformal, low direct-plasma based SiO2 layer on top of the SiN liner layer by using a process such as atomic layer deposition (ALD). In this approach, an optional rapid thermal annealing process may be performed and then the HDP SiO2 deposition is performed.
In the second approach, regardless of whether the ALD SiO2 is provided, the process hydrogen in deposition chamber is reduced/eliminated during the temperature ramp prior to the HDP SiO2 deposition. This can be accomplished, in one embodiment, by ensuring that little or no hydrogen is provided during the HDP SiO2 deposition prior to introduction of silane (SiH4) into the deposition chamber.
Further, in combination with one or both of the above approaches, dummy fins can be introduced into the STI region.
The substrate 102 can be of any suitable substrate material such as, for example, monocrystalline Si, SiGe, SiC, or semiconductor-on-insulator (SOI). In some embodiments, a top layer of the substrate 102 can be Si, SiGe, Group III-V channel material, or other suitable channel materials. Group III-V channel materials include materials having at least one group III element and at least one group V element, such as, for example, one or more of aluminum gallium arsenide, aluminum gallium nitride, aluminum arsenide, aluminum indium arsenide, aluminum nitride, gallium antimonide, gallium aluminum antimonide, gallium arsenide, gallium arsenide antimonide, gallium nitride, indium antimonide, indium arsenide, indium gallium arsenide, indium gallium arsenide phosphide, indium gallium nitride, indium nitride, indium phosphide and alloy combinations including at least one of the foregoing materials.
In some embodiments, a hardmask layer is deposited on top of the substrate 102 and patterned such that discrete hardmasks 104 remain. The hardmasks can be of any suitable material, such as silicon nitride SiN and can be referred to herein as a fin hardmask from time to time. In more detail, the fins are formed by forming fin hardmasks 104 on top of a substrate 102 and then performing a reactive ion etching process on the substrate to remove portions of the substrate not covered by the fin hardmask layer 104. Because there is no stop layer on or in the substrate 102, the reactive ion etch process is time based.
As illustrated, the hardmasks 104 are labelled as 104n and 104p. This is to denote that the device 100 can, when completed, form a CMOS FinFET device having an nMOS (with fins 104n) and a pMOS (with fins 104p). It will be understood, however, that the teachings herein are not limited to such an application and can be utilized in any situation where HDP SiO2 is formed on SiN.
The center of each fin 206n, 206p is separated from the center of it nearest neighbor by a distance p or “fin pitch”. Of course the distance p could be measured from one left edge of a fin to the left edge of its adjacent neighbor in some embodiments. For a particular fin pitch, a distance “d” exists between each adjacent fin. This space between adjacent fins in particular, fin group 210, 212 can be referred to as a gap.
As illustrated, the nFET fin group 110 is separated from the pFET fin group 112 by an isolation distance disolation.
As shown in
As discussed above, in one embodiment, before the HDP SiO2 deposition is performed, and a shown in
As shown in
In general, HDP SiO2 deposition typically includes the following steps:
1) Load the device 100 into a deposition chamber;
2) Flow Argon gas and start the plasma source;
3) Heat up device 100 in the chamber;
4) Introduce hydrogen gas and stabilize the temperature and the plasma;
5) Introduce SiH4 and oxygen gases, increase plasma power, start SiO2 deposition;
6) Stop film deposition by stopping SiH4 and hydrogen gas flow, reduce plasma power;
7) Cool down device; and
8) Unload device from the deposition chamber.
The addition of the SiO2 liner layer 502 before this HDP SiO2 process has been shown to reduce delamination between the SiN layer 402 and the silicon substrate that is at least partly due to the performance of the HDP SiO2 process. One possible reason is that the SiO2 liner layer 502 may reduce plasma damage to the SiN layer 402, which may weaken the interface process as the HDP plasma ambient provides ionized species that attack the nitride due to ion bombardment, and highly reactive species such as ionized H can penetrate the nitride layer.
According to one embodiment, the HDP process can be changed. The alternative process can the following steps:
1) Load the device 100 into a deposition chamber;
2) Flow Argon gas and start the plasma source;
3) Heat up device 100 in the chamber;
4) Stabilize the temperature and the plasma. This step can happen without hydrogen flow;
5) Introduce SiH4 and hydrogen and oxygen gases, increase plasma power, start SiO2 deposition;
6) Stop film deposition by stopping SiH4 and hydrogen gas flow, reduce plasma power;
7) Cool down wafer; and
8) Unload device from the deposition chamber.
From the above, it is clear that the newly described process can be performed in such a manner that hydrogen gas is not introduced into the deposition chamber until the same time or after the introduction of SiH4 into the chamber during the HDP plasma SiO2 deposition.
In an alternative embodiment to that described in relation to
As shown in
As shown in
Of course, any of the devices formed in
Various embodiments of the present invention are described herein with reference to the related drawings. Alternative embodiments can be devised without departing from the scope of this invention. Although various connections and positional relationships (e.g., over, below, adjacent, etc.) are set forth between elements in the following description and in the drawings, persons skilled in the art will recognize that many of the positional relationships described herein are orientation-independent when the described functionality is maintained even though the orientation is changed. These connections and/or positional relationships, unless specified otherwise, can be direct or indirect, and the present invention is not intended to be limiting in this respect. Accordingly, a coupling of entities can refer to either a direct or an indirect coupling, and a positional relationship between entities can be a direct or indirect positional relationship. As an example of an indirect positional relationship, references in the present description to forming layer “A” over layer “B” include situations in which one or more intermediate layers (e.g., layer “C”) is between layer “A” and layer “B” as long as the relevant characteristics and functionalities of layer “A” and layer “B” are not substantially changed by the intermediate layer(s).
The following definitions and abbreviations are to be used for the interpretation of the claims and the specification. As used herein, the terms “comprises,” “comprising,” “includes,” “including,” “has,” “having,” “contains” or “containing,” or any other variation thereof, are intended to cover a non-exclusive inclusion. For example, a composition, a mixture, process, method, article, or apparatus that comprises a list of elements is not necessarily limited to only those elements but can include other elements not expressly listed or inherent to such composition, mixture, process, method, article, or apparatus.
Additionally, the term “exemplary” is used herein to mean “serving as an example, instance or illustration.” Any embodiment or design described herein as “exemplary” is not necessarily to be construed as preferred or advantageous over other embodiments or designs. The terms “at least one” and “one or more” are understood to include any integer number greater than or equal to one, i.e. one, two, three, four, etc. The terms “a plurality” are understood to include any integer number greater than or equal to two, i.e. two, three, four, five, etc. The term “connection” can include an indirect “connection” and a direct “connection.”
References in the specification to “one embodiment,” “an embodiment,” “an example embodiment,” etc., indicate that the embodiment described can include a particular feature, structure, or characteristic, but every embodiment may or may not include the particular feature, structure, or characteristic. Moreover, such phrases are not necessarily referring to the same embodiment. Further, when a particular feature, structure, or characteristic is described in connection with an embodiment, it is submitted that it is within the knowledge of one skilled in the art to affect such feature, structure, or characteristic in connection with other embodiments whether or not explicitly described.
For purposes of the description hereinafter, the terms “upper,” “lower,” “right,” “left,” “vertical,” “horizontal,” “top,” “bottom,” and derivatives thereof shall relate to the described structures and methods, as oriented in the drawing figures. The terms “overlying,” “atop,” “on top,” “positioned on” or “positioned atop” mean that a first element, such as a first structure, is present on a second element, such as a second structure, wherein intervening elements such as an interface structure can be present between the first element and the second element. The term “direct contact” means that a first element, such as a first structure, and a second element, such as a second structure, are connected without any intermediary conducting, insulating or semiconductor layers at the interface of the two elements.
Spatially relative terms, e.g., “beneath,” “below,” “lower,” “above,” “upper,” and the like, can be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as “below” or “beneath” other elements or features would then be oriented “above” the other elements or features. Thus, the term “below” can encompass both an orientation of above and below. The device can be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.
The phrase “selective to,” such as, for example, “a first element selective to a second element,” means that the first element can be etched and the second element can act as an etch stop.
The terms “about,” “substantially,” “approximately,” and variations thereof, are intended to include the degree of error associated with measurement of the particular quantity based upon the equipment available at the time of filing the application.
The term “conformal” (e.g., a conformal layer) means that the thickness of the layer is substantially the same on all surfaces, or that the thickness variation is less than 15% of the nominal thickness of the layer.
The terms “epitaxial growth and/or deposition” and “epitaxially formed and/or grown” mean the growth of a semiconductor material (crystalline material) on a deposition surface of another semiconductor material (crystalline material), in which the semiconductor material being grown (crystalline overlayer) has substantially the same crystalline characteristics as the semiconductor material of the deposition surface (seed material). In an epitaxial deposition process, the chemical reactants provided by the source gases can be controlled and the system parameters can be set so that the depositing atoms arrive at the deposition surface of the semiconductor substrate with sufficient energy to move about on the surface such that the depositing atoms orient themselves to the crystal arrangement of the atoms of the deposition surface. An epitaxially grown semiconductor material can have substantially the same crystalline characteristics as the deposition surface on which the epitaxially grown material is formed. For example, an epitaxially grown semiconductor material deposited on a {100} orientated crystalline surface can take on a {100} orientation. In some embodiments of the invention, epitaxial growth and/or deposition processes can be selective to forming on semiconductor surface, and cannot deposit material on exposed surfaces, such as silicon dioxide or silicon nitride surfaces.
As previously noted herein, for the sake of brevity, conventional techniques related to semiconductor device and integrated circuit (IC) fabrication may or may not be described in detail herein. By way of background, however, a more general description of the semiconductor device fabrication processes that can be utilized in implementing one or more embodiments of the present invention will now be provided. Although specific fabrication operations used in implementing one or more embodiments of the present invention can be individually known, the described combination of operations and/or resulting structures of the present invention are unique. Thus, the unique combination of the operations described in connection with the fabrication of a semiconductor device according to the present invention utilize a variety of individually known physical and chemical processes performed on a semiconductor (e.g., silicon) substrate, some of which are described in the immediately following paragraphs.
In general, the various processes used to form a micro-chip that will be packaged into an IC fall into four general categories, namely, film deposition, removal/etching, semiconductor doping and patterning/lithography. Deposition is any process that grows, coats, or otherwise transfers a material onto the wafer. Available technologies include physical vapor deposition (PVD), chemical vapor deposition (CVD), electrochemical deposition (ECD), molecular beam epitaxy (MBE) and more recently, atomic layer deposition (ALD) among others. Removal/etching is any process that removes material from the wafer. Examples include etch processes (either wet or dry), and chemical-mechanical planarization (CMP), and the like. Semiconductor doping is the modification of electrical properties by doping, for example, transistor sources and drains, generally by diffusion and/or by ion implantation. These doping processes are followed by furnace annealing or by rapid thermal annealing (RTA). Annealing serves to activate the implanted dopants. Films of both conductors (e.g., poly-silicon, aluminum, copper, etc.) and insulators (e.g., various forms of silicon dioxide, silicon nitride, etc.) are used to connect and isolate transistors and their components. Selective doping of various regions of the semiconductor substrate allows the conductivity of the substrate to be changed with the application of voltage. By creating structures of these various components, millions of transistors can be built and wired together to form the complex circuitry of a modern microelectronic device. Semiconductor lithography is the formation of three-dimensional relief images or patterns on the semiconductor substrate for subsequent transfer of the pattern to the substrate. In semiconductor lithography, the patterns are formed by a light sensitive polymer called a photo-resist. To build the complex structures that make up a transistor and the many wires that connect the millions of transistors of a circuit, lithography and etch pattern transfer steps are repeated multiple times. Each pattern being printed on the wafer is aligned to the previously formed patterns and slowly the conductors, insulators and selectively doped regions are built up to form the final device.
The flowchart and block diagrams in the Figures illustrate possible implementations of fabrication and/or operation methods according to various embodiments of the present invention. Various functions/operations of the method are represented in the flow diagram by blocks. In some alternative implementations, the functions noted in the blocks can occur out of the order noted in the Figures. For example, two blocks shown in succession can, in fact, be executed substantially concurrently, or the blocks can sometimes be executed in the reverse order, depending upon the functionality involved.
The descriptions of the various embodiments of the present invention have been presented for purposes of illustration, but are not intended to be exhaustive or limited to the embodiments described. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The terminology used herein was chosen to best explain the principles of the embodiments, the practical application or technical improvement over technologies found in the marketplace, or to enable others of ordinary skill in the art to understand the embodiments described herein.
