PRINTED BOARD AND SEMICONDUCTOR INTEGRATED CIRCUIT

Abstract

An IC which includes a first circuit and a plurality of first paired terminals each including a first power supply terminal and a first GND terminal which are connected to the first circuit, and a second circuit and a plurality of second paired terminals each including a second power supply terminal and a second GND terminal which are connected to the second circuit. The first and second paired terminals are isolated inside. A printed board with the IC mounted has an inductor which is provided in a route that guides a wiring line from the first GND terminal to the second GND terminal and the GND of the printed board. The printed board has a portion where each of the first GND terminals is arranged inside the terminal array of the IC. The inductor suppresses a high-frequency potential variation generated by the operation of the first circuit.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

FIGS. 1A and 1B are views showing the internal arrangement of an IC according to a representative embodiment of the present invention;

FIG. 2 is a view showing radiant noise generation by the IC;

FIGS. 3A and 3B are views showing an IC mounted on a four-layered printed board and its connection state;

FIGS. 4A and 4B are views showing an IC mounted on a two-layered double-sided printed board and its connection state;

FIGS. 5A and 5B are views showing an IC mounted on a two-layered double-sided printed board or a single-layered single-sided printed board with a small GND pattern area and its connection state;

FIGS. 6A and 6B are views showing connection between an IC and a printed wiring board which suppresses radiant noise from the IC according to the first embodiment of the present invention;

FIGS. 7A and 7B are views schematically showing high-frequency current confinement according to the first embodiment of the present invention;

FIG. 8 is a view showing an example of pattern wiring when an IC 2 is mounted on a two-layered double-sided printed board;

FIG. 9 is a view showing the internal arrangement of an IC incorporating constituent elements to suppress radiant noise;

FIGS. 10A and 10B are views showing connection between an IC and a printed wiring board which suppresses radiant noise from the IC according to the second embodiment of the present invention;

FIGS. 11A to 11C are views schematically showing high-frequency current confinement according to the second embodiment of the present invention;

FIGS. 12A and 12B are views showing examples of a four-layered printed board with pattern wiring isolation according to the third embodiment of the present invention;

FIGS. 13A and 13B are views showing a noise propagation route on a printed board according to the fourth embodiment of the present invention;

FIGS. 14A and 14B are views showing examples of a four-layered printed board with pattern wiring isolation according to the fourth embodiment of the present invention;

FIGS. 15A and 15B are views showing an example of pattern wiring when an IC 2 is mounted on a printed board; and

FIGS. 16A and 16B are views showing an example of pattern wiring when an IC 2 is mounted on a printed board.

Claims

1. A printed board comprising: a first circuit;a plurality of first paired terminals, each of which includes a first power supply terminal and a first GND terminal which are connected to the first circuit;a second circuit;a second paired terminal including a second power supply terminal and a second GND terminal which are connected to the second circuit;an IC in which the first paired terminal and the second paired terminal are isolated; anda first suppressing unit adapted to suppress a high-frequency potential variation generated by an operation of the first circuit, said first suppressing unit being arranged in a route that guides a wiring line from the first GND terminal to the second GND terminal and a GND pattern of the printed board, wherein the first GND terminals of the plurality of first paired terminals are connected by a short-distance pattern near the IC.

2. The board according to claim 1, wherein the short-distance pattern has a portion arranged inside a terminal array of the IC.

3. The board according to claim 1, wherein said first suppressing unit comprises a ferrite bead.

4. The board according to claim 1, wherein an impedance of said first suppressing unit is low with respect to a DC current and high with respect to a high-frequency current.

5. The board according to claim 4, wherein a wiring pattern from the first GND terminal is arranged so as to be physically isolated from a wiring pattern from the second GND terminal, andthe wiring patterns arranged so as to be physically isolated form an inductor corresponding to said first suppressing unit.

6. The board according to claim 5, further comprising a plurality of first circuits and a plurality of second circuits, and wherein an impedance of a first wiring line that mutually connect the first paired terminals connected to the plurality of first circuits is lower than an impedance of a second wiring line that mutually connect the second paired terminals connected to the plurality of second circuits.

7. The board according to claim 1, wherein a predetermined power supply voltage is supplied to the first power supply terminal and the second power supply terminal.

8. The board according to claim 1, further comprising a first charge accumulation unit connected between the first power supply terminal and the first GND terminal.

9. The board according to claim 8, further comprising a second suppressing unit provided in a route that guides a wiring line from the first power supply terminal to a wiring line from the second power supply terminal and the power supply voltage pattern, anda second charge accumulation unit connected between the second power supply terminal and the second GND terminal.

10. The board according to claim 9, wherein said second suppressing unit comprises a ferrite bead.

11. The board according to claim 9, wherein each of said first suppressing unit and said second suppressing unit comprises a common-mode choke.

12. The board according to claim 9, wherein a wiring pattern from the first power supply terminal is arranged so as to be physically isolated from a wiring pattern from the second power supply terminal,a wiring pattern from the first GND terminal is arranged so as to be physically isolated from a wiring pattern from the second GND terminal, and the wiring patterns arranged so as to be physically isolated form an inductor corresponding to said first suppressing unit.

13. The board according to claim 12, wherein a predetermined power supply voltage is supplied from a power supply voltage supply unit to the first circuit,a wiring pattern from the first power supply terminal and a wiring pattern from the first GND terminal are arranged in parallel up to the power supply voltage supply unit, andthe wiring patterns arranged in parallel form an inductor corresponding to said first suppressing unit.

14. The board according to claim 13, wherein the power supply voltage supply unit comprises an external power supply voltage unit.

15. The board according to claim 1, wherein the IC comprises an ASIC,the first circuit comprises an internal core circuit of the ASIC, andthe second circuit comprises an I/O buffer circuit of the ASIC.

16. A semiconductor integrated circuit comprising: a first circuit;a first pair internal wiring line including a first power supply internal wiring line and a first GND internal wiring line which are connected to the first circuit;a second circuit;a second pair internal wiring line including a second power supply internal wiring line and a second GND internal wiring line which are connected to the second circuit, the first pair internal wiring line and the second pair internal wiring line being isolated; anda first internal suppressing unit adapted to suppress a high-frequency potential variation generated by an operation of the first circuit, said first internal suppressing unit being arranged in an internal route that guides the first GND internal wiring line to the second GND internal wiring line and an external connection GND terminal of the semiconductor integrated circuit; anda first internal charge accumulation unit connected between the first power supply internal wiring line and the first GND internal wiring line.

17. The circuit according to claim 16, further comprising a second internal suppressing unit provided in an internal route that guides the first power supply internal wiring line to the second power supply internal wiring line and an external connection power supply terminal of the semiconductor integrated circuit.

18. The circuit according to claim 17, further comprising a second internal charge accumulation unit connected between the second power supply internal wiring line and the second GND internal wiring line.

19. The circuit according to claim 16, wherein the semiconductor integrated circuit comprises an ASIC,the first circuit comprises an internal core circuit of the ASIC, andthe second circuit comprises an I/O buffer circuit of the ASIC.