This application claims the priority benefit of TW application serial No. 103139060, filed on Nov. 11, 2014. The entirety of the above-mentioned patent applications is hereby incorporated by reference herein and made a part of specification.
1. Field of the Invention
The disclosure relates to a circuit board structure and, more particularly, to a printed circuit board structure.
2. Description of the Related Art
With technology development, computing functions and information transmission efficiency of components of an electronic device are increased. For a large amount of information transmission, connectors having high speed data transmission efficiency are disposed in the electronic device.
Generally, a plurality of connecting pads are disposed on a printed circuit board to correspond to connection terminals of the connector subsequently disposed on the printed circuit board for electrically connecting to the connectors of the electronic device. The connectors of the electronic device are matched with the connectors disposed on the printed circuit board to transmit data. However, the entire thickness of the printed circuit board is increased to causes the size problem in the electronic device.
The printed circuit board structure includes a main body and a connecting interface connected to the main body and located at a side of the main body. The connecting interface includes a plurality of conductive layers and a plurality of insulation layers. The insulation layers and the conductive layers are alternately disposed. The conductive layers at least include a first conductive layer, a second conductive layer, a third conductive layer and a fourth conductive layer. The insulation layers at least include a first insulation layer, a second insulation layer and a third insulation layer. The first insulation layer is located between the first conductive layer and the second conductive layer. An orthographic projection of the first conductive layer on the first insulation layer is partially overlapped with an orthographic projection of the second conductive layer on the first insulation layer. The second insulation layer is located between the second conductive layer and the third conductive layer. The third insulation layer is located between the third conductive layer and the fourth conductive layer.
These and other features, aspects and advantages of the disclosure will become better understood with regard to the following embodiments and accompanying drawings.
Please refer to
Please refer to
In detail, in the embodiment, the thickness of the main body 110 and the thickness of the connecting interface 120 are the same, and the main body 110 is connected to the connecting interface 120 seamlessly, or they are integrated formed. Preferably, in the embodiment, the thickness of the connecting interface 120 is between 0.8 mm and 1.6 mm, and the thickness of the main body 110 is also between 0.8 mm and 1.6 mm correspondingly. In the embodiment, the connecting interface 120 is such as a serial advanced technology attachment (SATA) express interface portion, the first conductive layer 122a is formed by seven high speed signal terminals S1 and fifteen power supply terminals P1, and the fourth conductive layer 122d is formed by three signal terminals E1 and seven high speed signal terminals S2. The high speed signal terminal S1, S2 is the signal terminals whose transmission speed is above 1 Gbps, and the transmission speed of the signal terminal E1 is below 1 Gbps.
Further, as shown in
Additionally, in the embodiment, the orthographic projection of the second conductive layer 122b on the second insulation layer 124b is overlapped with the orthographic projection of the third conductive layer 122c on the second insulation layer 124b. The second conductive layer 122b is such as a ground plane, or a power plane, or a ground plane and a power plane, and the third conductive layer 122c is such as a ground plane, or a power plane, or a ground plane and a power plane. In detail, the second conductive layer 122b is used to decrease an induction area of the first conductive layer 122a, so as to increase the resistance and the characteristic impedance, and then to achieve the impedance matching. Similarly, the third conductive layer 122c is also used to decrease an induction area of the fourth conductive layer 122d, so as to increase the resistance and the characteristic impedance, and then to achieve the impedance matching.
The number of layers of the conductive layers 122 and the number of the insulation layers 124 of the connecting interface 120 is not limited to above embodiments. Although in the above embodiments, the conductive layers 122 includes four layers, the insulation layers 124 includes three layers, in another embodiments not shown, the conductive layers 122 includes an even number of layers, such as six layers, eight layers, ten layers, and the insulation layers 124 includes an odd number of layers, such as five layers, seven layers, nine layers. In an embodiment, only if the thickness of the connecting interface 120 is between 0.8 mm and 1.6 mm, the number of layers is not limited herein.
Since the printed circuit board structure includes the main body and the connecting interface, and the orthographic projection of the first conductive layer of the connecting interface on the first insulation layer is partially overlapped with the orthographic projection of the second conductive layer on the first insulation layer, the printed circuit board structure both include a function of the connector (coupled to the external electronic components) and a function of the circuit board (signal transmission). Furthermore, the printed circuit board structure is small and thin, the preferable impedance matching is achieved, and the impedance discontinuity is avoided.
Number | Date | Country | Kind |
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103139060 | Nov 2014 | TW | national |