Patent Application
20080135282
The present invention relates generally to electronic circuit substrates, and more particularly to printed electronic circuits having printed active devices and printed three dimensional interconnects and methods of manufacturing the circuits and devices using high speed roll-to-roll or sheet-fed printing processes.
Conventional fabrication methods for manufacturing printed circuits have always utilized one or more methods of creating a conductive metal pattern on a dielectric substrate. Some of the various methods include print and etch, electroless copper deposition, vacuum deposition, and screen printing, contact printing, or ink jetting a liquid slurry of metal onto the substrate. Some of these methods are subtractive, such as the print and etch where patterns are etched from a laminated copper foil, others are purely additive, such as the printing or ink jetting methods where conductor patterns are directly formed on the substrate, and still others are combinations of additive and subtractive. In addition to forming conductor patterns for the electrical circuitry, many have also sought to create passive devices, such as resistors and capacitors, on the substrate. Resistors and capacitors have long been utilized with success in circuits with ceramic substrates, and some have even modified this technology to incorporate it into circuitry on rigid glass reinforced polymer substrates. Adoption of passive and active devices on high volume, low cost, flexible film substrates has been less successful.
Fabrication of printed electronic circuitry and devices using high speed graphic arts printing technology has the potential to produce very inexpensive circuits in very high volumes e.g. gravure, flexography. However, the lack of a simple and cost effective means to route electrical signals from one layer to another has hindered the widespread use of this technology. Currently, designers are restricted to a few cost-prohibitive options of forming a layer X to layer Y connection, such as mechanical and laser drilling, sequential lamination, and build up. Mechanically drilled vias can penetrate the entire printed multilayer electronic circuit, but they occupy space on every layer. Laser drilled blind microvias can be employed to reduce the size and cost of the printed multilayer electronic circuit, and compared to mechanical drilling, laser drilling allows much smaller vias, but they can only connect the outermost layer to the next inner layer. Furthermore, many of above processes have been developed for the traditional printed wiring board industry, are relatively slow, and are usually not compatible with high speed printing processes that can have throughput speeds of up to 2000 ft/min or 7000 sheets/hr. It is therefore highly desirable to find a means of creating high density printed multilayer circuits on flexible substrates that can interconnect circuit elements on differing levels using high speed graphic arts technology.
The accompanying figures, where like reference numerals refer to identical or functionally similar elements throughout the separate views and which together with the detailed description below are incorporated in and form part of the specification, serve to further illustrate various embodiments and to explain various principles and advantages all in accordance with the present invention.
Skilled artisans will appreciate that elements in the figures are illustrated for simplicity and clarity and have not necessarily been drawn to scale. For example, the dimensions of some of the elements in the figures may be exaggerated relative to other elements to help to improve understanding of embodiments of the present invention.
Before describing in detail embodiments that are in accordance with the present invention, it should be observed that the embodiments reside primarily in combinations of method and apparatus components related to multilayer printed electronic circuits using high speed roll-to-roll or sheet-fed printing processes. Accordingly, the apparatus components and methods have been represented where appropriate by conventional symbols in the drawings, showing only those specific details that are pertinent to understanding the embodiments of the present invention so as not to obscure the disclosure with details that will be readily apparent to those of ordinary skill in the art having the benefit of the description herein.
In this document, relational terms such as first and second, top and bottom, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. The terms “comprises,” “comprising,” or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. An element proceeded by “comprises . . . a” does not, without more constraints, preclude the existence of additional identical elements in the process, method, article, or apparatus that comprises the element.
It will be appreciated that embodiments of the invention described herein may be comprised of one or more conventional processes and/or elements for manufacturing a multilayer printed electronic circuit. Of course, a combination of the two approaches could be used. Thus, methods and means for these functions have been described herein. Further, it is expected that one of ordinary skill, notwithstanding possibly significant effort and many design choices motivated by, for example, available time, current technology, and economic considerations, when guided by the concepts and principles disclosed herein will be readily capable of generating such multilayer printed electronic circuits with minimal experimentation.
A printed multilayer electronic circuit comprises a number of printed electronic components on a first level circuit. One or more electrical conductors are printed on this first level circuit such that the conductors are electrically connected to at least some of the electronic components. A layer of dielectric material is then printed over the printed electrical conductors, and, optionally, over the electronic components. The dielectric layer is formed such that it contains apertures that extend vertically through the dielectric layer down to the electrical conductors. A second set of electrical conductors are then printed on the dielectric layer, such that at least some of these second electrical conductors are situated around some of the apertures. Electrically conductive material is then printed in these apertures so that an electrical connection is made from the second set of electrical conductors to the electrical conductors on the lower level. A second level circuit comprising additional electronic components are then formed on the dielectric layer and the second set of conductors, such that these electronic components are electrically connected to at least some of the electronic components on the first level circuit through the path of the printed second set of electrical conductors, the printed electrically conductive material, and the printed electrical conductors on the lower level.
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Having described one embodiment of the structure of our invention, we now turn to a description of the process used to create this structure. Referring now to
In summary, a printed multilayer electronic circuit that forms a three dimensional interconnect between two levels of circuitry can be created using high speed printing techniques such as flexography, lithography, gravure, screen, or pad printing. A series of electrical conductors are printed, then a layer of dielectric material is printed over these electrical conductors. The dielectric layer contains apertures openings that extend vertically through the dielectric layer down to the electrical conductors. A second set of electrical conductors are then printed on the dielectric layer, and electrically conductive material is printed in the apertures so that an electrical connection is made from the second set of electrical conductors to the electrical conductors on the lower level. The printing head contains cavities that vary in volume as a function of the amount of electrically conductive material to be filled in the apertures. In one embodiment, the substrate that supports the first level circuit is a temporary substrate, and is releasable from the built up multilayer structure. Those familiar with the art will appreciate that the invention could be applied to more than 2 layers. Multi-layer structures consisting of 3, 4 or more layers can be constructed by applying the process described in the invention. As the number of layers increases, the depth of the apertures can vary significantly, and the cavities in the printing head can be designed to accommodate variations in volume of ink required.
In the foregoing specification, specific embodiments of the present invention have been described. However, one of ordinary skill in the art appreciates that various modifications and changes can be made without departing from the scope of the present invention as set forth in the claims below. Accordingly, the specification and figures are to be regarded in an illustrative rather than a restrictive sense, and all such modifications are intended to be included within the scope of present invention. The benefits, advantages, solutions to problems, and any element(s) that may cause any benefit, advantage, or solution to occur or become more pronounced are not to be construed as a critical, required, or essential features or elements of any or all the claims. The invention is defined solely by the appended claims including any amendments made during the pendency of this application and all equivalents of those claims as issued.
