Patent Application
20080040920
The following detailed description of the invention is merely exemplary in nature and is not intended to limit the invention or the application and uses of the invention. Furthermore, there is no intention to be bound by any theory presented in the preceding background of the invention or the following detailed description of the invention.
Turning now to
In the depicted embodiment, the vias 104 are formed through the substrate 102, and thus extend between the substrate first and second sides 112, 114. It will be appreciated, however, that in alternative embodiments, one or more of the vias 104 may be formed only partially through the substrate 102. For example, in embodiments in which the substrate 102 is implemented using a multi-laminate substrate, one or more of the vias 104 may extend through only one or more of the laminates that comprise the substrate 102.
The conductive traces 106, as is generally known, are used to electrically interconnect non-illustrated components that may be mounted on the substrate 102, to electrically interconnect the interstitial resistors 108 to one or more of the non-illustrated components and/or other interstitial resistors, and to electrically interconnect the substrate 102 to one or more external circuits and/or devices. The conductive traces 108 are preferably formed of a relatively low resistance conductive material, such as copper. It will be appreciated, however, that various other conductive materials may also be used.
The interstitial resistors 108 are disposed in at least selected ones of the plurality of vias 104, and are formed of an electrically resistive material or compound. The interstitial resistors 108 each have an electrical resistance value, and its particular resistance value depends on various factors. For example, the electrical resistance value of each interstitial resistor 108 may vary with the type of resistive compound that is used, with the length of the resistor 108, and with the cross sectional area of the resistor 108. In particular, various known resistive compounds have differing values of resistivity. For example, known carbon-based resistive inks are available in different mixtures that provide different ranges of resistance. Moreover, for a given resistive compound, it is generally known that the resistance of an interstitial resistor 108 is proportional to its length, and inversely proportional to its cross sectional area.
In addition to the above, it is noted that resistance values of at least two of the interstitial resistors 108 depicted in
As shown in
After the vias 212 are formed, and depending on the process and/or device that is used to form the vias 212, one or more post-formation processes could be conducted. For example, the via 212 formation process could result in burrs being formed on the foil layers 204, and dust adhering to the foil layers 204 and/or walls of the vias 212. If so, a deburring and/or dust removal process may be conducted. In addition, if the vias 212 are formed using a drill, heat generated during the drilling process may cause some localized melting of the substrate 202 and form a so-called smear on walls of the vias 212. Thus, a de-smear process may also be conducted to remove the smear.
Whether or not one or more of the above-described post-via-formation processes (or additional processes) is conducted, at least selected ones of the vias 212 are then filled with a resistive compound. Not all of the vias 212 on the substrate 202 may be filled with a resistive compound, and those vias 212 that are filled with a resistive compound are not filled simultaneously. Rather, those vias 212 that are being used to implement interstitial resistors having equal, or at least substantially equal, resistance values are preferably filled simultaneously, while the remaining vias 212 are prevented from being filled. To accomplish this, a multi-stage masking process, which will now be described in more detail, is implemented. Before describing the process, it is noted that, once again for clarity and ease of depiction and description, in the depicted embodiment the first via 212-1 is being used to implement a first interstitial resistor having a first resistance value, the second via 212-2 is being used to implement a second interstitial resistor having a second resistance value that differs from the first, the third via 212-3 is being used to implement a third interstitial resistor having a third resistance value that differs from the first and second, and the fourth via 212-4 is not being used to implement an interstitial resistor.
Turning now to
Before proceeding further, it is noted that although only one via 212 is used to implement an interstitial resistor 108-1 having the first resistance value, if two or more vias 212 were being used to implement interstitial resistors 108-1 having the first resistance value, then the first mask 302 would be configured such that two or more vias 212 were exposed and could be filled with the resistive compound 402. Moreover, if one or more other vias 212 that are to be used to implement interstitial resistors have diameters that differ from the first via 212-1 and, if filling these larger diameter vias 212 with the resistive compound 402 would result in these larger diameter vias 212 implementing interstitial resistors 108 of desired resistance values, the first mask 302 could additionally be configured such that these larger diameter vias 212 would remain exposed.
Returning now to the description, and with reference now to
Thereafter, and as
After all of the interstitial resistors 108 have been appropriately formed, the associated vias 212 are cap-plated with an appropriate plating material. It will be appreciated that the plating material may be any one of numerous types of suitable conductive materials, non-limiting examples of which include copper, tin, various copper-tin alloys, various nickel alloys, and various silver alloys, and gold. In some embodiments it may be desirable to cap-plate one or more other vias 212 in addition to those associated with the interstitial resistors 108. Preferably, and as shown in
After the vias 212 have been cap-plated and the masks 702 removed from the substrate 202, circuit traces are then formed in one or both (preferably both) conductive foil layers 204. The circuit traces may be formed using any one of numerous known processes. Such processes include, for example, the use of photoresist masks and etchant, as is generally known in the art. It is noted that before the circuit traces are formed, a planarization process is preferably performed to provide smooth, even surfaces, which in turn provides for uniform etching to form the traces. After the circuit traces are formed, the circuit traces and cap-plated vias 212 may additionally be plated with a non-illustrated protective plating material, such as immersion gold or other non-corrosive metal.
It will be appreciated that the process described above can be used in the manufacture of a multi-laminate PWB 900, such as the one depicted in
While the invention has been described with reference to a preferred embodiment, it will be understood by those skilled in the art that various changes may be made and equivalents may be substituted for elements thereof without departing from the scope of the invention. In addition, many modifications may be made to adapt to a particular situation or material to the teachings of the invention without departing from the essential scope thereof. Therefore, it is intended that the invention not be limited to the particular embodiment disclosed as the best mode contemplated for carrying out this invention, but that the invention will include all embodiments falling within the scope of the appended claims.
