Claims
- 1. Process for obtaining a high-voltage N-channel transistor, particularly for an EEPROM memory with CMOS technology, comprising in succession the steps of:
- a) N.sup.- doping at least a first portion of a P-type semiconductor substrate surface which has been covered with an oxide layer,
- b) oxidizing the doped first portion of the substrate surface to form a gate oxide layer which is thicker than gate oxide layer thicknesses on any other portion of the substrate surface as a result of the N.sup.- doping,
- c) deposite and definition of an N.sup.+ doped polysilicon layer on a part of said doped first portion and on an adjacent portion of the substrate surface to form a gate strip,
- d) oxidizing the gate strip,
- e) N.sup.+ doping the remaining part of said doped first portion of the substrate surface which does not have the N.sup.+ doped polysilicon layer deposited and defined thereon, and simultaneously N.sup.+ doping another portion of the substrate surface at a side of the gate strip opposite to that of said doped first portion to form drain and source areas.
- 2. Process in accordance with claim 1 characterized in that said first portion comprises a first drain portion for an EEPROM cell selection transistor and a second drain portion for a high-voltage external circuitry transistor for an EEPROM memory and said additional portion comprises a first source portion for said selection transistor and a second source portion for said circuitry transistor.
- 3. Process in accordance with claim 2 characterized in that said N.sup.- doping is also performed on said second source portion, part of which receives said polysilicon layer and the remaining part being subjected to said N.sup.+ doping.
Priority Claims (1)
Number |
Date |
Country |
Kind |
19580 A/88 |
Feb 1988 |
ITX |
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Parent Case Info
This application is a continuation of Ser. No. 07/309,889, filed 2/14/89 now abandoned.
US Referenced Citations (11)
Foreign Referenced Citations (2)
Number |
Date |
Country |
0064069 |
Apr 1983 |
JPX |
0025458 |
Feb 1987 |
JPX |
Non-Patent Literature Citations (2)
Entry |
Ho et al., "Si/S102 Interface Oxidation Kinetics: A Physical Model for the Influence of High Substrate Doping Levels", J. of Electrochemical Society, Sep. 1979, pp. 1516-1530. |
Deal et al., "Thermal Oxidation of Heavily Doped Silicon", J. Electrochemical Soc., Apr. 65, pp. 430-435. |
Continuations (1)
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Number |
Date |
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Parent |
309889 |
Feb 1989 |
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