Patent Application
20110120969
This application claims the priority benefit of Taiwan patent application number 098139518, filed on Nov. 20, 2009.
1. Field of the Invention
The present invention relates to a process of manufacturing a ceramic substrate; particularly the ceramic substrate comprises an etching resistance layer plated on the metallic layer and the conductive metallic layer of the wiring portion, thus the etching solution would not cause reduction of surface area to the width of the wire, accordingly, the precision of the wire size can be upgraded.
2. Description of the Related Art
Following fast development of technology and demand for the better quality of life, many products have been designed for meeting rigid requirements in their applicable features. The manufacturers have invested a considerable sum of budget into the research of the integrated circuit packaging process in order to provide products to perform better transmission efficiency in the miniaturized size (for applying in the products such as cellular phone, mini-notebook computer). After years of research, a ceramic-made substrate is created with advantageous characteristics such as excellent isolation effect, chemical stability, electromagnet, high hardness, and abrasion and thermal resistance, which makes ceramic substrate to obtain better performance than the conventional substrate, and that is the reason why the ceramic substrate is more popularly used nowadays.
Generally, the metallic layer and conductive layer are attached to the ceramics substrate by thermo-compression bonding process, then a dry membrane is attached onto the conductive layer for processing further exposure, developing and etching to form circuit on the metallic layer and the conductive layer as required. Due the difficulty of etching the metallic layer, the etchant may cause excessive removal of the conductive layer; the layout of the circuit has been predetermined on the dry membrane during the process of exposure and development, and excessive removal of the conductive layer may form stair case profile between the metallic layer and the conductive layer and accordingly reduce the width of the circuit. Therefore, how to solve the above described defect is the priority issue for the manufacturers in the field.
The present invention has been accomplished under the circumstances in view. It is therefore the main object of the present invention to provide a manufacturing process of a ceramic substrate to upgrade the precision of the product size.
The other aspect of the present invention includes after plating conductive metallic layer onto the metallic layer with the circuit, an etching resistance layer is then plated thereon. The etching resistance layer is used to protect the surface of the conductive metallic layer from etching the width of the circuit on the surface of the conductive metallic layer by the etchant solution. Thus, a determined width of the circuit after etching may be maintained, and the precession of the product size can be upgraded.
The metallic layer 12 has a dry membrane 2 attached on the surface for processing exposure and development in a photolithography process to remove the dry membrane 2 from the predetermined circuit, then the conductive metallic layer 13 is coated on the partial metallic layer 12 where predetermined circuit and exposed by the dry membrane 2. The material of the conductive metallic layer 13 may be copper, and the thickness of the conductive metallic layer 13 may be from 50 μm to 75 μm. An etching resistance layer 3 may be coated onto the conductive metallic layer 13, and the etching resistance layer 3 may be made of silver or gold or any other material with better etching resistance. The preferred material of forming the etching resistance layer 3 is gold, and the thickness of the etching resistance layer 3 is 0.01 μm to 0.1 μm. Furthermore, the dry membrane 2 is removed from the portion which is not predetermined for forming circuit, and etching of the metallic layer 12 is performed after the removal of the dry membrane 2. The circuit is formed after etching using, for example ferric chloride or copper chloride, to remove the metallic layer 12. The remaining etching resistance layer 3 can be removed from the conductive metallic layer 13 by using a removing agent, and then a coating process is performed on the anti oxidization welding layer 4 and coating on the welding resistance inking layer 5 to complete the process.
The method of coating the metallic layer 12 on the surface of the ceramics substrate 1 can be sputtering the titanium or the nanometer surfactant may be used to modify the surface of the ceramics substrate 1, then further coated with nickel, chromium, gold, silver or other metal. To coat the metallic layer 12 is the common knowledge in the field and not the key point of the present invention, therefore, more detailed description thereof is omitted.
Aluminum nitride (AlN) or aluminum oxide (Al2O3) may be used to form the soft embryo and one or more than one apertures 11 may be formed by using a laser after sintering, or one or more than one apertures 11 may be first formed on the soft embryo then to sintered, and the above description is not intended to limit the scope of the present invention; therefore, any illustrative or structural modification shall be construed to be within the scope of the present invention.
To apply the process of the ceramic substrate of the present invention, the conductive metallic layer 13 may be coated on the metallic layer 12 of the circuit, then the etching resistance layer 3 may be coated to prevent the etchant from directly contacting the surface of the conductive metallic layer 13, and the predetermined width of the circuit can be preserved and the precision of the size of the product can be upgraded.
The process of manufacturing the ceramic substrate in the present invention include orderly coating of the metallic layer 12 on the surface of the ceramics substrate 1 and attaching the dry membrane 2, and removing the dry membrane 2 after the exposure and development to form the circuit. Further, the conductive metallic layer 13, the etching resistance layer 3 may be sequentially coated onto the surface of the metallic layer 12 of the circuit, in order to prevent the reduction of the width of the circuit on the surface of the conductive metallic layer 13 while etching, and accordingly, the precision of the size of the circuit can be upgraded. Although a particular embodiment of the invention has been described in detail for purposes of illustration, various modifications and enhancements may be made without departing from the spirit and scope of the invention.
While the invention has been described in conjunction with a specific best mode, it is to be understood that many alternatives, modifications, and variations will be apparent to those skilled in the art in light of the foregoing description. Accordingly, it is intended to embrace all such alternatives, modifications, and variations in which fall within the spirit and scope of the included claims. All matters set forth herein or shown in the accompanying drawings are to be interpreted in an illustrative and non-limiting sense.
| Number | Date | Country | Kind |
|---|---|---|---|
| 098139518 | Nov 2009 | TW | national |
