This invention relates to the measurement of stitching offsets in etched interconnect layers, and more particularly, to structures, systems and methods employing proportional variable resistors suitable for electrically measuring unidirectional misalignment of stitched masks in etched interconnect layers.
One step in the production of a microdevice is photolithography in which contacts are patterned in a mask, on top of glass and the contacts are etched. After removal of the mask the patterned wafer is covered with a thin layer of aluminum. Applying lithography again, spaces between the aluminum lines are etched away, the mask is removed and a new layer is deposited. The glass layer is polished and the process is repeated until all layers of interconnect have been applied. The whole process hinges on the use of the photographic process to create the fine-featured patterns of the integrated circuit. A specific mask defines each layer of the chip and there are typically up to 24 mask layers in each IC.
As exposure areas have become increasingly large in keeping with the increased size of substrates, block exposure type stitching processes which partition the exposure area of the substrate into a plurality of unit areas (sometimes referred to as “shots” or “shot areas”) and successively project and expose images of corresponding patterns on the shots have been developed. Such stitching of masks can result in misalignments which must be avoided since defects in masks can cause short circuits, open circuits or other design rule violations, any of which can be fatal to the functionality of the chip.
Therefore inspection and measurement of stitched masks is essential. Currently, the only known method of inspection is visual inspection employing devices such as scanning electron microscopes to detect misalignments. As fine geometries become smaller the ability to observe defects visually becomes more expensive and difficult.
Accordingly a need exists in the art for a method and/or device suitable for electrically measuring unidirectional misalignment of stitched masks in etched interconnect layers.
In accordance with the invention, offset detection is isolated to one direction and mask misalignment is used as the variable resistor. In one embodiment the structure has a decreased resistance compared to that of its control structure when a positive offset on the secondary mask of a stitched mask set occurs. In another embodiment the structure has an increased resistance compared to that of its control structure when a positive offset on the secondary mask of a stitched mask set occurs.
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Note that each direction is measured by one set of test pads, and the measurement directions are independent. Thus, horizontal misalignment is measured by interconnects 34, 36, 38 and 52 of
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In this manner mask mismatches may be measured simply by applying a probe to a test pad to measure the resistance between test pads. A method is thus provided for measuring stitched mask misalignment in etched interconnect layers by providing a reference mask having test pads disposed thereon and superimposing on said reference mask a second mask to provide proportional variable resistors between complementary test pads and interconnects of the respective masks, measuring the resistance of the proportional variable resistors, establishing an optimum resistance between interconnects, comparing the measured resistance to said optimum resistance and adjusting the position of said masks to alignment. When the resistance matches the reference resistance the masks are aligned.
While the above describes the preferred embodiment of the invention, various modifications or additions would be apparent to those of skill in the art. For example, the shapes of the interconnects are not limited to those set forth in the Figures. In addition the layout of the masks set forth herein are exemplary and the teachings of the present invention are applicable to any layout contemplated and not limited to what is shown in the Figures.
This application claims the benefit of U.S. Provisional Application Ser. No. 60/497,960 filed Aug. 26, 2003, which is incorporated herein whole by reference.
Filing Document | Filing Date | Country | Kind | 371c Date |
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PCT/IB2004/051568 | 8/26/2004 | WO | 00 | 8/15/2007 |
Publishing Document | Publishing Date | Country | Kind |
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WO2005/019938 | 3/3/2005 | WO | A |
Number | Name | Date | Kind |
---|---|---|---|
3808527 | Thomas | Apr 1974 | A |
4153998 | McMurtry | May 1979 | A |
4386459 | Boulin | Jun 1983 | A |
4437760 | Ausschnitt | Mar 1984 | A |
4571538 | Chow | Feb 1986 | A |
6393714 | Look et al. | May 2002 | B1 |
Number | Date | Country | |
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20080197862 A1 | Aug 2008 | US |
Number | Date | Country | |
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60497960 | Aug 2003 | US |