Claims
- 1. A pair of CMOS devices having self-aligned gates comprising:
- a silicon substrate of a first conductivity type;
- a first region of a second conductivity type opposite said first impurity type formed in said substrate;
- a layer of a silicon oxide forming the gate oxide over a portion of said substrate and of said first region;
- a silicon doped aluminum gate on said silicon oxide layer over each of said portions;
- ion implanted source and drain region of said first impurity type in said first region having adjacent edges vertically aligned with the edges of its respective gate; and
- ion implanted source and drain regions of said second impurity type in said portion of said substrate having adjacent edges vertically aligned with the edges of its respective gate.
- 2. The CMOS devices according to claim 1 wherein said gate is between one and three percent silicon and ninety-nine to ninety-seven percent aluminum.
- 3. The CMOS devices according to claim 1 wherein said substrate is N conductivity type and said first region is P conductivity type; and including a guard ring of P conductivity type at the surface interface of said substrate, guard ring having a greater impurity concentration than said substrate.
- 4. The CMOS devices, according to claim 1 including a second silicon oxide layer over said substrate and said gate and aluminum interconnects extending through apertures in said second silicon oxide layer to said source and drain regions.
Parent Case Info
This is a divisional of application Ser. No. 893,929, filed Apr. 6, 1978, now U.S. Pat. No. 4,313,768 issued Feb. 2, 1982.
US Referenced Citations (12)
Foreign Referenced Citations (1)
Number |
Date |
Country |
50-81177 |
Jun 1975 |
JPX |
Divisions (1)
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Number |
Date |
Country |
Parent |
893929 |
Apr 1978 |
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