Claims
- 1. A method of manufacturing an integrated circuit comprising:
- providing semiconductor device structures in and on a semiconductor substrate;
- depositing a conducting layer overlying the surfaces of said semiconductor device structures and patterning said conducting layer to form conducting lines;
- depositing a dielectric layer comprising:
- conformally depositing a first oxide layer over the surfaces of said conducting layer wherein said first oxide layer comprises subatmospheric chemically vapor deposited ozone-TEOS and is deposited at a first temperature of between about 350.degree. to 370.degree. C. and to a first thickness; and
- depositing a second oxide layer over said first oxide layer wherein said second oxide layer is deposited at a second temperature of between about 430.degree. to 450.degree. C. and to a second thickness wherein said second thickness is greater than said first thickness to complete said dielectric layer; and
- completing the fabrication of said integrated circuit.
- 2. A method according to claim 1 wherein said depositing said dielectric layer further comprises depositing a nucleation layer underlying said first oxide layer and overlying said patterned conducting layer.
- 3. A method according to claim 2 wherein said nucleation layer comprises plasma enhanced chemical vapor deposited silicon oxide.
- 4. A method according to claim 2 wherein said nucleation layer comprises plasma enhanced chemical vapor deposited TEOS oxide.
- 5. A method according to claim 1 wherein said first thickness is between about 500 to 2000 Angstroms.
- 6. A method according to claim 1 wherein said second oxide layer comprises subatmospheric chemically vapor deposited ozone-TEOS.
- 7. A method according to claim 1 wherein said second thickness is between about 3000 to 4500 Angstroms.
- 8. A method according to claim 1 wherein the sum of said first and second thicknesses is more than about 4000 Angstroms.
- 9. A method according to claim 1 wherein said first oxide deposited at said first temperature reduces the pattern sensitivity of said second oxide deposition.
- 10. A method according to claim 1 wherein said second oxide deposited at said second temperature increases the quality of said dielectric layer.
- 11. A method of manufacturing an integrated circuit comprising:
- providing semiconductor device structures in and on a semiconductor substrate;
- depositing a conducting layer overlying the surfaces of said semiconductor device structures and patterning said conducting layer to form conducting lines;
- depositing a dielectric layer comprising:
- depositing a nucleation layer over the surfaces of said conducting layer;
- depositing a first oxide layer overlying said nucleation layer wherein said first oxide layer comprises subatmospheric chemically vapor deposited ozone-TEOS and is deposited at a first temperature of between about 350.degree.-370.degree. C. to a first thickness; and
- depositing a second oxide layer over said first oxide layer wherein said second oxide layer is deposited at a second temperature of between about 430.degree. to 450.degree. C. and to a second thickness wherein said second thickness is greater than said first thickness to complete said dielectric layer; and
- completing the fabrication of said integrated circuit.
- 12. A method according to claim 11 wherein said nucleation layer comprises plasma enhanced chemical vapor deposited silicon oxide.
- 13. A method according to claim 11 wherein said nucleation layer comprises plasma enhanced chemical vapor deposited TEOS oxide.
- 14. A method according to claim 11 wherein said first thickness is between about 500 to 2000 Angstroms.
- 15. A method according to claim 11 wherein said second oxide layer comprises subatmospheric chemically vapor deposited ozone-TEOS.
- 16. A method according to claim 11 wherein said second thickness is between about 3000 to 4500 Angstroms.
- 17. A method according to claim 11 wherein the sum of said first and second thicknesses is more than about 4000 Angstroms.
- 18. A method according to claim 11 wherein said first oxide deposited at said first temperature reduces the pattern sensitivity of said second oxide deposition.
- 19. A method according to claim 11 wherein said second oxide deposited at said second temperature increases the quality of said dielectric layer.
- 20. A method of manufacturing an integrated circuit comprising:
- providing semiconductor device structures in and on a semiconductor substrate;
- depositing a conducting layer overlying the surfaces of said semiconductor device structures and patterning said conducting layer to form conducting lines;
- depositing a dielectric layer comprising:
- depositing a nucleation layer over the surfaces of said conducting layer;
- depositing a first oxide layer overlying said nucleation layer wherein said first oxide layer comprises subatmospheric chemically vapor deposited ozone-TEOS and is deposited at a temperature of between about 350.degree. to 370.degree. C. to a first thickness; and
- depositing a second oxide layer over said first oxide layer wherein said second oxide layer is deposited at a temperature of between about 430.degree. to 450.degree. C. wherein the presence of said first oxide layer reduces the pattern sensitivity of said second oxide deposition and wherein said second oxide layer is deposited to a second thickness wherein said second thickness is greater than said first thickness to increase the quality of said dielectric layer; and
- completing the fabrication of said integrated circuit.
- 21. A method according to claim 20 wherein said nucleation layer comprises plasma enhanced chemical vapor deposited silicon oxide.
- 22. A method according to claim 20 wherein said nucleation layer comprises plasma enhanced chemical vapor deposited TEOS oxide.
- 23. A method according to claim 20 wherein said first thickness is between about 500 to 2000 Angstroms.
- 24. A method according to claim 20 wherein said second oxide layer comprises subatmospheric chemically vapor deposited ozone-TEOS.
- 25. A method according to claim 20 wherein said second thickness is between about 3000 to 4500 Angstroms.
- 26. A method according to claim 20 wherein the sum of said first and second thicknesses is more than about 4000 Angstroms.
RELATED PATENT APPLICATION
1) Co-pending U.S. patent application Ser. No. 08/494,630 (TS94-098) filed on Jun. 23, 1995 to S. M. Jang et al.
US Referenced Citations (9)
Non-Patent Literature Citations (1)
Entry |
Wolf, Stanley, "Si Proc for the VLSI Era" vol. 2, (1990) p. 194. |