Patent Application
20160260674
Embodiments of invention generally relate to semiconductor devices, design structures for designing a semiconductor device, and semiconductor device fabrication methods. More particularly, embodiments relate to the removal of integrated circuit (IC) chips from a wafer.
Numerous integrated circuits are typically manufactured on a single semiconductor wafer. The semiconductor wafer comprises semiconductor chips whereupon the integrated circuits are located. Kerfs or scribe lines separate the chips. The individual chips are typically diced by sawing the wafer along the kerf. The individual chips are then typically packaged, either separately or in a multi-chip module.
Conventional dicing saws are about 62 microns which resulting in a minimum kerf width of about 85 microns between neighboring chips to allow for misalignment of the saw blade. This is wasted area that reduces the number of product IC chips that can fit on a wafer. Further, conventional dicing generally requires cutting along straight lines which results in most IC chips being rectangular and of similar size. In applications where IC chips differ in size, the dicing may destroys or sacrifices some IC chips to obtain a particular IC chip.
During chip dicing operations, cracks form that can propagate into active areas of the IC chip, causing fails. Therefore, crack stop layers have been incorporated into the perimeter of IC chips to prevent the cracks from propagating into the IC chip. Cracks generally propagate through the BEOL (back end of line) dielectrics which are generally brittle materials, such as silicon oxide. Crack stops are generally built around the perimeter of each IC chip, the depth of these structures being limited to the depth of the IC chip device layers. Crack stops can be formed during wafer processing as part of the pattern or during wafer finishing using a laser to create a partial depth groove. Despite use of crack stops, cracks still find their way under and/or through crack stops and significantly impact IC chip yield and reliability. When crack stops are utilized, the minimum width between IC chips is approximately 125 microns, further limiting the number of product IC chips that can fit on the wafer.
In an embodiment of the present invention, a semiconductor device includes an active inner region and a kerf region at the perimeter of the active inner region. The active inner region includes a semiconductor substrate, an integrated circuit (IC) device layer formed upon the semiconductor substrate, and a wiring layer formed upon the IC device layer. The IC device layer includes an IC device and the wiring layer includes wiring making electrical contact with the integrated circuit device. The kerf region includes a through kerf via (TKV) extending through the kerf region.
In another embodiment of the present invention, a wafer includes a plurality of chips separated by a kerf comprising the TKV. Each chip includes an active inner region that includes the semiconductor substrate, the IC device layer formed upon the semiconductor substrate, and the wiring layer formed upon the IC device layer.
In another embodiment of the present invention, a semiconductor structure fabrication method includes forming a semiconductor device upon or within a substrate of a first IC chip separated from a second IC chip by a kerf region, forming a TSV extending through the substrate, forming a TKV extending through the kerf region, and separating the first IC chip from the second IC chip by removing the TKV.
These and other embodiments, features, aspects, and advantages will become better understood with reference to the following description, appended claims, and accompanying drawings.
So that the manner in which the above recited features of the present invention are attained and can be understood in detail, a more particular description of the invention, briefly summarized above, may be had by reference to the embodiments thereof which are illustrated in the appended drawings.
It is to be noted, however, that the appended drawings illustrate only typical embodiments of this invention and are therefore not to be considered limiting of its scope, for the invention may admit to other equally effective embodiments.
The drawings are not necessarily to scale. The drawings are merely schematic representations, not intended to portray specific parameters of the invention. The drawings are intended to depict only exemplary embodiments of the invention. In the drawings, like numbering represents like elements.
Detailed embodiments of the claimed structures and methods are disclosed herein; however, it can be understood that the disclosed embodiments are merely illustrative of the claimed structures and methods that may be embodied in various forms. These exemplary embodiments are provided so that this disclosure will be thorough and complete and will fully convey the scope of this invention to those skilled in the art. In the description, details of well-known features and techniques may be omitted to avoid unnecessarily obscuring the presented embodiments.
Embodiments relate to the removal of integrated circuit (IC) chips from a wafer. In particular, the wafer may include various IC chips separated by a kerf that includes a through kerf via (TKV). The chips are removed from the wafer and separated from each other by removing the TKV. The TKV may be formed simultaneous or subsequent to formation of a through semiconductor via (TSV) within the IC chips. The TKV reduces wasted area of the wafer allowing for more IC chips to be included thereupon. Further, the TKV allows for IC chips to differ in geometry relative to each other.
Embodiments of invention generally relate to semiconductor devices, such as a semiconductor chip (chip). The chip may be planar device and may comprise planar electrodes in parallel planes, made by alternate diffusion of p- and n-type impurities into the semiconductor substrate of the chip. Alternatively, the chip may be a FinFET type device and may comprise a plurality of fins formed from or upon the semiconductor substrate and a gate covering a portion of the fins. The portion of the fins covered by the gate may serve as a channel region of the device. Portions of the fins may also extend out from under the gate and may serve as source and drain regions of the device.
Referring now to the FIGs, wherein like components are labeled with like numerals, exemplary fabrication steps of forming a wafer 5 including multiple chips 10, in accordance with embodiments of the present invention are shown, and will now be described in greater detail below. It should be noted that some of the FIGs depict various cross section views of a portion of chip 10, multiple chips 10, etc. Furthermore, it should be noted that while this description may refer to components of the chip 10 in the singular tense, more than one component may be depicted throughout the figures and within the chip 10. The specific number of components depicted in the figures and the cross section orientation was chosen to best illustrate the various embodiments described herein.
The semiconductor substrate 50 may include, but is not limited to: any semiconducting material such conventional Si-containing materials, Germanium-containing materials, GaAs, InAs and other like semiconductors. Si-containing materials include, but are not limited to: Si, bulk Si, single crystal Si, polycrystalline Si, SiGe, amorphous Si, silicon-on-insulator substrates (SOI), SiGe-on-insulator (SGOI), annealed poly Si, and poly Si line structures. In various embodiments, substrate 50 may be, for example, a layered substrate (e.g. silicon on insulator) or a bulk substrate.
In various embodiments, devices 55 may be formed upon or within the substrate 50. Devices 55 and the process of device 55 fabrication are well known in the art. Devices 55 may be for example, a diode, field effect transistor (FET), metal oxide FET (MOSFET), logic gate, or any suitable combination thereof. Devices 55 also may be components that form a function device such as a gate, fin, source, drain, channel, etc. For clarity, though one device 55 is shown, there are typically numerous devices 55 included within inner active regions 11 of each chip 10. In certain embodiments, devices 55 may be formed within substrate 50. For example, a source and drain may be formed within substrate 50.
The FEOL layer 60 is the layer of chip 10 that generally includes individual devices 55 (e.g. transistors, capacitors, resistors, etc.) patterned in the substrate 50. For example, FinFETs may be implemented in FEOL layer 60 with gate first or gate last FinFET fabrication process techniques. The FEOL layer 60 may include devices 55, one or more dielectric layers, contact 65 to electrically connect device 55 to wiring 75. The BEOL layer 70 is the layer of chip 10 including wiring 75 formed by known wiring 75 fabrication techniques. The BEOL layer 70 may further include one or more dielectric layers and bond sites for chip-to-package connections, etc.
In various embodiments, wafer 5 may further include crack stops 40 for along the perimeter of each chip 10. Crack stop 40 may be formed utilizing known techniques. For example, crack stop 40b may be formed simultaneous to the formation of e.g., devices 55, contact 65, and/or wiring 75. Therefore, each crock stop 40b may include number layers each associated with a particular wiring or device layer. Alternatively, crack stop 40a may be formed by creating a crack stop trench within crack stop region by removing (laser removal, etching, etc.) material within crack stop region 30 and filling the crack stop trench with crack stop material.
Through-silicon hole 80 and through-silicon trench 90 may be formed, for example, utilizing photolithography and a wet etch, dry etch, or combination. More specifically, a pattern may be produced by applying a masking layer such as a photoresist or photoresist with an underlying hardmask, to the surface to be etched; exposing the photoresist to a pattern of radiation; and then developing the pattern into the photoresist utilizing a resist developer. Once the patterning of the photoresist is completed, the sections covered by the photoresist are protected while the exposed regions are removed using a selective etching process that removes the unprotected regions. In certain embodiments, multiple etches may be employed. For example, a first mask may be used to open the layer(s) over the substrate 50 and open an upper portion of the substrate 50 and a second mask to open a lower portion of the substrate 50.
In various embodiments, through-silicon hole 80 and through-silicon trench 90 may be simultaneously formed. For example, one or more similar etch processes, one or more similar etch masks, one or more similar photoresists, etc. may be employed to form both through-silicon hole 80 and through-silicon trench 90 in a similar trench formation stage. In other embodiments, through-silicon trench 90 may be formed in a stand alone through-silicon trench 90 formation stage. For example, subsequent to the completion of active region 11 formation, through-silicon trench 90 may be formed. In embodiments, through-silicon hole 80 and/or through-silicon trench 90 may be formed before, during or after devices 55, contacts 65, or wiring 75.
In various embodiments, through-silicon hole 80 and through-silicon trench 90 may be formed to have a similar depth. In other embodiments through-silicon hole 80 depth D1 may be less than through-silicon trench 90 depth D2. Similarly, the width W1 of through-silicon hole 80 and the width W2 of through-silicon trench 90 may be similar. However, in various embodiments of the invention, W2 may be larger or smaller than W1. Unless otherwise indicated, generally, hole 80 and trench 90 may be formed by other removal techniques without deviating from the sprit of the embodiments herein claimed.
In embodiments, a liner 91 may be formed within trench 90. Liner 91 may be a dielectric material (e.g. silicon oxide), a metal (e.g. tantalum nitride), or a combination, etc.). Liner 91 may form a perimeter barrier of each chip 10 upon chip 10 separation and aid in the prevention of cracks or delamination propagating into active area 11. Liner 91 may be formed by known deposition techniques. For example, liner 91 may be formed using any of several known methods, for example, thermal or plasma oxidation or nitridation methods, chemical vapor deposition methods, physical vapor deposition methods, etc. A directional etching process may be subsequently utilized to open, reform, etc. trench 90. Similarly, a liner 81 may be formed within hole 80. Liner 81 may be a dielectric material (e.g. silicon oxide, etc.), a metal (e.g. tantalum nitride), or a combination, etc. for electrically isolating TSV 100, shown in
TKV 130 may be similar to TSV 100 in that it vertically passes completely through a silicon wafer or die and may be formed in similar fabrication stages. For example, TKV 130 passes through the entire kerf region 20. However, TKV 130 may differ from TSV 100 in that it need not make electrical connection from above or below. TKV 130 may be a pillar, stud, elongated pillar, straight wall, shaped wall, curved wall, fabricated by filling the remaining internal space of the through-silicon trench 90 with a TKV material. TKV material may be similar to the material of TSV 100. Generally, TKV material is a material that may be selectively removed relative to other materials of wafer 5 to effectively separate chips 10. For example, during a subsequent selective removal process, the TKV material is removed and the semiconductor substrate 50 material, FEOL layer 60 material, and BEOL layer 70 material is retained. In embodiments, where a TKV liner 91 is utilized, the TKV material is removed and the TKV liner material 91, semiconductor substrate 50 material, FEOL layer 60 material, and BEOL layer 70 material is retained.
In embodiments, TKV 130 may be fabricated without forming the electrically insulating film on the internal surface of the through-silicon trench 90 but by directly filling the through-silicon trench 90 with a conductive material. In other words, in certain embodiments, TKV 130 need not be electrically isolated from surrounding kerf region 20 material.
In various embodiments, TSV 100 and TKV 130 may be simultaneously formed. For example, one or more similar filling processes, similar fill material, etc. may be employed to form both TSV 100 and TKV 130 in a similar formation stage. In other embodiments, TKV 130 may be formed in a stand alone TKV formation stage. For example, subsequent to the completion of active region 11 formation, TKV 130 may be formed. For example, through-silicon trench 90 may be formed utilizing a laser, etc. in a latter wafer 5 fabrication stage and subsequently filled with TKV material. Unless otherwise indicated, generally, TVK 130 and TSV 100 may be formed known deposition techniques without deviating from the sprit of the embodiments herein claimed. In embodiments where TSV 100 and/or TKV 130 are formed before the last wiring level, additional layers of contacts and/or wiring may be built upon the TSV 100 and or TKV 130, simultaneously to the formation of contacts 65 and/or wiring 75 within inner active region 11.
Backside contact 110 may be an electrically conductive pad, ball, etc. electrically coupled to TSV 100. Contact 110 may be fabricated by forming a pad opening in a deposited dielectric layer, forming a seed layer, performing an electrochemical plating (ECP) to fill the opening with a metallic material, and then performing a CMP to remove excess metallic material. Additional metal layers and bumps (not shown) may also be formed on the backside contact 110, and electrically coupled to TSV 100. Unless otherwise indicated, generally, contact 110 may be formed by deposition techniques without deviating from the sprit of the embodiments herein claimed.
As shown in
Separation trench 180 may be formed, for example, utilizing photolithography and a wet etch, dry etch, or combination. More specifically, a pattern may be produced by applying masking layer such as a photoresist or photoresist with an underlying hardmask, to the surface to be etched; exposing the photoresist to a pattern of radiation; and then developing the pattern into the photoresist utilizing a resist developer. Once the patterning of the photoresist is completed, the sections covered by the photoresist are protected while TKV 130 is removed using a selective etching process that removes the TKV 130 while retaining the materials of e.g., liner 91. Separation trench 180 extends the entire thickness of chip 10, thereby separating neighboring chips 10 upon wafer 5. In certain embodiments, the removal of TKV 130 may be integrated with the removal processes utilized to form the trench 170. In other embodiments, a separate removal technique or process may be utilized. Unless otherwise indicated, generally, trench 180 may be formed by other TKV 130 material removal techniques without deviating from the spirit of the embodiments herein claimed.
Generally, the placement of TKV 130 is customizable to effectively form perimeters of each chip 10 upon wafer 5. Therefore, TKV 130 may be formed around the perimeter of variable sized, differing shaped, etc. chips 10 upon wafer 5. For example, one or more chips 10 upon wafer 5 may be square, rectangular, or irregularly shaped relative to other chips 10 upon wafer 5. Further, the width of TKV 130 may be less than current kerfs. Therefore, a greater number of chips 10 upon wafer 5 may be realized. In certain embodiments, TKV 130 may effectively become the kerf area wherein neighboring chips 10 are separated by only TKV 130. In other words, in utilizing embodiments of the present invention, crack stop region 30 becomes optional.
Method 220 may continue by forming wiring 75 upon substrate 50 electrically coupled to devices 55 (block 226). Method 220 may continue by forming trough silicon hole 80 within the active region 11 of chip 10 and through silicon trench 90 within kerf region 20 (block 228). In some embodiments, trough silicon hole 80 and through silicon trench 90 may be formed simultaneously (i.e. during similar trench formation processes, etc.). In other embodiments, through silicon trench 90 may be formed in distinct trench formation processes, e.g. subsequent to fabricating active region 11 of chip 10. In embodiments, a liner 91 may be formed with trench 90 and/or a liner 81 may be formed within hole 80.
Method 220 may continue by forming wiring 75 upon substrate 50 electrically coupled to devices 55 (block 226). Method 220 may continue by forming trough silicon hole 80 within the active region 11 of chip 10 and through silicon trench 90 within kerf region 20 (block 228). In some embodiments, trough silicon hole 80 and through silicon trench 90 may be formed simultaneously (i.e. during similar trench formation processes, etc.). In other embodiments, through silicon trench 90 may be formed in distinct trench formation processes, e.g. subsequent to fabricating active region 11 of chip 10. In embodiments, a liner 91 may be formed with trench 90 and/or a liner 81 may be formed within hole 80.
Method 220 may continue by forming TSV 100 by filling trough silicon hole 80 with electrically conductive material and by forming and forming TKV 130 by filling through silicon trench 90 with a material that may be removed (block 230). In certain embodiments, an electrically insulating layer 81 is formed adjacent to the walls of trough silicon hole 80 prior to filling the trough silicon hole 80 with electrically conductive material. In certain embodiments, an electrically insulating layer 91 is formed adjacent to the walls of trough silicon trench 90 prior to filling the trough silicon trench 90 with TKV material.
TKV 130 may be fabricated by filling the internal space of the through-silicon trench 90 with a material that may be selectively removed in relation to the material of substrate 50, material of FEOL layer 60 formed upon substrate 50, and material of BEOL layer 70, formed upon FEOL layer 60. In embodiments, where liner 91 is utilized, TKV 130 may be fabricated by filling the internal space of the through-silicon trench 90 with a material that may be selectively removed in relation to the material of liner 91, substrate 50, material of FEOL layer 60 formed upon substrate 50, and material of BEOL layer 70, formed upon FEOL layer 60. The material of TKV 130 may be electrically conductive, a dielectric, etc. In some embodiments, TSV 100 and TKV 130 may be formed simultaneously (i.e. during similar trench formation processes, etc.). In other embodiments, TKV 130 may be formed in distinct trench formation processes, e.g. subsequent to fabricating active region 11 of chip 10.
Method 220 may continue by forming one or more contacts 110, 120 on the front side or backside of chip 10, respectively, electrically coupled to TSV 100 (block 232). In other words, in certain embodiments, TKV 130 is not electrically coupled to contacts 110, 120, etc. Method 220 may continue with separating and removing the first chip 10 and second chip 10 from wafer 5 removing the TKV 130 (block 234). In various embodiments, of the present invention, TKV 130 passes through the entire kerf region 20. Method 220 ends at block 236.
Referring now to
The design structures processed and/or generated by design flow 300 may be encoded on machine-readable transmission or storage media to include data and/or instructions that when executed or otherwise processed on a data processing system generate a logically, structurally, mechanically, or otherwise functionally equivalent representation of hardware components, circuits, devices, or systems. Machines include, but are not limited to, any machine used in an IC design process, such as designing, manufacturing, or simulating a circuit, component, device, or system. For example, machines may include: lithography machines, machines and/or equipment for generating masks (e.g. e-beam writers), computers or equipment for simulating design structures, any apparatus used in the manufacturing or test process, or any machines for programming functionally equivalent representations of the design structures into any medium (e.g. a machine for programming a programmable gate array).
Design flow 300 may vary depending on the type of representation being designed. For example, a design flow 300 for building an application specific IC (ASIC) may differ from a design flow 300 for designing a standard component or from a design flow 300 for instantiating the design into a programmable array, for example a programmable gate array (PGA) or a field programmable gate array (FPGA) offered by Altera® Inc. or Xilinx® Inc.
When encoded on a machine-readable data transmission, gate array, or storage medium, design structure 320 may be accessed and processed by one or more hardware and/or software modules within design process 310 to simulate or otherwise functionally represent an electronic component, circuit, electronic or logic module, apparatus, device, structure, or system such as those shown in
Design process 310 preferably employs and incorporates hardware and/or software modules for synthesizing, translating, or otherwise processing a design/simulation functional equivalent of the components, circuits, devices, or structures shown
Design process 310 may include hardware and software modules for processing a variety of input data structure types including Netlist 380. Such data structure types may reside, for example, within library elements 330 and include a set of commonly used elements, circuits, and devices, including models, layouts, and symbolic representations, for a given manufacturing technology (e.g., different technology nodes, 14, 32 nm, 45 nm, 90 nm, etc.). The data structure types may further include design specifications 340, characterization data 350, verification data 360, design rules 370, and test data files 385 which may include input test patterns, output test results, and other testing information. Design process 310 may further include, for example, standard mechanical design processes such as stress analysis, thermal analysis, mechanical event simulation, process simulation for operations such as casting, molding, and die press forming, etc.
One of ordinary skill in the art of mechanical design can appreciate the extent of possible mechanical design tools and applications used in design process 310 without deviating from the scope and spirit of the invention claimed herein. Design process 310 may also include modules for performing standard circuit design processes such as timing analysis, verification, design rule checking, place and route operations, etc.
Design process 310 employs and incorporates logic and physical design tools such as HDL compilers and simulation model build tools to process design structure 320 together with some or all of the depicted supporting data structures along with any additional mechanical design or data (if applicable), to generate a second design structure 390. Design structure 390 resides on a storage medium or programmable gate array in a data format used for the exchange of data of mechanical devices and structures (e.g. information stored in a IGES, DXF, Parasolid XT, JT, DRG, or any other suitable format for storing or rendering such mechanical design structures).
Similar to design structure 320, design structure 390 preferably comprises one or more files, data structures, or other computer-encoded data or instructions that reside on transmission or data storage media and that when processed by an ECAD system generate a logically or otherwise functionally equivalent form of one or more of the embodiments of the invention shown in
Design structure 390 may also employ a data format used for the exchange of layout data of integrated circuits and/or symbolic data format (e.g. information stored in a GDSII (GDS2), GL1, OASIS, map files, or any other suitable format for storing such design data structures). Design structure 390 may comprise information such as, for example, symbolic data, map files, test data files, design content files, manufacturing data, layout parameters, wires, levels of metal, vias, shapes, data for routing through the manufacturing line, and any other data required by a manufacturer or other designer/developer to produce a device or structure as described above and shown in
The accompanying figures and this description depicted and described embodiments of the present invention, and features and components thereof. Those skilled in the art will appreciate that any particular nomenclature used in this description was merely for convenience, and thus the invention should not be limited by the specific process identified and/or implied by such nomenclature. Therefore, it is desired that the embodiments described herein be considered in all respects as illustrative, not restrictive, and that reference be made to the appended claims for determining the scope of the invention.
The exemplary methods and techniques described herein may be used in the fabrication of integrated circuit chips. The resulting integrated circuit chips can be distributed by the fabricator in raw wafer form (i.e., as a single wafer that has multiple unpackaged chips), as a bare die, or in a packaged form. In the latter case, the chip is mounted in a single chip package (e.g., a plastic carrier, with leads that are affixed to a motherboard or other higher level carrier) or in a multichip package (e.g., a ceramic carrier that has either or both surface interconnections or buried interconnections). The chip is then integrated with other chips, discrete circuit elements and/or other signal processing devices as part of either (a) an intermediate product, such as a motherboard, or (b) an end product. The end product can be any product that includes integrated circuit chips, ranging from toys and other low-end applications to advanced computer products having numerous components, such as a display, a keyboard or other input device and/or a central processor, as non-limiting examples.
References herein to terms such as “vertical”, “horizontal”, etc. are made by way of example, and not by way of limitation, to establish a frame of reference. The term “horizontal” as used herein is defined as a plane parallel to the conventional plane or surface of the substrate, regardless of the actual spatial orientation of the semiconductor substrate. The term “vertical” refers to a direction perpendicular to the horizontal, as just defined. Terms, such as “on”, “above”, “below”, “side” (as in “sidewall”), “higher”, “lower”, “over”, “beneath” and “under”, are defined with respect to the horizontal plane. It is understood that various other frames of reference may be employed for describing the present invention without departing from the spirit and scope of the present invention.
