The present invention relates to semiconductor processing and semiconductor devices, and more particularly, to a method for removal of stray ruthenium metal nuclei from non-growth surfaces for selective ruthenium metal layer formation.
Semiconductor devices contain filled recessed features such as trenches or vias that are formed in a dielectric material such as an interlayer dielectric (ILD). Selective metal filling of the recessed features is problematic due to finite metal deposition selectivity on a metal layer at the bottom of the recessed features relative to on the dielectric material. This makes it difficult to fully fill the recessed features with a metal in a bottom-up deposition process before the on-set of unwanted metal nuclei deposition on the field area (horizontal area) around the recessed features and on the sidewalls of the recessed features.
A method is provided for removal of stray Ru metal nuclei for selective Ru metal layer formation. According to one embodiment, a method of forming a semiconductor device includes providing a patterned substrate containing a dielectric layer and a metal layer, and depositing ruthenium (Ru) metal on the patterned substrate by vapor phase deposition, where a Ru metal layer is deposited on a surface of the metal layer and Ru metal nuclei are deposited on a surface of the dielectric layer. The method further includes removing the Ru metal nuclei by gas phase etching using an ozone (O3) gas exposure that forms volatile ruthenium oxide species by oxidation of the Ru metal nuclei. Thereafter, the method further includes repeating the depositing and removing steps at least once to increase a thickness of the Ru metal layer. The depositing of the Ru metal is interrupted before the Ru metal nuclei reach a critical size that results in formation of non-volatile ruthenium oxide species and incomplete removal of the Ru metal nuclei during the gas phase etching.
According to one embodiment, the method includes providing a patterned substrate containing a dielectric layer and a metal layer, and depositing ruthenium (Ru) metal on the patterned substrate by vapor phase deposition, where a Ru metal layer is deposited on a surface of the metal layer and Ru metal nuclei are deposited on a surface of the dielectric layer. The method further includes removing a portion of the Ru metal nuclei by gas phase etching using an O3 gas exposure that forms volatile ruthenium oxide species by oxidation of the Ru metal nuclei, exposing the patterned substrate to a reducing gas containing H2 gas that converts any non-volatile ruthenium oxide species formed during the O3 gas exposure back to metallic Ru, and repeating the depositing, removing, and exposing steps at least once to increase a thickness of the Ru metal layer. According to one embodiment, the removing and exposing steps are repeated at least once to fully remove the Ru metal nuclei before the depositing step is repeated.
A more complete appreciation of the invention and many of the attendant advantages thereof will be readily obtained as the same becomes better understood by reference to the following detailed description when considered in connection with the accompanying drawings, wherein:
Embodiments of the invention provide a method for selectively forming a low-resistivity Ru metal layer on a metal layer relative to a dielectric layer on a patterned substrate. According to one embodiment, exposed surfaces of the dielectric layer and the metal layer are in the same horizontal plane, for example after a planarization process. According to another embodiment, a recessed feature is formed in the dielectric layer and the metal layer is exposed in the recessed feature. The recessed feature can include a trench having a first width, and a via containing the metal layer and having a second width that is less than the first width. However, the method is not limited to those structures and may be applied to simpler and more complex structures found in manufacturing of semiconductor devices.
As schematically shown in
According to one embodiment, the etch stop layer 102 and the dielectric layer 104 contain SiO2, a low dielectric constant (low-k) material such as fluorinated silicon glass (FSG), carbon doped oxide, a polymer, a SiCOH-containing low-k material, a non-porous low-k material, a porous low-k material, a CVD low-k material, a spin-on dielectric (SOD) low-k material, or any other suitable dielectric material, including a high dielectric constant (high-k) material. In some examples, a width (critical dimension (CD)) of the via 105 in the recessed feature 101 can be between about 10 nm and about 100 nm, between about 10 nm and about 15 nm, between about 20 nm and about 90, or between about 40 nm and about 80 nm. In some examples, the depth of the via 105 can between bout 40 nm and about 200 nm, between about 50 nm and about 150, or between about 50 nm and about 150 nm. Further, in some examples, a width of the trench 103 can be between about 20 nm and about 200 nm, and a depth of the trench 103 can be between about 50 nm and about 300 nm.
The method further includes depositing Ru metal on the patterned substrate 1 by vapor phase deposition. According to some embodiments of the invention, the Ru metal may be deposited by chemical vapor phase deposition (CVD) or atomic layer deposition (ALD). Examples of volatile Ru precursors that may be used include triruthenium dodecacarbonyl (Ru3(CO)12), (2,4-dimethylpentadienyl) (ethylcyclopentadienyl) ruthenium (Ru(DMPD)(EtCp)), bis(2,4-dimethylpentadienyl) ruthenium (Ru(DMPD)2), 4-dimethylpentadienyl) (methylcyclopentadienyl) ruthenium (Ru(DMPD)(MeCp)), and bis(ethylcyclopentadienyl) ruthenium (Ru(EtCp)2), as well as combinations of these and other Ru precursors. In one example, Ru metal may be deposited by CVD using a Ru3(CO)12 precursor in a CO carrier gas.
As depicted in
The method further includes interrupting the deposition of the Ru metal and, thereafter, removing the unwanted Ru metal nuclei 112a from the dielectric layer 104 by gas phase etching using an ozone (O3) gas exposure. This is schematically shown in
The sequential steps of depositing the Ru metal and removing the Ru metal nuclei 112a may be performed at the same or substantially the same substrate temperature (e.g., ˜180° C.) in a single process chamber. This allows for fast and effective processing of the patterned substrate 1 with high substrate throughput. Further, performing the sequential steps in a single process chamber can reduce substrate contamination and prevent air exposure.
The sequential steps of depositing the Ru metal and removing the Ru metal nuclei 112a may be repeated at least once to increase a thickness of the Ru metal layer 112 on the metal layer 106 in the recessed feature 101, until a desired thickness of the Ru metal layer 112 is achieved. In one example, shown in
Referring back to
Following the H2 gas exposure, the sequential steps of depositing the Ru metal and removing the Ru metal nuclei 112a may be repeated at least once.
The sequential steps of depositing the Ru metal and removing the Ru metal nuclei 112a may be repeated at least once to increase a thickness of the Ru metal layer 112 on the metal layer 106 in the recessed feature 101, until a desired thickness of the Ru metal layer 112 is achieved. In one example, shown in
Methods for removal of stray ruthenium metal nuclei from non-growth surfaces for selective ruthenium metal layer formation been disclosed in various embodiments. The foregoing description of the embodiments of the invention has been presented for the purposes of illustration and description. It is not intended to be exhaustive or to limit the invention to the precise forms disclosed. This description and the claims following include terms that are used for descriptive purposes only and are not to be construed as limiting. Persons skilled in the relevant art can appreciate that many modifications and variations are possible in light of the above teaching. Persons skilled in the art will recognize various equivalent combinations and substitutions for various components shown in the Figures. It is therefore intended that the scope of the invention be limited not by this detailed description, but rather by the claims appended hereto.
This application claims priority to and the benefit of the filing date of U.S. Provisional Patent Application No. 63/146,494, filed Feb. 5, 2021, which application is incorporated herein by reference in its entirety.
Number | Date | Country | |
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63146494 | Feb 2021 | US |