Claims
- 1. A resist mark for measuring the accuracy of overlay of a photomask disposed on semiconductor wafer, comprising:
a first measurement mark having a first opening, formed on the substrate; an intermediate layer formed on the first measurement mark and in the first opening; a frame-shaped second measurement mark formed on the intermediate layer; a third measurement mark that is spaced from the second measurement mark toward the outside, formed on the intermediate layer; and wherein the second measurement mark has a width which is short enough not to be influenced by a deformation caused by the thermal flow phenomenon.
- 2. A resist mark as claimed in claim 1, wherein the second measurement mark has a width in the range 0.3-1.0 μm.
- 3. A resist mark as claimed in claim 1, wherein a distance between the second measurement mark and the third measurement mark is in the range 0.3-1.0 μm.
- 4. A resist mark as claimed in claim 1, further comprising a fourth measurement mark formed in an area surrounded by the second measurement mark, the fourth measurement mark being spaced from the second measurement mark.
- 5. A resist mark as claimed in claim 4, wherein the second measurement mark has a width in the range 0.3-1.0 μm.
- 6. A resist mark as claimed in claim 1, wherein a distance between the second measurement mark and the third measurement mark is in the range 0.3-1.0 μm.
- 7. A resist mark as claimed in claim 1, wherein the second measurement mark is connected to the third measurement mark at the corners of the second measurement mark.
- 8. A resist mark as claimed in claim 7, wherein the second measurement mark has a width in the range 0.3-1.0 μm.
- 9. A resist mark as claimed in claim 7, wherein a distance between the second measurement mark and the third measurement mark is in the range 0.3-1.0 μm.
- 10. A resist mark as claimed in claim 7, further comprising a fourth measurement mark formed in an area surrounded by the second measurement mark, the fourth measurement mark being spaced from the second measurement mark.
- 11. A resist mark as claimed in claim 11, wherein the second measurement mark has a width in the range 0.3-1.0 μm.
- 12. A resist mark as claimed in claim 7, wherein a distance between the second measurement mark and the third measurement mark is in the range 0.3-1.0 μm.
- 13. A resist mark as claimed in claim 7, wherein the second measurement mark surrounds an area, and the area having a side, and wherein the space isolates the second measurement mark from the third measurement mark, the space having a length substantially the same as the length of the side of the area surrounded by the second measurement mark.
- 14. A method for manufacturing a semiconductor wafer having a resist mark for measuring the accuracy of overlay of a photomask disposed on the semiconductor wafer, comprising:
forming a first layer on the semiconductor wafer; forming a first rectangularly shaped opening in the first layer to make a first measurement mark; forming an intermediate layer on the first measurement mark and in the first opening; forming a second layer on the intermediate layer; forming a second measurement mark and a third measurement mark by forming a second rectangularly shaped opening and a frame-shaped opening in the second layer, the second rectangularly shaped opening being located above the first opening, the second measurement mark being isolated form the third measurement mark by the frame-shaped opening; wherein the second measurement mark is formed in a frame-shaped; and wherein the second measurement mark has a width which is short enough not to be influenced by a deformation caused by the thermal flow phenomenon.
- 15. A method for manufacturing a semiconductor wafer according to claim 14, further comprising, forming a fourth measurement mark in the second opening, the fourth measurement mark being spaced from the second measurement mark.
- 16. A method for manufacturing a semiconductor wafer according to claim 15, wherein, said forming the fourth measurement mark includes forming the fourth measurement mark simultaneously with the second and third measurement marks.
- 17. A method for manufacturing a semiconductor wafer having a resist mark for measuring the accuracy of overlay of a photomask disposed on the semiconductor wafer, comprising:
forming a first layer on the semiconductor wafer; forming a first rectangularly shaped opening in the first layer to make a first measurement mark; forming an intermediate layer on the first measurement mark and in the first opening; forming a second layer on the intermediate layer; forming a second measurement mark and a third measurement mark by forming a second rectangularly shaped opening and four openings in the second layer, the second rectangularly shaped opening being located above the first opening, the second measurement mark being formed in a frame-shaped, the four openings being formed along by each side of the second measurement mark, and the second measurement mark being connected to the third measurement mark at its corners; and wherein the second measurement mark has a width which is short enough not to be influenced by a deformation caused by the thermal flow phenomenon.
- 18. A method for manufacturing a semiconductor wafer according to claim 17, further comprising, forming a fourth measurement mark in the second opening, the fourth measurement mark being spaced from the second measurement mark.
- 19. A method for manufacturing a semiconductor wafer according to claim 18, wherein, said forming a fourth measurement mark includes forming the fourth measurement mark simultaneously with the second and third measurement marks.
Priority Claims (1)
Number |
Date |
Country |
Kind |
10-362716 |
Dec 1998 |
JP |
|
CROSS-REFERENCE TO RELATED APPLICATION
[0001] This application claims the priority benefit of Japanese Patent Application No. 10-362716, filed Dec. 21, 1998, the entire subject matter of which is incorporated herein of reference.
Divisions (1)
|
Number |
Date |
Country |
Parent |
09458819 |
Dec 1999 |
US |
Child |
10061285 |
Feb 2002 |
US |
Continuations (1)
|
Number |
Date |
Country |
Parent |
10061285 |
Feb 2002 |
US |
Child |
10196413 |
Jul 2002 |
US |