Patent Application
20160088722
This disclosure generally relates to information handling systems, and more particularly relates to a the use and application of rough copper in an information handling system printed circuit board.
As the value and use of information continues to increase, individuals and businesses seek additional ways to process and store information. One option is an information handling system. An information handling system generally processes, compiles, stores, and/or communicates information or data for business, personal, or other purposes. Because technology and information handling needs and requirements may vary between different applications, information handling systems may also vary regarding what information is handled, how the information is handled, how much information is processed, stored, or communicated, and how quickly and efficiently the information may be processed, stored, or communicated. The variations in information handling systems allow for information handling systems to be general or configured for a specific user or specific use such as financial transaction processing, reservations, enterprise data storage, or global communications. In addition, information handling systems may include a variety of hardware and software resources that may be configured to process, store, and communicate information and may include one or more computer systems, data storage systems, and networking systems.
A printed circuit board for an information handling system can use copper traces for providing power and for carrying signals for the information handling system. The surface roughness of the copper has an impact on the performance of the traces. For example a copper trace with a smooth surface will exhibit lower insertion loss and less phase variation in the conducted signals than a similar copper trace with a rougher surface. Moreover, this effect is enhanced as the signal frequency is increased. This is because at higher signal frequencies the signals are conducted closer to the surface of the conductor, and so the profile of the copper surface has a greater impact on the signal quality.
It will be appreciated that for simplicity and clarity of illustration, elements illustrated in the Figures have not necessarily been drawn to scale. For example, the dimensions of some of the elements are exaggerated relative to other elements. Embodiments incorporating teachings of the present disclosure are shown and described with respect to the drawings presented herein, in which:
The use of the same reference symbols in different drawings indicates similar or identical items.
The following description in combination with the Figures is provided to assist in understanding the teachings disclosed herein. The following discussion will focus on specific implementations and embodiments of the teachings. This focus is provided to assist in describing the teachings, and should not be interpreted as a limitation on the scope or applicability of the teachings. However, other teachings can certainly be used in this application. The teachings can also be used in other applications, and with several different types of architectures, such as distributed computing architectures, client/server architectures, or middleware server architectures and associated resources.
For purpose of this disclosure an information handling system can include any instrumentality or aggregate of instrumentalities operable to compute, classify, process, transmit, receive, retrieve, originate, switch, store, display, manifest, detect, record, reproduce, handle, or utilize any form of information, intelligence, or data for business, scientific, control, entertainment, or other purposes. For example, an information handling system can be a personal computer, a laptop computer, a smart phone, a tablet device or other consumer electronic device, a network server, a network storage device, a switch router or other network communication device, or any other suitable device and may vary in size, shape, performance, functionality, and price. Further, an information handling system can include processing resources for executing machine-executable code, such as a central processing unit (CPU), a programmable logic array (PLA), an embedded device such as a System-on-a-Chip (SoC), or other control logic hardware. An information handling system can also include one or more computer-readable medium for storing machine-executable code, such as software or data. Additional components of an information handling system can include one or more storage devices that can store machine-executable code, one or more communications ports for communicating with external devices, and various input and output (I/O) devices, such as a keyboard, a mouse, and a video display. An information handling system can also include one or more buses operable to transmit information between the various hardware components.
In manufacturing, a typical core layer 110 will be assembled with a coating of copper on the two surfaces of the core layer, a pattern of circuit traces will be provided on the copper coatings, and the excess copper from the two sides will be etched off of the surfaces to leave power plane trace 112 and circuit trace 114. Note that, while being described as a single power plane trace and a single circuit trace, in application, power plane trace 112 and circuit trace 114 will include multiple circuit traces, as needed or desired. With each of the four core layers 110 patterned with their associated traces 112 and 114, the four core layers are interleaved with three pre-preg layers 114, and the entire assembly is bonded together, typically using a pressure process, to make the completed printed circuit board 100.
Power plane layers 112 are illustrated as having a rough copper surface, while trace layers 114 are illustrated as having smooth copper layers. Note that the surface profiles of traces 112 and 114 in printed circuit board 100 are greatly exaggerated for the purpose of illustration, and that the relative roughness or smoothness of layers 112 and 114 would likely appear similar upon unaided visual inspection. The surface roughness of traces 112 and 114 are measured based upon a particular profile roughness parameter. An example of a profile roughness parameter includes an arithmetic average of absolute values parameter (Ra), a root mean square parameter (Rq), a skewness parameter (Rsk), or another profile roughness parameter, as needed or desired.
In a particular embodiment, the copper coatings that are used to make traces 112 and 114 are commercially available copper coatings, such as rolled copper foils with an Rq surface roughness of around 0.4 micrometers (μm), electrodeposited copper foils with an Rq surface roughness of around 0.5 to 3.5 μm, and resistive copper foils with an Rq surface roughness of around 1.0 to 2.0 μm. Here, for example, power trace 112 can be manufactured using a rough copper coating such as an electrodeposited copper foil with an Rq surface roughness at the higher end of the available coatings, such as with an Rq of between 1.5 and 3.5 μm, or such as a resistive foil with a similar Rq value. Further, circuit trace 114 can be manufactured using a smooth copper coating such as a rolled copper foil with an Rq surface roughness of around 0.4, or such as an electrodeposited copper foil with an Rq surface roughness at the lower end of the available coatings, such as with an Rq of between 0.5 and 1.5 μm.
In another embodiment, the copper coatings that are used to make traces 112 and 114 are commercially available copper coatings, and power trace 114 is further processed to increase the surface roughness. For example, a copper coating for both power trace 112 and circuit trace 114 can be selected that has a relatively smooth surface roughness, and the copper coating of power trace 112 can be mechanically or chemically roughened to provide a surface roughness of around 25 μm. In this way, a common processing methodology to adhere the copper coatings for both power trace 112 and circuit trace 114, and then the additional processing can be performed only on the power trace 112.
Devices 230, 240, and 250 include one or more high speed data interfaces that operate to rapidly move data between the devices. The data is transferred on signal traces, not shown, of printed circuit board 200. Thus, due to cross-talk effects and other coupling effects, power trace 212 can provide an undesirable high frequency element to devices 230, 240, and 250. For example, if via cross-talk between a signal trace and power trace 212, a high frequency signal from device 230 is injected into the power trace, the high frequency signal can be provided to the vie power node 220 to the circuit power node of device 240 as an undesirable power supply noise component.
However, because power trace 212 is formed using rough copper, the insertion loss of the rough copper operates to dampen the high frequency signal and clean up the power delivered to devices 230, 240, and 250. Thus power node 220 is shown schematically as being connected to device 230 via a high frequency impedance 232, to device 240 via a high frequency impedance 242, and to device 250 via a high frequency impedance 252.
Information handling system 400 can include devices or modules that embody one or more of the devices or modules described above, and operates to perform one or more of the methods described above. Information handling system 400 includes a processors 402 and 404, a chipset 410, a memory 420, a graphics interface 430, include a basic input and output system/extensible firmware interface (BIOS/EFI) module 440, a disk controller 450, a disk emulator 460, an input/output (I/O) interface 470, and a network interface 480. Processor 402 is connected to chipset 410 via processor interface 406, and processor 404 is connected to the chipset via processor interface 408. Memory 420 is connected to chipset 410 via a memory bus 422. Graphics interface 430 is connected to chipset 410 via a graphics interface 432, and provides a video display output 436 to a video display 434. In a particular embodiment, information handling system 400 includes separate memories that are dedicated to each of processors 402 and 404 via separate memory interfaces. An example of memory 420 includes random access memory (RAM) such as static RAM (SRAM), dynamic RAM (DRAM), non-volatile RAM (NV-RAM), or the like, read only memory (ROM), another type of memory, or a combination thereof.
BIOS/EFI module 440, disk controller 450, and I/O interface 470 are connected to chipset 410 via an I/O channel 412. An example of I/O channel 412 includes a Peripheral Component Interconnect (PCI) interface, a PCI-Extended (PCI-X) interface, a high-speed PCI-Express (PCIe) interface, another industry standard or proprietary communication interface, or a combination thereof. Chipset 410 can also include one or more other I/O interfaces, including an Industry Standard Architecture (ISA) interface, a Small Computer Serial Interface (SCSI) interface, an Inter-Integrated Circuit (I2C) interface, a System Packet Interface (SPI), a Universal Serial Bus (USB), another interface, or a combination thereof. BIOS/EFI module 440 includes BIOS/EFI code operable to detect resources within information handling system 400, to provide drivers for the resources, initialize the resources, and access the resources. BIOS/EFI module 440 includes code that operates to detect resources within information handling system 400, to provide drivers for the resources, to initialize the resources, and to access the resources.
Disk controller 450 includes a disk interface 452 that connects the disc controller to a hard disk drive (HDD) 454, to an optical disk drive (ODD) 456, and to disk emulator 460. An example of disk interface 452 includes an Integrated Drive Electronics (IDE) interface, an Advanced Technology Attachment (ATA) such as a parallel ATA (PATA) interface or a serial ATA (SATA) interface, a SCSI interface, a USB interface, a proprietary interface, or a combination thereof. Disk emulator 460 permits a solid-state drive 464 to be connected to information handling system 400 via an external interface 462. An example of external interface 462 includes a USB interface, an IEEE 1394 (Firewire) interface, a proprietary interface, or a combination thereof. Alternatively, solid-state drive 464 can be disposed within information handling system 400.
I/O interface 470 includes a peripheral interface 472 that connects the I/O interface to an add-on resource 474, to a TPM 476, and to network interface 480. Peripheral interface 472 can be the same type of interface as I/O channel 412, or can be a different type of interface. As such, I/O interface 470 extends the capacity of I/O channel 412 when peripheral interface 472 and the I/O channel are of the same type, and the I/O interface translates information from a format suitable to the I/O channel to a format suitable to the peripheral channel 472 when they are of a different type. Add-on resource 474 can include a data storage system, an additional graphics interface, a network interface card (NIC), a sound/video processing card, another add-on resource, or a combination thereof. Add-on resource 474 can be on a main circuit board, on separate circuit board or add-in card disposed within information handling system 400, a device that is external to the information handling system, or a combination thereof.
Network interface 480 represents a NIC disposed within information handling system 400, on a main circuit board of the information handling system, integrated onto another component such as chipset 410, in another suitable location, or a combination thereof. Network interface device 480 includes network channels 482 and 484 that provide interfaces to devices that are external to information handling system 400. In a particular embodiment, network channels 482 and 484 are of a different type than peripheral channel 472 and network interface 480 translates information from a format suitable to the peripheral channel to a format suitable to external devices. An example of network channels 482 and 484 includes InfiniBand channels, Fibre Channel channels, Gigabit Ethernet channels, proprietary channel architectures, or a combination thereof. Network channels 482 and 484 can be connected to external network resources (not illustrated). The network resource can include another information handling system, a data storage system, another network, a grid management system, another suitable resource, or a combination thereof.
Although only a few exemplary embodiments have been described in detail herein, those skilled in the art will readily appreciate that many modifications are possible in the exemplary embodiments without materially departing from the novel teachings and advantages of the embodiments of the present disclosure. Accordingly, all such modifications are intended to be included within the scope of the embodiments of the present disclosure as defined in the following claims. In the claims, means-plus-function clauses are intended to cover the structures described herein as performing the recited function and not only structural equivalents, but also equivalent structures.
The above-disclosed subject matter is to be considered illustrative, and not restrictive, and the appended claims are intended to cover any and all such modifications, enhancements, and other embodiments that fall within the scope of the present invention. Thus, to the maximum extent allowed by law, the scope of the present invention is to be determined by the broadest permissible interpretation of the following claims and their equivalents, and shall not be restricted or limited by the foregoing detailed description.
