Sequential elements such as flip-flops or latches are conventional building blocks in sequential digital circuits. A sequential element typically has a data input, a clock input, and a data output. The data input is copied to the data output at a time controlled by the clock. Sequential elements have timing attributes including setup time, hold time, and clock-to-Q delay describing the timing relationships between the data input, clock input, and data output. Scannable sequential elements may also provide a test input and a test enable signal so that the elements can be configured into a scan chain, facilitating testing the digital circuits. Such elements have additional timing attributes related to the test input instead of the data input.
A system and/or circuit is provided for scannable sequential elements, substantially as illustrated by and/or described in connection with at least one of the figures, as set forth more completely in the claims.
Certain features of the subject disclosure are set forth in the appended claims. However, for purpose of explanation, several implementations of the subject disclosure are set forth in the following figures.
It is understood that other configurations of the subject disclosure will become readily apparent to those skilled in the art from the following detailed description, wherein various configurations of the subject disclosure are shown and described by way of illustration. As will be realized, the subject disclosure is capable of other and different configurations and its several details are capable of modification in various other respects, all without departing from the scope of the subject disclosure. Accordingly, the drawings and detailed description are to be regarded as illustrative in nature and not as restrictive.
In one or more aspects, a sequential element (e.g., flip-flop 102) is a digital element whose output depends on previous as well as current inputs. In other words, the element has memory or retains state. A sequential element can be used to keep data in sequence as it moves through a digital pipeline or finite state machine. Examples of sequential elements include positive-edge-triggered flip-flops, negative-edge-triggered flip-flops, dual-edge-triggered flip-flops, pulsed latches, two-phase latches, Muller C elements, and others. Scannable sequential elements can choose between an ordinary input and a test input based on a test enable signal. The figures in this disclosure illustrate scannable positive-edge triggered flip-flops, but the subject disclosure is also applicable to other scannable sequential elements.
Moreover, the figures in this disclosure illustrate implementations using complementary metal-oxide semiconductor (CMOS) transistors, but the subject disclosure is also applicable to any other device capable of implementing digital logic including, but not limited to, bipolar transistors, tunnel transistors, gallium arsenide transistors, micro-electro-mechanical relays, Josephson junctions, and discrete components.
The maximum speed of the digital circuit 120 is limited by the time for a signal to come out of a flip-flop (e.g. 140), propagate through a combinational logic block (e.g. 130), and setup at the next flip-flop (e.g. 142). If the logic block has a propagation delay tpd, the clock period needs to be at least:
T
c
=t
pcq
+t
pd
+t
setup
=t
pdq
+t
pd
Therefore, it is important to minimize the sequencing overhead tpdq 218 from the data input 110 to the data output 118.
During test mode, signals propagate directly from the output of one flip-flop to the input of the next, generally without combinational logic between flops. Hence, these test paths usually do not limit the speed of the system. However, the test input 112 needs to remain stable at the input of a flip-flop for some hold time 212 after the rising edge of the clock 116. If tccq>thold, the flip-flops alone is too fast to ensure this constraint. In such a case, the designer may need to insert delay elements, such as inverters, buffers, transmission gates, wires, and so forth, between the flip-flops in the scan chain. These delay elements increase the size, cost, and power of the circuit and are undesirable.
Moreover, some circuits have significant delays, called clock skew, between the clocks going to different flip-flops. When one flip-flop switches early and the next switches late because of clock skew, even more delay elements are required to satisfy the hold time. Therefore, it is important to minimize the hold time 212 on the test input 112 to reduce the number of delay elements in the system.
The master stage 302 includes three pass gates. Pass gates 350 and 352 serve as the scan multiplexer, while pass gate 354 serves as the master latch. When the test enable input 114 is 0, pass gate 350 is ON and pass gate 352 is OFF, so D flows through inverter 360 and pass gate 350 to node A 320. When the test enable input 114 is 1, pass gate 352 is ON and pass gate 350 is OFF, so TI flows through inverter 362 and pass gate 352 to node A 320. When φ 116 is 0, pass gate 354 is ON and node A 320 flows through to node Xb 324. Thus, the master stage 302 is transparent and samples the value from D or TI onto node Xb 324. When φ 116 is 1, pass gate 354 is OFF. Thus the master stage 302 is opaque and node Xb 324 retains the last sampled value. Inverter 364 inverts node Xb 324 to produce node X 322.
The slave stage 304 includes pass gate 356 that serves as the slave latch. When φ is 0, the pass gate is OFF and the slave is opaque, so Q retains its old value. When φ is 1, the pass gate is ON and the slave is transparent, so the value at node Xb 324 flows through the pass gate 356 and inverters 366 and 368 to the data output 118.
When the master stage 302 is opaque, a feedback tristate inverter 380 turns ON to retain the value at node X 322. When the master is transparent, feedback tristate inverter 380 turns OFF to avoid contention (i.e. to avoid fighting the value flowing through the master). Similarly, feedback tristate inverter 382 retains the value at node Qb 326 while the slave is opaque.
In summary, the master and slave stages behave as two locks on a canal. When φ is 0, the D or TI input is selected (based on TE) and flows through the transparent master to node X 322, where it is blocked by the opaque slave. When φ rises to become 1, the slave becomes transparent and the value at node X 322 flows through to Q while the master becomes opaque and isolates node X 322 from changes on the inputs. Hence, the flip-flop copies D to Q on the rising edge of φ and retains its value at all other times.
The master stage 302 has a data path and a test path. The data path is the path from D to node X 322 through inverters 360 and 364 and pass gates 350 and 354. The test path is the path from TI to node X 322 through inverters 362 and 364 and pass gates 352 and 354. Both paths involve two pass gates and two inverters, so they are relatively slow. This slow delay means the setup time is relatively large but the hold time is relatively short.
Referring to
Various inverters and/or tristate inverters in the scannable sequential element 300 may be replaced with more complex gates to integrate logic into the flip-flop. For example, the inverter at the data input 110 can be replaced with a 2-input NAND gate also coupled to RESETb to create a synchronously resettable flip-flop. Similarly the inverter can be replaced with an inverting multiplexer to create a mux-flop.
A pulsed latch can be used in place of a flip-flop. A scannable pulsed latch includes a master stage but not a slave stage of the scannable sequential element 300. A scannable pulsed latch may further include an additional clocked pass gate to prevent hold time problems when operated in test mode.
In one or more implementations, a test input, a test enable input and a test path may be sometimes referred to as a scan input, a scan enable input, a scan path, respectively.
As stated above with respect to
Moreover, scanning techniques include selectively gating a clock input of each sequential element to reduce the sequencing overhead. However, clock gating increases the number of clocked transistors in the scan chain, which increases power consumption. In addition, clock gating can delay the clock input, resulting in a longer hold time requirement at each sequential element. If the hold time is too long, the designer needs to insert delay elements into the scan chain, increasing the size, cost, and power consumption of the circuit
In applications such as building high-speed circuits, sequential elements with short setup time and clock-to-Q delay between the data input and data output may be desired. In one or more implementations, the delay between the test input and data output may be less significant, but the test input needs a short hold time. In one or more implementations, if the hold time is too long, delay elements may need to be inserted into the scan chain, increasing the size, cost, and power consumption of the circuit. Hence, there is a need for, among others, sequential elements having fast delay on the data input and short hold time on the test input according to one or more implementations.
As such, a scannable sequential element with skew tolerance and short scan hold times in accordance with one or more implementations is provided, which uses a single pass gate (sometimes referred to as a transmission gate) on a data path that only receives data signals, controlled by a gated clock signal, for low sequencing overhead. Additionally, the scannable sequential element uses series pass gates on a test path that only receives test signals, respectively controlled by the clock signal and a test enable signal, for a relatively short hold time requirement on the test path.
In one or more aspects, a clock signal is logically combined with the test enable signal to form the gated clocked signal. An overlap between the clock signal and gated clocked signal exists that creates a transparency period during which pass gates located on the data path are configured to toggle simultaneously. In turn, the clock overlap significantly reduces the sequencing overhead, which speeds up the data path between master and slave portions of the scannable sequential element. In addition, the clock overlap provides for an increase in tolerance to clock skewing, which in turn, provides for increased hold times. In one or more implementations, the clock overlap can be increased by adding buffers, series transistors or capacitive loads.
In one or more aspects, a data path is configured to receive (or process or provide) one or more data signals but not any test signals (or test inputs). In one or more aspects, a test path is configured to receive (or process or provide) one or more test signals but not any data signals (or data inputs). In some implementations, the master stage 402 may include less than or greater than the number of components shown in
When the test enable input 114 is 0, the gates 420 and 422 of gated clock generator 404 produce gated clocks φdb 410 and φd 412, respectively, that are inverted and delayed versions of the clock φ 116. Thus, the data path is ON when φ 116 is 0 and OFF when φ 116 is 1. When TE is 1, gated clocks φdb 410 and φd 412 are held at 0 and 1, respectively, so the data path is OFF. However, the test path behaves just as it did in master stage 302. Thus, the master stage 402 behavior is unchanged from 302, but one pass gate is removed from the data path, reducing the setup time on the data input. In summary, the scannable sequential element 400 is faster on the D input than the scannable sequential element 300, while maintaining a short hold time on the TI input. In one or more aspects, the gate 420 is a NOR gate and the gate 422 is an inverter. In one or more aspects, the gated clock generator 404 may produce the complementary clock φb 317, which is the complement of the clock φ 116.
Note that the two pass gates 352 and 354 from the master stage test path of the scannable sequential element 300 are preferably swapped in the master stage 402. The pass gate 354 toggles with φ 116, even when the test path is not active. By making this swap, the pass gate 354 is isolated from the node X 322, reducing the capacitance on the node X 322. Although the flip-flop generally will function with either ordering of pass gates 352 and 354, the arrangement in the scannable sequential element 400 may be faster and consume less power.
Moreover, the flip-flop demonstrates a degree of skew-tolerance because the sequencing overhead becomes independent of the clock or data arrival time during the transparency window, as will be shown in
During the transparency window, the scannable sequential elements 400 and 500 have both the data path pass gate 450 and the feedback tristate inverter 380 simultaneously ON. The contention between the pass gate and the tristate increases the data path delay in the master stage 402. Therefore, it can be minimized.
In one or more aspects, feedback tristates can also be constructed from a gate (including but not limited to an inverter, NAND, or NOR) followed by one or more pass gates.
One or more implementations are performed by one or more integrated circuits, such as application specific integrated circuits (ASICs) or field programmable gate arrays (FPGAs). In one or more implementations, such integrated circuits execute instructions that are stored on the circuit itself. In one or more aspects, the term “integrated circuit” includes, but is not limited to, a design tool output file as binary code encompassing the overall physical design of the integrated circuit, a data file encoded with code representing the overall physical design of the integrated circuit, a packaged integrated circuit, or an unpackaged die. The data file can include elements of the integrated circuit, interconnections of those elements, and timing characteristics of those elements (including parasitics of the elements).
The terms “input” and “output” as used herein may refer to a non-transitory signal or a physical item such as a node, a circuit, a block, a pad, a terminal, a port, a raised semiconductor structure, and other similar physical items.
The various illustrative blocks, elements, components, and methods described herein may be implemented as electronic hardware. Various illustrative blocks, elements, components, and methods have been described above generally in terms of their functionality. Whether such functionality is implemented as hardware depends upon the particular application and design constraints imposed on the overall system. Skilled artisans may implement the described functionality in varying ways for each particular application. Various components and blocks may be arranged differently (e.g., arranged in a different order, or partitioned in a different way) all without departing from the scope of the subject technology.
The predicate words “configured to” and “operable to” do not imply any particular tangible or intangible modification of a subject, but, rather, are intended to be used interchangeably. In one or more implementations, a receiver configured to receive and process an operation or a component may also mean the receiver being operable to receive and process the operation.
Phrases such as an aspect, the aspect, another aspect, some aspects, one or more aspects, an implementation, the implementation, another implementation, some implementations, one or more implementations, an embodiment, the embodiment, another embodiment, some embodiments, one or more embodiments, a configuration, the configuration, another configuration, some configurations, one or more configurations, the subject technology, the disclosure, the present disclosure, other variations thereof and alike are for convenience and do not imply that a disclosure relating to such phrase(s) is essential to the subject technology or that such disclosure applies to all configurations of the subject technology. A disclosure relating to such phrase(s) may apply to all configurations, or one or more configurations. Such disclosure may provide one or more examples. A phrase such as an aspect may refer to one or more aspects and vice versa, and this applies similarly to other phrases.
Any implementation described herein as an “example” is not necessarily to be construed as preferred or advantageous over other implementations. Furthermore, to the extent that the term “include,” “have,” or the like is used in the description or the claims, such term is intended to be inclusive in a manner similar to the term “comprise” as “comprise” is interpreted when employed as a transitional word in a claim.
All structural and functional equivalents to the elements of the various aspects described throughout this disclosure that are known or later come to be known to those of ordinary skill in the art are expressly incorporated herein by reference and are intended to be encompassed by the claims. Moreover, nothing disclosed herein is intended to be dedicated to the public regardless of whether such disclosure is explicitly recited in the claims. No claim element is to be construed under the provisions of 35 U.S.C. §112, sixth paragraph, unless the element is expressly recited using the phrase “means for” or, in the case of a method claim, the element is recited using the phrase “step for.”
The previous description is provided to enable any person skilled in the art to practice the various aspects described herein. Various modifications to these aspects will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other aspects. Thus, the claims are not intended to be limited to the aspects shown herein, but are to be accorded the full scope consistent with the language claims, wherein reference to an element in the singular is not intended to mean “one and only one” unless specifically so stated, but rather “one or more.” Unless specifically stated otherwise, the term “some” refers to one or more. Pronouns in the masculine (e.g., his) include the feminine and neuter gender (e.g., her and its) and vice versa. Headings and subheadings, if any, are used for convenience only and do not limit the subject disclosure.
The present application claims the benefit of U.S. Provisional Patent Application Ser. No. 61/813,536, titled “SCANNABLE SEQUENTIAL ELEMENTS,” filed on Apr. 18, 2013, which is hereby incorporated by reference in its entirety for all purposes.
Number | Date | Country | |
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61813536 | Apr 2013 | US |