Scheduling and Traffic Management with Offload Processors

Abstract

A scheduling system for a packet processing system is disclosed. The system can include a classification circuit connected to a memory bus and configurable to classify network packets, placing the classified network packets into first multiple input/output queues, a scheduling circuit for reordering the network packets received from the classification circuit through the first multiple input/output queues and placing the reordered network packets into second multiple input/output queues, an arbitration circuit for directing network packets received from the scheduling circuit through the second multiple input/output queues to multiple output ports, and multiple offload processors, each coupled to at least one of the multiple output ports, the offload processors configured to modify the network packets.

Description

TECHNICAL FIELD

Described embodiments relate to scheduling and traffic management services for computer systems that can be provided by a memory bus connected module with offload processors.

BACKGROUND

Efficient managing of network packet flow and processing is critical for high performance networked computing systems. Network packet flow can be highly variable, depending on hardware configurations, process flows and data flows, with data processing needs varying over several orders of magnitude on time scales that can range from seconds to hours. Substantial improvements in network service are made possible by systems that can flexibly process a data flow, recognize or characterize patterns in the data flow, and improve routing and processing decisions for the data flow. This is of particular importance for networked computer environment using packet switching communication. For example, delays in data flow are often created due to network security required packet inspection. Such packet inspection may be directed at either a header of the packet or a payload of the packet, and can include processor content matching, behavioral anomaly detection, “black” or “white” listing comparisons, or the like. Other high packet processing applications can include encryption/decryption, quality of service controlled packet reassembly, streaming sensor data, or video or audio processing. Without an efficient mechanism for scheduling packet processing arriving as part of a complex data flow system, users may encounter unacceptable delays in network system response.

Commonly available traffic management circuits supporting a packet switch fabric capable of handling complex data flow streams often include depth-limited output queues, the access to which is arbitrated by a scheduling circuit. The input queues are managed using a scheduling discipline to provide traffic management for incoming data flows. Schedulers may allocate or identify a data flow priorities and provide output port to each of these data flows. If multiple data flows compete for the same output port, time multiplexed access to each of the output ports can be provided, or alternatively multiple data flows contending for an output port may be arbitrated by an arbitration circuit before being sent out over an output port. However, a traffic management circuit typically has limited or no access to information relating to handling and management of data by downstream memory or processing elements. For example, based on an allocation of priority, data flow performance can be improved if incoming packets can be dynamically reordered in a buffer to help maintain persistence of session flows in these queues. The scheduling discipline chosen for such packet processing prioritization or traffic management (TM), can affect the traffic shape of flows and micro-flows through delay (buffering), bursting of traffic (buffering and bursting), smoothing of traffic (buffering and rate-limiting flows), dropping traffic (choosing data to discard so as to avoid exhausting the buffer), or delay jitter (temporally shifting cells of a flow by different amounts).

SUMMARY

This disclosure describes embodiments of systems, hardware and methods suitable to act as a scheduling system for a packet processing system. The system includes a classification circuit connected to a memory bus and configurable to classify network packets. The classification circuit can place the classified network packets into first multiple input/output queues. A scheduling circuit can reorder the network packets received from the classification circuit through the first multiple input/output queues and place the reordered network packets into second multiple input/output queues. An arbitration circuit directs network packets received from the scheduling circuit through the second multiple input/output queues to multiple output ports. Multiple offload processors, each connected to one of the multiple output ports, are respectively configured to modify network packets.

In certain embodiments the memory bus supports direct memory access, and multiple offload processors can direct modified packets back to the memory bus. In addition, the classification circuit can classify network packets based on session metadata. In still other embodiments, the scheduling circuit can direct network packets based on availability of respective multiple offload processors; reorder network packets according to session priority; initiates a context switch for the multiple offload processors; transfer network packets into a defined traffic management queue; check with each of the multiple offload processors to determine if respective network packet processing is complete; or operate in preemption mode to control session execution.

Another embodiment is a method for scheduling packet processing, including the step of classifying network packets based on session metadata and placing the classified network packets into first multiple input/output queues, with packets transported to a classification circuit using a memory bus having a defined memory transport protocol. Reordered network packets received from the first multiple input/output queues using a scheduling circuit can be placed into a second multiple input/output queues, where an arbitration circuit directs network packets received from the scheduling circuit through the second multiple input/output queues into multiple output ports. These network packets can be modified using multiple offload processors, each offload processor respectively connected to one of the multiple output ports, with the respective offload processers able to direct modified packets back to the memory bus.

Another embodiment described includes a memory bus connected module for scheduling services for network packet processing. The module includes a memory bus connection and a scheduling circuit for reordering the network packets received from the memory bus connection and placing the reordered network packets into multiple input/output queues. Multiple offload processors are connected to the memory bus connection, with each offload processor capable of modifying network packets placed into multiple input/output queues. The memory bus connection can be compatible with a memory bus socket, and in certain embodiments be formed to fit into a dual in-line memory module (DIMM) socket.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1-0 shows a traffic management and scheduler system according to an embodiment.

FIG. 1-1 shows a scheduling process according to an embodiment.

FIG. 1-2 shows a module supporting multiple scheduling circuits and an arbitration circuit according to an embodiment.

FIGS. 2-0 to 2-3 show processor modules according to various embodiments.

FIG. 2-4 shows a conventional dual-in-line memory module.

FIG. 2-5 shows a system according to another embodiment.

FIG. 3 shows one particular implementation of a memory bus connected offload processor that can be included in embodiments.

FIG. 4 shows an exemplary flow chart for a scheduling process according to an embodiment.

DETAILED DESCRIPTION

Various embodiments of the present invention will now be described in detail with reference to a number of drawings. The embodiments show processing systems and methods for scheduling packet flow in a packet processing systems. Such scheduling can be performed by, or with the use of, offload modules connect to a memory bus of a system. Such offload processors can be in addition to any host processors connected to the system memory bus, and, in some embodiments, process packets transferred over the system memory bus independent of any host processors. In very particular embodiments, processing modules can populate physical slots for connecting in-line memory modules (e.g., DIMMs) to a system memory bus.

FIG. 1-0 is a diagram of a system 100 for providing scheduling and traffic management services. A system 100 can include a switch 106, host processor section 108/110, memory controller 112, and offload processing section 116/116/118. In the particular embodiment shown, host processor section can include a switch 106, a switching fabric 108, host processor(s) 110, and a bus interconnect 109 connected to memory controller 112. Further, offload processing section can be in communication with memory controller 112, and can include a switch 114, scheduler 116 and offload processor(s) 118.

In operation, a switch 106 can receive and/or transmit data packets 104 from data source 102. A data source 102 can be any suitable source of packet data, including the Internet, a network cloud, inter- or intra-data center networks, cluster computers, rack systems, multiple or individual servers or personal computers, or the like. Data can be packet or switch based, although in particular embodiments non-packet data is generally converted or encapsulated into packets for ease of handling. The data packets typically have certain characteristics, including transport protocol number, source and destination port numbers, or source and destination (Internet Protocol) IP addresses. The data packets can further have associated metadata that helps in packet classification and management.

A switch 106 can be a virtual switch (an I/O device). A switch 106 can include, but is not limited to, devices compatible with peripheral component interconnect (PCI) and/or PCI express (PCIe) devices connecting with host motherboard via PCI or PCIe bus 107. The switch 106 can include a network interface controller (NIC), a host bus adapter, a converged network adapter, or a switched or an asynchronous transfer mode (ATM) network interface. In some embodiments, a switch 106 can employ IO virtualization schemes such as a single root I/O virtualization (SR-IOV) interface to make a single network I/O device appear as multiple devices. SR-IOV permits separate access to resources among various PCIe hardware functions by providing both physical control and virtual functions. In certain embodiments, the switch 106 can support OpenFlow or similar software defined networking to abstract out of the control plane. The control plane of the first virtual switch performs functions such as route determination, target node identification etc.

A switch 106 can be capable of examining network packets, and using its control plane to create appropriate output ports for network packets. Based on route calculation for the network packets or data flows associated with the network packets, the forwarding plane of the switch 106 can transfer the packets to an output interface. An output interface of the switch may be connected with an IO bus, and in certain embodiments the switch 106 may have the capability to directly (or indirectly, via an I/O fabric 108) transfer the network packets to a memory bus interconnect 109 for a memory read or write operation (direct memory access operation). Functionally, for certain applications the network packets can be assigned for transport to specific memory locations based on control plane functionality.

Switch 106, connected to an IO fabric 108 and memory bus interconnect 109, can also be connected to host processor(s) 110. Host processor(s) 110 can include one or more host processors which can provide computational services including a provisioning agent 111. The provisioning agent 111 can be part of an operating system or user code running on the host processor(s) 110. The provisioning agent 111 typically initializes and interacts with virtual function drivers provided by system 100. The virtual function driver can be responsible for providing the virtual address of the memory space where a direct memory addressing (DMA) is needed. Each device driver can be allocated virtual addresses that map to the physical addresses. A device model can be used to create an emulation of a physical device for the host processor 110 to recognize each of the multiple virtual functions (VF) that can be created. The device model can be replicated multiple times to give the impression to VF drivers (a driver that interacts with a virtual IO device) that they are interacting with a physical device. For example, a certain device model may be used to emulate a network adapter that the VF driver can act to connect. The device model and the VF driver can be run in either privileged or non-privileged mode. There can be no restriction with regard to which device hosts/runs the code corresponding to the device model and the VF driver. The code, however, can have the capability to create multiple copies of device model and VF driver so as to enable multiple copies of said I/O interface to be created. In certain embodiments the operating system can also create a defined physical address space for applications supported by VF drivers. Further, the host operating system can allocate a virtual memory address space to the application or provisioning agent. The provisioning agent 111 can broker with the host operating system to create a mapping between virtual addresses and a subset of the available physical address space. The provisioning agent 111 can be responsible for creating each VF driver and allocating it a defined virtual address space.

By operation of such memory mapping, data (e.g., packet data) can be transmitted from switch 106 offload processor section 114/116/118. A second switch 114 can also be connected to the memory controller 112 by memory bus 109. A second switch 114 can be a virtual switch, and can receive and switch traffic originating from the memory bus 109 both to and from offload processor(s) 118. Traffic may include, but is not limited to, data flows to virtual devices created and assigned by the provisioning agent 111, with processing supported by offload processors 118. The forwarding plane of the second switch 114 can transports packets from a memory bus 109 to offload processors 118 or from the offload processors 118 back onto the memory bus 109. For certain applications, the described system architecture can allow relatively direct communication of network packets to the offload processors 118 with minimal or no interruptions to a host processor(s) 110. The second switch 114 can be capable of receiving packets and classifying them prior to distribution to different hardware schedulers based on a defined arbitration and scheduling scheme. The hardware scheduler 116 receives packets that can be assigned to flow sessions that are scheduled for processing in one or more separate sessions run by offload processor(s) 118.

In particular embodiments, scheduler 116 can be employed to implement traffic management of incoming packets. Packets from a certain source, relating to a certain traffic class, pertaining to a specific application or flowing to a certain socket are referred to as part of a session flow and are classified using session metadata. Session metadata often serve as the criterion by which packets are prioritized and as such, incoming packets can be reordered based on their session metadata. This reordering of packets can occur in one or more buffers and can modify the traffic shape of these flows. Packets of a session that are reordered based on session metadata can be sent over to specific traffic managed queues that are arbitrated out to output ports using an arbitration circuit (not shown). The arbitration circuit can feed these packet flows to a downstream packet processing/terminating resource directly. Certain embodiments provide for integration of thread and queue management so as to enhance the throughput of downstream resources handling termination of network data through above said threads.

As will be understand, multiple types of conventional input/output busses such as PCI, Fibre Channel can be used in system embodiments described herein. The bus architecture can also be based on relevant JEDEC standards, on DIMM data transfer protocols, on Hypertransport, or any other suitable high speed, low latency interconnection system. Offload processor(s) 118 may include double data rate (DDR) dynamic random access memory (DRAM), reduced latency DRAM (RLDRAM), embedded DRAM, next generation stacked memory such as Hybrid Memory Cube (HMC), flash, or other suitable memory, separate logic or bus management chips, programmable units such as field programmable gate arrays (FPGAs), custom designed application specific integrated circuits (ASICs) and an energy efficient, general purpose processor such as those based on ARM, ARC, Tensilica, MIPS, Strong/ARM, or RISC architectures. Host processor(s) 110 can include general purpose processor(s), including those based on Intel or AMD x86 architecture, Intel Itanium architecture, MIPS architecture, SPARC architecture or the like.

FIG. 1-1 illustrates one embodiment of a hardware scheduled data flow method 140 suitable for operation in conjunction with an embodiment like that of FIG. 1-0. As seen in flowchart 140, a hardware scheduler can manage traffic by segregating packets based on sessions (141). In some embodiments, sessions are identified by metadata of the packets. Sessions can be prioritized and queued (142) and a general purpose operating system (OS) running on one or more offload processors can be used control execution of a current session (143). A hardware scheduler can use the current state of the OS, including numbers of session, state of the session, feedback from the OS relating to processing resources or future scheduling requirements, etc., to make scheduling decisions or arbitration between competing processes for memory resources (144). If certain conditions are met, the hardware scheduler can initiate a context switch in which a current session has its state stored in memory, and a new session is begun or returned to (145).

FIG. 1-2 illustrates one embodiment of a hardware scheduler 150 (i.e., a scheduling circuit). The hardware scheduler 150 can include input ports 152/152′, classification circuit 154, input queues (one shown as 156), scheduling circuits 158/158′, output queues (one shown as 160), arbitration circuit 162, and output ports 164/164′. Connected to the hardware scheduler can be common packet status registers 166/166′, packet buffers 168/168′, one or more cache memory ports 170 (which can be an accelerator coherency port ACP, in one particular embodiment), and a low latency memory 172. It is understood that while FIG. 1-2 shows an architecture with two input ports and two output ports, alternate embodiments can include one input and output port, or more than two such ports.

The hardware scheduler 150 can receive packets from an arbiter circuit (not shown) that is connected to several such hardware schedulers. The hardware scheduler 150 can receive such data at one or more input ports 152/152′. The hardware scheduler 150 can employ a classification circuit 154, which can examine incoming packets, and based on metadata present in the packets, classifies packets into different incoming queues. The classification circuit 154 can examine different packet headers, and can use an interval matching circuit to carry out segregation of incoming packets. One suitable interval matching circuit is described in U.S. Pat. No. 7,760,715 issued to Dalal on Aug. 4, 2007 (hereinafter the '715 patent). However, any other suitable classification scheme may be employed to execute the classification circuit.

The hardware scheduler 150 can be connected with packet status registers 166/166′ for communicating with offload processors (not shown). Registers 166/166′ can be operated upon by both the hardware scheduler 150 and an OS running on an offload processor. The hardware scheduler can also be connected with a packet buffer 168/168′ to store outgoing packets of a session or for processing to/by an offload processor OS. A detailed explanation of packet status registers and packet buffers that can be included in embodiments is given below.

The hardware scheduler 150 can use port 170 to access data related to a session that is currently running on an offload processor OS in the cache of the offload processor and transfer it out using a bulk transfer during a context switch to a different session. The hardware scheduler 150 can uses the cache transfer to reduce the overhead associated with the session. The hardware scheduler 150 can also use a low latency memory 172 to store the session related information from the cache for its subsequent access.

As noted above, a hardware scheduler 150 can have more than one input port 152/152′. The data coming into the hardware scheduler may be packet data waiting to be terminated at the offload processors or it could be packet data waiting to be processed, modified or switched out. The hardware scheduler 150 can be responsible for segregating incoming packets into corresponding application sessions based on examination of packet data. The hardware scheduler 150 can be capable of packet inspection and identifying relevant packet characteristics.

A hardware scheduler 150 may offload part of the network stack to free offload processors from overhead incurred from such network stack processing. A hardware scheduler 150 may carry out any of TCP/transport offload, encryption/decryption offload, segmentation and reassembly, or the like, thus allowing the offload processor to use the payload of the network packets directly.

In some embodiments, hardware scheduler 150 can further have the capability to transfer the packets belonging to a session into a particular traffic management queue (e.g., 156) for its scheduling (158) and transfer to an output queues (e.g., 160). The hardware scheduler 150 may be used to control the scheduling of each of these persistent sessions into a general purpose OS. The stickiness of sessions across a pipeline of stages, including a general purpose OS, can be accentuated by a scheduler circuit 150 carrying out optimizations at each of the stages in the pipeline (described in more detail below). For example, a hardware scheduler 150 can takes into account of downstream execution resources. The session flows queued in each of these queues can be sent out through an output port to a downstream network element. One particular implementation of such scheduling is shown in the '715 patent, which is incorporated herein by reference, in its entirety.

Referring still to FIG. 1-2, a hardware scheduler 150 may employ an arbitration circuit 162 to arbitrate or otherwise control access of multiple traffic management output queues to available output ports. Each of the output ports may be connected to one of the offload processor cores through a packet buffer 168/168′. A packet buffer 168/168′ may further include a header pool and a packet body pool. A header pool can contain only the header of packets to be processed by offload processors. Sometimes, if the size of the packet to be processed is sufficiently small, the header pool may contain the entire packet. Packets can be transferred over to the header pool/packet body pool depending on the nature of operation carried out at the offload processor. For packet processing, overlay, analytics, filtering and such other applications it might be appropriate to transfer only the packet header to the offload processors. In this case, depending on the handling of the packet header, the packet body might either be sewn together with a packet header and transferred over an egress interface, or dropped. For applications requiring the termination of packets, the entire body of the packet might be transferred. The offload processor cores may receive the packets and execute suitable application session on them to execute said packet contents.

A hardware scheduler 150 can schedule different sessions on a downstream processor, wherein the two are operated in coordination to reduce the overhead during context switches. A hardware scheduler 150 can be understood to arbitrate not just between outgoing queues or session flows at line rate speeds, but between terminated sessions at very high speeds. The hardware scheduler 150 can manage the queuing of sessions on the offload processor. A scheduling circuit 158/158′ can be responsible for queuing each session flow into the OS as a different OS processing entity. Scheduling circuit 158/158′ can be responsible for causing the execution of a new application session on the OS. It can indicate to the OS that packets for a new session are available based on traffic management carried out by it.

A hardware scheduler 150 can be informed of the state of the execution resources on the offload processors, the current session that is run on the execution resource, the memory space allocated to it, and the location of the session context in the processor cache. It can use the state of the execution resource to carry out traffic management and arbitration decisions. The hardware scheduler 150 can provide for an integration of thread management on the operating system with traffic management of incoming packets. It can induce persistence of session flows across a spectrum of components including traffic management queues and processing entities on the offload processors. An OS running on a downstream (e.g. offload) processor may allocate execution resources such as processor cycles and memory to a particular queue it is currently handling. The OS may further allocate a thread or a group of threads for that particular queue, so that it is handled distinctly by the general purpose processing element as a separate entity. The fact that there are multiple sessions running on a general purpose (GP) processing resource, each handling data from a particular session flow resident in a queue on the hardware scheduler, can tightly integrate the hardware scheduler and the downstream resource. This can bring an element of persistence within session information across the traffic management and scheduling circuit and the general purpose processing resource. Further, the offload OS can be modified to reduce the penalty and overhead associated with context switch between resources. This is further exploited by the hardware scheduler to carry out seamless switching between queues, and consequently their execution as different sessions by the execution resource.

In effect, in some embodiments a hardware scheduler can be employed to implement traffic management of incoming packets. Packets from a certain source, relating to a certain traffic class, pertaining to a specific application or flowing to a certain socket are referred to as part of a session flow and can be classified using session metadata. Session metadata often serve as the criterion by which packets are prioritized and as such, incoming packets are reordered based on their session metadata. This reordering of packets can occur in one or more buffers and can modify the traffic shape of these flows. Packets of a session that are reordered based on session metadata can be sent over to specific traffic managed queues that are arbitrated out to output ports using an arbitration circuit. An arbitration circuit (e.g. 162) can feed these packet flows to a downstream packet processing/terminating resource directly. Certain embodiments provide for integration of thread and queue management so as to enhance the throughput of downstream resources handling termination of network data through above said threads.

Accordingly, a hardware scheduler can perform any of the following functions:

a) the hardware scheduler is responsible for carrying out traffic management, arbitration and scheduling of incoming network packets (and flows);b) hardware scheduler is responsible for offloading part of the network stack of the offload OS, so that the offload OS can be kept free of stack level processing and resources are free to carry out execution of application sessions;c) the hardware scheduler is responsible for classification of packets based on packet metadata, and packets classified into different session are queued in output traffic queues are sent over to the offload OS;d) the hardware scheduler is responsible for cooperating with minimal overhead context switching between terminated sessions on the offload OS; the hardware scheduler ensures that multiple sessions on the offload OS can be switched with as minimal overhead as possible (the ability to switch between multiple sessions on the offload sessions makes it possible to terminate multiple sessions at very high speeds, providing packet processing speeds for terminated sessions);d) the hardware scheduler is responsible for queuing each session flow into the OS as a different OS processing entity;e) the hardware scheduler is responsible for causing the execution of a new application session on the OS, it can indicate to the OS that packets for a new session are available based on traffic management carried out by it;f) the hardware scheduler is informed of the state of the execution resources on the offload processors, the current session that is run on the execution resource and the memory space allocated to it, the location of the session context in the processor cache. The hardware scheduler can use the state of the execution resource to carry out traffic management and arbitration decisions. The hardware scheduler can provide for an integration of thread management on the operating system with traffic management of incoming packets. It can induce persistence of session flows across a spectrum of components including traffic management queues and processing entities on the offload processors.

As will be understood, many of the foregoing processing tasks can be implemented on multiple threads running on multiple processing cores. Such parallelization of tasks into multiple thread contexts can provide for increased throughput. Processors architectures such as MIPS may include deep instruction pipelines to improve the number of instructions per cycle. Further, the ability to run a multi-threaded programming environment results in enhanced usage of existing processor resources. To further increase parallel execution on the hardware, processor architecture may include multiple processor cores. Multi-core architectures comprising the same type of cores, referred to as homogeneous core architectures, provide higher instruction throughput by parallelizing threads or processes across multiple cores. However, in such homogeneous core architectures, the shared resources, such as memory, are amortized over a small number of processors. In still other embodiments, multiple offload or host processors can reside on modules connected to individual rack units or blades that in turn reside on racks or individual servers. These can be further grouped into clusters and datacenters, which can be spatially located in the same building, in the same city, or even in different countries. Any grouping level can be connected to each other, and/or connected to public or private cloud internets.

Memory and I/O accesses can incur a high amount of processor overhead. Further, context switches in conventional general purpose processing units can be computationally intensive. It is therefore desirable to reduce context switch overhead in a networked computing resource handling a plurality of networked applications in order to increase processor throughput. Conventional server loads can require complex transport, high memory bandwidth, extreme amounts of data bandwidth (randomly accessed, parallelized, and highly available), but often with light touch processing: HTML, video, packet-level services, security, and analytics. Further, idle processors still consume more than 50% of their peak power consumption.

In contrast, according to embodiments herein, complex transport, data bandwidth intensive, frequent random access oriented, ‘light’ touch processing loads can be handled behind a socket abstraction created on multiple offload processor cores. At the same time, “heavy” touch, computing intensive loads can be handled by a socket abstraction on a host processor core (e.g., x86 processor cores). Such software sockets can allow for a natural partitioning of these loads between ARM and x86 processor cores. By usage of new application level sockets, according to embodiments, server loads can be broken up across the offload processing cores and the host processing cores.

FIGS. 2-0 to 2-5 describe aspects of hardware embodiments and methods for providing scheduling and traffic management services using processing modules. In particular embodiments, such processing modules can include DIMM mountable modules to support offload processing.

FIG. 2-0 is a block diagram of a processing module 200 according to one embodiment. A processing module 200 can include a physical connector 202, a memory interface 204, arbiter logic 206, offload processor(s) 208, local memory 210, and control logic 212. A connector 202 can provide a physical connection to system memory bus. This is in contrast to a host processor which can access a system memory bus via a memory controller, or the like. In very particular embodiments, a connector 202 can be compatible with a dual in-line memory module (DIMM) slot of a computing system. Accordingly, a system including multiple DIMM slots can be populated with one or more processing modules 200, or a mix of processing modules and DIMM modules.

A memory interface 204 can detect data transfers on a system memory bus, and in appropriate cases, enable write data to be stored in the processing module 200 and/or read data to be read out from the processing module 200. Such data transfers can include the receipt of packet data having a particular network identifier. In some embodiments, a memory interface 204 can be a slave interface, thus data transfers are controlled by a master device separate from the processing module 200. In very particular embodiments, a memory interface 204 can be a direct memory access (DMA) slave, to accommodate DMA transfers over a system memory bus initiated by a DMA master. In some embodiments, a DMA master can be a device different from a host processor. In such configurations, processing module 200 can receive data for processing (e.g., DMA write), and transfer processed data out (e.g., DMA read) without consuming host processor resources.

A memory interface 204 can detect data transfers on a system memory bus, and in appropriate cases, enable write data to be stored in the processing module 200 and/or read data to be read out from the processing module 200. In some embodiments, a memory interface 204 can be a slave interface, thus data transfers are controlled by a master device separate from the processing module. In very particular embodiments, a memory interface 204 can be a direct memory access (DMA) slave, to accommodate DMA transfers over a system memory initiated by a DMA master. In some embodiments, a DMA master can be a device different from a host processor. In such configurations, processing module 200 can receive data for processing (e.g., DMA write), and transfer processed data out (e.g., DMA read) without consuming host processor resources.

Arbiter logic 206 can arbitrate between conflicting accesses of data within processing module 200. In some embodiments, arbiter logic 206 can arbitrate between accesses by offload processor 208 and accesses external to the processor module 200. It is understood that a processing module 200 can include multiple locations that are operated on at the same time. It is understood that accesses arbitrated by arbiter logic 206 can include accesses to physical system memory space occupied by the processor module 200, as well as accesses to other resources (e.g., cache memory of offload or host processor). Accordingly, arbitration rules for arbiter logic 206 can vary according to application. In some embodiments, such arbitration rules are fixed for a given processor module 200. In such cases, different applications can be accommodated by switching out different processing modules. However, in alternate embodiments, such arbitration rules can be configurable.

Offload processor 208 can include one or more processors that can operate on data transferred over the system memory bus. In some embodiments, offload processors can run a general operating system or server applications such as Apache (as but one very particular example), enabling processor contexts to be saved and retrieved. Computing tasks executed by offload processor 208 can be handled by the hardware scheduler. Offload processors 208 can operate on data buffered in the processor module 200. In addition or alternatively, offload processors 208 can access data stored elsewhere in a system memory space. In some embodiments, offload processors 208 can include a cache memory configured to store context information. An offload processor 208 can include multiple cores or one core.

A processor module 200 can be included in a system having a host processor (not shown). In some embodiments, offload processors 208 can be a different type of processor as compared to the host processor. In particular embodiments, offload processors 208 can consume less power and/or have less computing power than a host processor. In very particular embodiments, offload processors 208 can be “wimpy” core processors, while a host processor can be a “brawny” core processor. However, in alternate embodiments, offload processors 208 can have equivalent computing power to any host processor. In very particular embodiments, a host processor can be an x86 type processor, while an offload processor 208 can include an ARM, ARC, Tensilica, MIPS, Strong/ARM, or RISC type processor, as but a few examples.

Local memory 210 can be connected to offload processor 208 to enable the storing of context information. Accordingly, an offload processor 208 can store current context information, and then switch to a new computing task, then subsequently retrieve the context information to resume the prior task. In very particular embodiments, local memory 210 can be a low latency memory with respect to other memories in a system. In some embodiments, storing of context information can include copying an offload processor 208 cache.

In some embodiments, a same space within local memory 210 is accessible by multiple offload processors 208 of the same type. In this way, a context stored by one offload processor can be resumed by a different offload processor.

Control logic 212 can control processing tasks executed by offload processor(s). In some embodiments, control logic 212 can be considered a hardware scheduler that can be conceptualized as including a data evaluator 214, scheduler 216 and a switch controller 218. A data evaluator 214 can extract “metadata” from write data transferred over a system memory bus. “Metadata”, as used herein, can be any information embedded at one or more predetermined locations of a block of write data that indicates processing to be performed on all or a portion of the block of write data and/or indicate a particular task/process to which the data belongs (e.g., classification data). In some embodiments, metadata can be data that indicates a higher level organization for the block of write data. As but one very particular embodiment, metadata can be header information of one or more network packets (which may or may not be encapsulated within a higher layer packet structure).

A scheduler 216 (e.g., a hardware scheduler) can order computing tasks for offload processor(s) 208. In some embodiments, scheduler 216 can generate a schedule that is continually updated as write data for processing is received. In very particular embodiments, a scheduler 216 can generate such a schedule based on the ability to switch contexts of offload processor(s) 208. In this way, on-module computing priorities can be adjusted on the fly. In very particular embodiments, a scheduler 216 can assign a portion of physical address space (e.g., memory locations within local memory 210) to an offload processor 208, according to computing tasks. The offload processor 208 can then switch between such different spaces, saving context information prior to each switch, and subsequently restoring context information when returning to the memory space.

Switch controller 218 can control computing operations of offload processor(s) 208. In particular embodiments, according to scheduler 216, switch controller 218 can order offload processor(s) 208 to switch contexts. It is understood that a context switch operation can be an “atomic” operation, executed in response to a single command from switch controller 218. In addition or alternatively, a switch controller 218 can issue an instruction set that stores current context information, recalls context information, etc.

In some embodiments, processor module 200 can include a buffer memory (not shown). A buffer memory can store received write data on board the processor module. A buffer memory can be implemented on an entirely different set of memory devices, or can be a memory embedded with logic and/or the offload processor. In the latter case, arbiter logic 206 can arbitrate access to the buffer memory. In some embodiments, a buffer memory can correspond to a portion of a system physical memory space. The remaining portion of the system memory space can correspond to other like processor modules and/or memory modules connected to the same system memory bus. In some embodiments buffer memory can be different than local memory 210. For example, buffer memory can have a slower access time than local memory 210. However, in other embodiments, buffer memory and local memory can be implemented with like memory devices.

In very particular embodiments, write data for processing can have an expected maximum flow rate. A processor module 200 can be configured to operate on such data at, or faster than, such a flow rate. In this way, a master device (not shown) can write data to a processor module without danger of overwriting data “in process”.

The various computing elements of a processor module 200 can be implemented as one or more integrated circuit devices (ICs). It is understood that the various components shown in FIG. 2-0 can be formed in the same or different ICs. For example, control logic 212, memory interface 214, and/or arbiter logic 206 can be implemented on one or more logic ICs, while offload processor(s) 208 and local memory 210 are separate ICs. Logic ICs can be fixed logic (e.g., application specific ICs), programmable logic (e.g., field programmable gate arrays, FPGAs), or combinations thereof.

Advantageously, the foregoing hardware and systems can provide improved computational performance as compared to traditional computing systems. Conventional systems, including those based on x86 processors, are often ill-equipped to handle such high volume applications. Even idling, x86 processors use a significant amount of power, and near continuous operation for high bandwidth packet analysis or other high volume processing tasks makes the processor energy costs one of the dominant price factors.

In addition, conventional systems can have issues with the high cost of context switching wherein a host processor is required to execute instructions which can include switching from one thread to another. Such a switch can require storing and recalling the context for the thread. If such context data is resident in a host cache memory, such a context switch can occur relatively quickly. However, if such context data is no longer in cache memory (i.e., a cache miss), the data must be recalled from system memory, which can incur a multi-cycle latency. Continuous cache misses during context switching can adversely impact system performance.

FIG. 2-1 shows a processor module 200-1 according to one very particular embodiment which is capable of reducing issues associated with high volume processing or context switching associated with many conventional server systems. A processor module 200-1 can include ICs 220-0/1 mounted to a printed circuit board (PCB) type substrate 222. PCB type substrate 222 can include in-line module connector 202, which in one very particular embodiment, can be a DIMM compatible connector. IC 220-0 can be a system-on-chip (SoC) type device, integrating multiple functions. In the very particular embodiment shown, an IC 220-0 can include embedded processor(s), logic and memory. Such embedded processor(s) can be offload processor(s) 208 as described herein, or equivalents. Such logic can be any of controller logic 212, memory interface 204 and/or arbiter logic 206, as described herein, or equivalents. Such memory can be any of local memory 210, cache memory for offload processor(s) 208, or buffer memory, as described herein, or equivalents. Logic IC 220-1 can provide logic functions not included IC 220-0.

FIG. 2-2 shows a processor module 200-2 according to another very particular embodiment. A processor module 200-2 can include ICs 220-2, -3, -4, -5 mounted to a PCB type substrate 222, like that of FIG. 2-1. However, unlike FIG. 2-1, processor module functions are distributed among single purpose type ICs. IC 220-2 can be a processor IC, which can be an offload processor 208. IC 220-3 can be a memory IC which can include local memory 210, buffer memory, or combinations thereof. IC 220-4 can be a logic IC which can include control logic 212, and in one very particular embodiment, can be an FPGA. IC 220-5 can be another logic IC which can include memory interface 204 and arbiter logic 206, and in one very particular embodiment, can also be an FPGA.

It is understood that FIGS. 2-1/2 represent but two of various implementations. The various functions of a processor module can be distributed over any suitable number of ICs, including a single SoC type IC.

FIG. 2-3 shows an opposing side of a processor module 200-1 or 200-2 according to a very particular embodiment. Processor module 200-3 can include a number of memory ICs, one shown as 220-6, mounted to a PCB type substrate 222, like that of FIG. 2-1. It is understood that various processing and logic components can be mounted on an opposing side to that shown. A memory IC 220-6 can be configured to represent a portion of the physical memory space of a system. Memory ICs 220-6 can perform any or all of the following functions: operate independently of other processor module components, providing system memory accessed in a conventional fashion; serve as buffer memory, storing write data that can be processed with other processor module components, or serve as local memory for storing processor context information.

FIG. 2-4 shows a conventional DIMM module (i.e., it serves only a memory function) that can populate a memory bus along with processor modules as described herein, or equivalents.

FIG. 2-5 shows a system 230 according to one embodiment. A system 230 can include a system memory bus 228 accessible via multiple in-line module slots (one shown as 226). According to embodiments, any or all of the slots 226 can be occupied by a processor module 200 as described herein, or an equivalent. In the event all slots 226 are not occupied by a processor module 200, available slots can be occupied by conventional in-line memory modules 224. In a very particular embodiment, slots 226 can be DIMM slots.

In some embodiments, a processor module 200 can occupy one slot. However, in other embodiments, a processor module can occupy multiple slots.

In some embodiments, a system memory bus 228 can be further interfaced with one or more host processors and/or input/output device (not shown).

Having described processor modules according to various embodiments, operations of an offload processor module capable of interfacing with server or similar system via a memory bus and according to a particular embodiment will now be described.

FIG. 3 shows a system 301 according to another embodiment. A system 301 can transport packet data requiring network overlay services to one or more computational units (one shown as 300) located on a module, which in particular embodiments, can include a connector compatible with an existing memory module. In some embodiments, a computational unit 300 can include a processor module as described in embodiments herein, or an equivalent. A computational unit 300 can be capable of intercepting or otherwise accessing packets sent over a memory bus 316 and carrying out processing on such packets, including but not limited to termination or metadata processing. A system memory bus 316 can be a system memory bus like those described herein, or equivalents (e.g., 228).

Referring still to FIG. 3, a system 301 can include an I/O device 302 which can receive packet or other I/O data from an external source. In some embodiments I/O device 302 can include physical or virtual functions generated by the physical device to receive a packet or other I/O data from the network or another computer or virtual machine. In the very particular embodiment shown, an I/O device 302 can include a network interface card (NIC) having input buffer 302a (e.g., DMA ring buffer) and an I/O virtualization function 302b.

According to embodiments, an I/O device 302 can write a descriptor including details of the necessary memory operation for the packet (i.e. read/write, source/destination). Such a descriptor can be assigned a virtual memory location (e.g., by an operating system of the system 301). I/O device 302 then communicates with an input output memory management unit (IOMMU) 304 which can translate virtual addresses to corresponding physical addresses with an IOMMU function 304b. In the particular embodiment shown, a translation look-aside buffer (TLB) 304a can be used for such translation. Virtual function reads or writes data between I/O device and system memory locations can then be executed with a direct memory transfer (e.g., DMA) via a memory controller 306b of the system 301. An I/O device 302 can be connected to IOMMU 304 by a host bus 312. In one very particular embodiment, a host bus 312 can be a peripheral interconnect (PCI) type bus. IOMMU 304 can be connected to a host processing section 306 at a central processing unit I/O (CPUIO) 306a. In the embodiment shown, such a connection 314 can support a HyperTransport (HT) protocol.

In the embodiment shown, a host processing section 306 can include the CPUIO 306a, memory controller 306b, processing core 306c and corresponding provisioning agent 306d.

In particular embodiments, a computational unit 300 can interface with the system bus 316 via standard in-line module connection, which in very particular embodiments can include a DIMM type slot. In the embodiment shown, a memory bus 316 can be a DDR3 type memory bus. Alternate embodiments can include any suitable system memory bus. Packet data can be sent by memory controller 306b via memory bus 316 to a DMA slave interface 310a. DMA slave interface 310a can be adapted to receive encapsulated read/write instructions from a DMA write over the memory bus 316.

A hardware scheduler (308b/c/d/e/h) can perform traffic management on incoming packets by categorizing them according to flow using session metadata. Packets can be queued for output in an onboard memory (310b/308a/308m) based on session priority. When the hardware scheduler determines that a packet for a particular session is ready to be processed by the offload processor 308i, the onboard memory is signaled for a context switch to that session. Utilizing this method of prioritization, context switching overhead can be reduced, as compared to conventional approaches. That is, a hardware scheduler can handle context switching decisions and thus optimize the performance of the downstream resource (e.g., offload processor 308i).

As noted above, in very particular embodiments, an offload processor 308i can be a “wimpy core” type processor. According to some embodiments, a host processor 306c can be a “brawny core” type processor (e.g., an x86 or any other processor capable of handling “heavy touch” computational operations). While an I/O device 302 can be configured to trigger host processor interrupts in response to incoming packets, according to embodiments, such interrupts can be disabled, thereby reducing processing overhead for the host processor 306c. In some very particular embodiments, an offload processor 308i can include an ARM, ARC, Tensilica, MIPS, Strong/ARM or any other processor capable of handling “light touch” operations. Preferably, an offload processor can run a general purpose operating system for executing a plurality of sessions, which can be optimized to work in conjunction with the hardware scheduler in order to reduce context switching overhead.

Referring still to FIG. 3, in operation, a system 301 can receive packets from an external network over a network interface. The packets are destined for either a host processor 306c or an offload processor 308i based on the classification logic and schematics employed by I/O device 302. In particular embodiments, I/O device 302 can operate as a virtualized NIC, with packets for a particular logical network or to a certain virtual MAC (VMAC) address can be directed into separate queues and sent over to the destination logical entity. Such an arrangement can transfer packets to different entities. In some embodiments, each such entity can have a virtual driver, a virtual device model that it uses to communicate with connected virtual network.

According to embodiments, multiple devices can be used to redirect traffic to specific memory addresses. So, each of the network devices operates as if it is transferring the packets to the memory location of a logical entity. However, in reality, such packets are transferred to memory addresses where they can be handled by one or more offload processors (e.g., 308i). In particular embodiments such transfers are to physical memory addresses, thus logical entities can be removed from the processing, and a host processor can be free from such packet handling.

Accordingly, embodiments can be conceptualized as providing a memory “black box” to which specific network data can be fed. Such a memory black box can handle the data (e.g., process it) and respond back when such data is requested.

Referring still to FIG. 3, according to some embodiments, I/O device 302 can receive data packets from a network or from a computing device. The data packets can have certain characteristics, including transport protocol number, source and destination port numbers, source and destination IP addresses, for example. The data packets can further have metadata that is processed (308d) that helps in their classification and management.

I/O device 302 can include, but is not limited to, peripheral component interconnect (PCI) and/or PCI express (PCIe) devices connecting with a host motherboard via PCI or PCIe bus (e.g., 312). Examples of I/O devices include a network interface controller (NIC), a host bus adapter, a converged network adapter, an ATM network interface, etc.

In order to provide for an abstraction scheme that allows multiple logical entities to access the same I/O device 302, the I/O device may be virtualized to provide for multiple virtual devices each of which can perform some of the functions of the physical I/O device. The IO virtualization program (e.g., 302b) according to an embodiment, can redirect traffic to different memory locations (and thus to different offload processors attached to modules on a memory bus). To achieve this, an I/O device 302 (e.g., a network card) may be partitioned into several function parts; including controlling function (CF) supporting input/output virtualization (IOV) architecture (e.g., single-root IOV) and multiple virtual function (VF) interfaces. Each virtual function interface may be provided with resources during runtime for dedicated usage. Examples of the CF and VF may include the physical function and virtual functions under schemes such as Single Root I/O Virtualization or Multi-Root I/O Virtualization architecture. The CF acts as the physical resources that sets up and manages virtual resources. The CF is also capable of acting as a full-fledged IO device. The VF is responsible for providing an abstraction of a virtual device for communication with multiple logical entities/multiple memory regions.

The operating system/the hypervisor/any of the virtual machines/user code running on a host processor 306c may be loaded with a device model, a VF driver and a driver for a CF. The device model may be used to create an emulation of a physical device for the host processor 306c to recognize each of the multiple VFs that are created. The device model may be replicated multiple times to give the impression to a VF driver (a driver that interacts with a virtual IO device) that it is interacting with a physical device of a particular type.

For example, a certain device module may be used to emulate a network adapter such as the Intel® Ethernet Converged Network Adapter(CNA) X540-T2, so that the I/O device 302 believes it is interacting with such an adapter. In such a case, each of the virtual functions may have the capability to support the functions of the above said CNA, i.e., each of the Physical Functions should be able to support such functionality. The device model and the VF driver can be run in either privileged or non-privileged mode. In some embodiments, there is no restriction with regard to who hosts/runs the code corresponding to the device model and the VF driver. The code, however, has the capability to create multiple copies of device model and VF driver so as to enable multiple copies of said I/O interface to be created.

An application or provisioning agent 306d, as part of an application/user level code running in a kernel, may create a virtual I/O address space for each VF, during runtime and allocate part of the physical address space to it. For example, if an application handling the VF driver instructs it to read or write packets from or to memory addresses 0xaaaa to 0xffff, the device driver may write I/O descriptors into a descriptor queue with a head and tail pointer that are changed dynamically as queue entries are filled. The data structure may be of another type as well, including but not limited to a ring structure 302a or hash table.

The VF can read from or write data to the address location pointed to by the driver. Further, on completing the transfer of data to the address space allocated to the driver, interrupts, which are usually triggered to the host processor to handle said network packets, can be disabled. Allocating a specific I/O space to a device can include allocating said IO space a specific physical memory space occupied.

In another embodiment, the descriptor may comprise only a write operation, if the descriptor is associated with a specific data structure for handling incoming packets. Further, the descriptor for each of the entries in the incoming data structure may be constant so as to redirect all data write to a specific memory location. In an alternate embodiment, the descriptor for consecutive entries may point to consecutive entries in memory so as to direct incoming packets to consecutive memory locations.

Alternatively, said operating system may create a defined physical address space for an application supporting the VF drivers and allocate a virtual memory address space to the application or provisioning agent 306d, thereby creating a mapping for each virtual function between said virtual address and a physical address space. Said mapping between virtual memory address space and physical memory space may be stored in IOMMU tables (e.g., a TLB 304a). The application performing memory reads or writes may supply virtual addresses to say virtual function, and the host processor OS may allocate a specific part of the physical memory location to such an application.

Alternatively, VF may be configured to generate requests such as read and write which may be part of a direct memory access (DMA) read or write operation, for example. The virtual addresses is be translated by the IOMMU 304 to their corresponding physical addresses and the physical addresses may be provided to the memory controller for access. That is, the IOMMU 304 may modify the memory requests sourced by the I/O devices to change the virtual address in the request to a physical address, and the memory request may be forwarded to the memory controller for memory access. The memory request may be forwarded over a bus 314 that supports a protocol such as HyperTransport 314. The VF may in such cases carry out a direct memory access by supplying the virtual memory address to the IOMMU 304.

Alternatively, said application may directly code the physical address into the VF descriptors if the VF allows for it. If the VF cannot support physical addresses of the form used by the host processor 306c, an aperture with a hardware size supported by the VF device may be coded into the descriptor so that the VF is informed of the target hardware address of the device. Data that is transferred to an aperture may be mapped by a translation table to a defined physical address space in the system memory. The DMA operations may be initiated by software executed by the processors, programming the I/O devices directly or indirectly to perform the DMA operations.

Referring still to FIG. 3, in particular embodiments, parts of computational unit 300 can be implemented with one or more FPGAs. In the system of FIG. 3, computational unit 300 can include FPGA 310 in which can be formed a DMA slave device module 310a and arbiter 310f. A DMA slave module 310a can be any device suitable for attachment to a memory bus 316 that can respond to DMA read/write requests. In alternate embodiments, a DMA slave module 310a can be another interface capable of block data transfers over memory bus 316. The DMA slave module 310a can be capable of receiving data from a DMA controller (when it performs a read from a ‘memory’ or from a peripheral) or transferring data to a DMA controller (when it performs a write instruction on the DMA slave module 310a). The DMA slave module 310a may be adapted to receive DMA read and write instructions encapsulated over a memory bus, (e.g., in the form of a DDR data transmission, such as a packet or data burst), or any other format that can be sent over the corresponding memory bus.

A DMA slave module 310a can reconstruct the DMA read/write instruction from the memory R/W packet. The DMA slave module 310a may be adapted to respond to these instructions in the form of data reads/data writes to the DMA master, which could either be housed in a peripheral device, in the case of a PCIe bus, or a system DMA controller in the case of an ISA bus.

I/O data that is received by the DMA device 310a can then queued for arbitration. Arbitration can include the process of scheduling packets of different flows, such that they are provided access to available bandwidth based on a number of parameters. In general, an arbiter 310f provides resource access to one or more requestors. If multiple requestors request access, an arbiter 310f can determine which requestor becomes the accessor and then passes data from the accessor to the resource interface, and the downstream resource can begin execution on the data. After the data has been completely transferred to a resource, and the resource has competed execution, the arbiter 310f can transfer control to a different requestor and this cycle repeats for all available requestors. In the embodiment of FIG. 3 arbiter 310f can notify other portions of computational unit 300 (e.g., 308) of incoming data.

Alternatively, a computation unit 300 can utilize an arbitration scheme shown in U.S. Pat. No. 7,813,283, issued to Dalal on Oct. 12, 2010, the contents of which are incorporated herein by reference. Other suitable arbitration schemes known in art could be implemented in embodiments herein. Alternatively, the arbitration scheme of the current invention might be implemented using an OpenFlow switch and an OpenFlow controller.

In the very particular embodiment of FIG. 3, computational unit 300 can further include notify/prefetch circuits 310c which can prefetch data stored in a buffer memory 310b in response to DMA slave module 310a, and as arbitrated by arbiter 310f. Further, arbiter 310f can access other portions of the computational unit 300 via a memory mapped I/O ingress path 310e and egress path 310g.

Referring to FIG. 3, a hardware scheduler can include a scheduling circuit 308b/n to implement traffic management of incoming packets. Packets from a certain source, relating to a certain traffic class, pertaining to a specific application or flowing to a certain socket are referred to as part of a session flow and are classified using session metadata. Such classification can be performed by classifier 308e.

In some embodiments, session metadata 308d can serve as the criterion by which packets are prioritized and scheduled and as such, incoming packets can be reordered based on their session metadata. This reordering of packets can occur in one or more buffers and can modify the traffic shape of these flows. The scheduling discipline chosen for this prioritization, or traffic management (TM), can affect the traffic shape of flows and micro-flows through delay (buffering), bursting of traffic (buffering and bursting), smoothing of traffic (buffering and rate-limiting flows), dropping traffic (choosing data to discard so as to avoid exhausting the buffer), delay jitter (temporally shifting cells of a flow by different amounts) and by not admitting a connection (e.g., cannot simultaneously guarantee existing service level agreements (SLAs) with an additional flow's SLA).

According to embodiments, computational unit 300 can serve as part of a switch fabric, and provide traffic management with depth-limited output queues, the access to which is arbitrated by a scheduling circuit 308b/n. Such output queues are managed using a scheduling discipline to provide traffic management for incoming flows. The session flows queued in each of these queues can be sent out through an output port to a downstream network element.

It is noted that conventional traffic management do not take into account the handling and management of data by downstream elements except for meeting the SLA agreements it already has with said downstream elements.

In contrast, according to embodiments a scheduler circuit 308b/n can allocate a priority to each of the output queues and carry out reordering of incoming packets to maintain persistence of session flows in these queues. A scheduler circuit 308b/n can be used to control the scheduling of each of these persistent sessions into a general purpose operating system (OS) 308j, executed on an offload processor 308i. Packets of a particular session flow, as defined above, can belong to a particular queue. The scheduler circuit 308b/n may control the prioritization of these queues such that they are arbitrated for handling by a general purpose (GP) processing resource (e.g., offload processor 308i) located downstream. An OS 308j running on a downstream processor 308i can allocate execution resources such as processor cycles and memory to a particular queue it is currently handling. The OS 308j may further allocate a thread or a group of threads for that particular queue, so that it is handled distinctly by the general purpose processing element 308i as a separate entity. The fact that there can be multiple sessions running on a GP processing resource, each handling data from a particular session flow resident in a queue established by the scheduler circuit, tightly integrates the scheduler and the downstream resource (e.g., 308i). This can bring about persistence of session information across the traffic management and scheduling circuit and the general purpose processing resource 308i.

Dedicated computing resources (e.g., 308i), memory space and session context information for each of the sessions can provide a way of handling, processing and/or terminating each of the session flows at the general purpose processor 308i. The scheduler circuit 308b/n can exploit this functionality of the execution resource to queue session flows for scheduling downstream. The scheduler circuit 308b/n can be informed of the state of the execution resource(s) (e.g., 308i), the current session that is run on the execution resource; the memory space allocated to it, the location of the session context in the processor cache.

According to embodiments, a scheduler circuit 308b/n can further include switching circuits to change execution resources from one state to another. The scheduler circuit 308b/n can use such a capability to arbitrate between the queues that are ready to be switched into the downstream execution resource. Further, the downstream execution resource can be optimized to reduce the penalty and overhead associated with context switch between resources. This is further exploited by the scheduler circuit 308b/n to carry out seamless switching between queues, and consequently their execution as different sessions by the execution resource.

According to embodiments, a scheduler circuit 308b/n can schedule different sessions on a downstream processing resource, wherein the two are operated in coordination to reduce the overhead during context switches. An important factor in decreasing the latency of services and engineering computational availability can be hardware context switching synchronized with network queuing. In embodiments, when a queue is selected by a traffic manager, a pipeline coordinates swapping in of the cache (e.g., L2 cache) of the corresponding resource (e.g., 308i) and transfers the reassembled I/O data into the memory space of the executing process. In certain cases, no packets are pending in the queue, but computation is still pending to service previous packets. Once this process makes a memory reference outside of the data swapped, the scheduler circuit (308b/n) can enable queued data from an I/O device 302 to continue scheduling the thread.

In some embodiments, to provide fair queuing to a process not having data, a maximum context size can be assumed as data processed. In this way, a queue can be provisioned as the greater of computational resource and network bandwidth resource. As but one very particular example, a computation resource can be an ARM A9 processor running at 800 MHz, while a network bandwidth can be 3 Gbps of bandwidth. Given the lopsided nature of this ratio, embodiments can utilize computation having many parallel sessions (such that the hardware's prefetching of session-specific data offloads a large portion of the host processor load) and having minimal general purpose processing of data.

Accordingly, in some embodiments, a scheduler circuit 308b/n can be conceptualized as arbitrating, not between outgoing queues at line rate speeds, but arbitrating between terminated sessions at very high speeds. The stickiness of sessions across a pipeline of stages, including a general purpose OS, can be a scheduler circuit optimizing any or all such stages of such a pipeline.

Alternatively, a scheduling scheme can be used as shown in U.S. Pat. No. 7,760,715 issued to Dalal on Jul. 20, 2010, incorporated herein by reference. This scheme can be useful when it is desirable to rate limit the flows for preventing the downstream congestion of another resource specific to the over-selected flow, or for enforcing service contracts for particular flows. Embodiments can include arbitration scheme that allows for service contracts of downstream resources, such as general purpose OS that can be enforced seamlessly.

Referring still to FIG. 3, a hardware scheduler according to embodiments herein, or equivalents, can provide for the classification of incoming packet data into session flows based on session metadata. It can further provide for traffic management of these flows before they are arbitrated and queued as distinct processing entities on the offload processors.

In some embodiments, offload processors (e.g., 308i) can be general purpose processing units capable of handling packets of different application or transport sessions. Such offload processors can be low power processors capable of executing general purpose instructions. The offload processors could be any suitable processor, including but not limited to: ARM, ARC, Tensilica, MIPS, StrongARM or any other processor that serves the functions described herein. Such offload processors have a general purpose OS running on them, wherein the general purpose OS is optimized to reduce the penalty associated with context switching between different threads or group of threads.

In contrast, context switches on host processors can be computationally intensive processes that require the register save area, process context in the cache and TLB entries to be restored if they are invalidated or overwritten. Instruction Cache misses in host processing systems can lead to pipeline stalls and data cache misses lead to operation stall and such cache misses reduce processor efficiency and increase processor overhead.

In contrast, an OS 308j running on the offload processors 308i in association with a scheduler circuit 308b/n, can operate together to reduce the context switch overhead incurred between different processing entities running on it. Embodiments can include a cooperative mechanism between a scheduler circuit and the OS on the offload processor 308i, wherein the OS sets up session context to be physically contiguous (physically colored allocator for session heap and stack) in the cache; then communicates the session color, size, and starting physical address to the scheduler circuit upon session initialization. During an actual context switch, a scheduler circuit can identify the session context in the cache by using these parameters and initiate a bulk transfer of these contents to an external low latency memory (e.g., 308g). In addition, the scheduler circuit can manage the prefetch of the old session if its context was saved to a local memory 308g. In particular embodiments, a local memory 308g can be low latency memory, such as a reduced latency dynamic random access memory (RLDRAM), as but one very particular embodiment. Thus, in embodiments, session context can be identified distinctly in the cache.

In some embodiments, context size can be limited to ensure fast switching speeds. In addition or alternatively, embodiments can include a bulk transfer mechanism to transfer out session context to a local memory 308g. The cache contents stored therein can then be retrieved and prefetched during context switch back to a previous session. Different context session data can be tagged and/or identified within the local memory 308g for fast retrieval. As noted above, context stored by one offload processor may be recalled by a different offload processor.

In the very particular embodiment of FIG. 3, multiple offload processing cores can be integrated into a computation FPGA 308. Multiple computational FPGAs can be arbitrated by arbitrator circuits in another FPGA 310. The combination of computational FPGAs (e.g., 308) and arbiter FPGAs (e.g., 310) are referred to as “XIMM” modules or “Xockets DIMM modules” (e.g., computation unit 300). In particular applications, these XIMM modules can provide integrated traffic and thread management circuits that broker execution of multiple sessions on the offload processors.

FIG. 3 also shows an offload processor tunnel connection 308k, as well as a memory interface 308m and port 3081 (which can be an accelerator coherency port (ACP)). Memory interface 308m can access buffer memory 308a.

Having described various embodiments suitable for hardware scheduling and traffic management operations, an example illustrating particular aspects will now be described.

FIG. 4 illustrates an example embodiment of a scheduling process 400 for access to offload processing resources according to a very particular embodiment. In some embodiments, a scheduler (e.g., hardware scheduler) can implement a scheduling process as a traffic management scheme in order to meet the requirements of offload processors, and may be operated in a preemption mode. In a preemption mode, the scheduler can be responsible for controlling the execution of a session on the OS. The scheduler can decide when to remove a current session from execution and cause another session to be executed. A session may comprise of a thread or a group of threads on an offload processor. Depending on a number of parameters, including such factors as the characteristics of the current session—whether it is stalled or running or waiting for a packet, the amount of execution resources allocated to the session, and factors such as time allocated to the current session, the hardware scheduler may make a context switching decision. When a packet arrives at the hardware scheduler, and based on meeting any of the above said criteria, the scheduler may decide to context switch if the packet is for a different session.

As seen in FIG. 4, a method 400 can wait for packets or other data (402). Incoming packets can be received by a monitor buffer, queue or file. Once a packet or service level specification (SLS) has been received, there may be a check to ensure other conditions are met (406). If the packet/data has arrived (and optionally, other conditions met, such as those noted above) (Yes from 406), a packet session status is determined (408). If the packet is part of a current session (Yes from 408), it can be queued for the current session (412) and processed as part of the current session (410). In some embodiments, this can include hardware scheduler queuing the packet and sending it to an offload processor for processing.

If a packet is not part of a current session (No from 408), it can be determined if the packet is for a previous session (414). If the packet is not from a previous session (No from 414), it can be determined if there is enough memory for a new session (416). If there is enough memory (Yes from 416), when the offload processor(s) is ready (428), the transfer of context data can be made to the cache memory of the processor(s) (430). Once such a transfer is complete, the session can run (410).

If the packet is from a previous session (Yes from 414) or there is not enough memory for a new session (No from 416), it can be determined if the previous session or new session is of the same color (418). If this is not the case, a switch can be made to the previous session or new session (420). A least recently uses (LRU) cache entity can be flushed, and the previous session context can be retrieved, or the new session context created. The packets of this retrieved/new session can be assigned a new color which can be retained. In some embodiments, this can include reading context data stored in a low latency memory to the cache of an offload processor. If a previous/new session is of the same color (Yes from 418), a check can be made to see if the color pressure can be exceeded (422). If this is not possible, but another color is available (“No, other color available” from 422), a switch to the previous or new session can be made (i.e., 420). If the color pressure can be excluded, or it cannot, but no other color is available (“Yes/No, other color unavail.”), an LRU cache entity of the same color can be flushed, and the previous session context can be retrieved, or the new session context created (424). These packets will retain their assigned color. Again, in some embodiments, this can include reading context data stored in a low latency memory to the cache of an offload processor.

In the event of a context switch (420/424), the new session can be initialized (426). When the offload processor(s) are ready (428), the transfer of context data can be made to the cache memory of the processor(s) (430). Once such a transfer is complete, the session can run (410).

Referring still to FIG. 4, While the offload processor is processing a packet (410), there is a periodic check to see if the packet has finished processing (432) and return if processing is not done (No, dequeue packets from 432). If the packet is done (Yes from 432), a hardware scheduler can looks to its output queue for more packets (434). If there are more packets (Yes from 434) and the offload processor is ready to receive them (Yes from 436), the packets can transferred to the offload processor. In some embodiments, packets can be queued into the offload processor as soon as a “ready for processing” message is triggered by the offload processor. After the offload processor is done processing the packets, the entire cycle can repeat beginning with the hardware scheduler checking to which session the packet belongs, etc.

If an offload processor is not ready for a packet (No from 436) and it is waiting for rate limit (438), the hardware scheduler can check to see if there are other packets available. If there are no more packets in the queue, the hardware scheduler can goes into a wait mode, waiting for rate limit until more packets arrive. Thus, the hardware scheduler works quickly and efficiently to manage and supply packets going to the downstream resource.

As shown, a session can be preempted by the arrival of a packet from a different session, resulting in the new packet being processed as noted above (406).

It should be appreciated that in the foregoing description of exemplary embodiments of the invention, various features of the invention are sometimes grouped together in a single embodiment, figure, or description thereof for the purpose of streamlining the disclosure aiding in the understanding of one or more of the various inventive aspects. This method of disclosure, however, is not to be interpreted as reflecting an intention that the claimed invention requires more features than are expressly recited in each claim. Rather, as the following claims reflect, inventive aspects lie in less than all features of a single foregoing disclosed embodiment. Thus, the claims following the detailed description are hereby expressly incorporated into this detailed description, with each claim standing on its own as a separate embodiment of this invention.

It is also understood that the embodiments of the invention may be practiced in the absence of an element and/or step not specifically disclosed. That is, an inventive feature of the invention may be elimination of an element.

Accordingly, while the various aspects of the particular embodiments set forth herein have been described in detail, the present invention could be subject to various changes, substitutions, and alterations without departing from the spirit and scope of the invention.

Claims

1. A scheduling system for a packet processing system, comprising: a classification circuit connected to a memory bus and configurable to classify network packets, placing the classified network packets into first multiple input/output queues,a scheduling circuit for reordering the network packets received from the classification circuit through the first multiple input/output queues and placing the reordered network packets into second multiple input/output queues,an arbitration circuit for directing network packets received from the scheduling circuit through the second multiple input/output queues to multiple output ports, andmultiple offload processors, each coupled to at least one of the multiple output ports, the offload processors configured to modify the network packets.

2. The system of claim 1 wherein the memory bus supports direct memory access, and the multiple offload processors can direct modified packets back to the memory bus.

3. The system of claim 1 wherein the classification circuit is configured to classify network packets based on session metadata.

4. The system of claim 1 wherein the scheduling circuit is configured to direct network packets based on availability of respective multiple offload processors.

5. The system of claim 1 wherein the scheduling circuit is configured to reorder network packets according to session priority.

6. The system of claim 1 wherein the scheduling circuit is configured to initiate a context switch for at least one of the multiple offload processors.

7. The system of claim 1 wherein the scheduling circuit is configured to transfer network packets into a defined traffic management queue.

8. The system of claim 1 wherein the scheduling circuit is configured to determine when network packet processing for each of the multiple offload processors is complete.

9. The system of claim 1 wherein the scheduling circuit is configured to operate in a preemption mode to control session execution.

10. A scheduling system for a packet processing system, comprising: a classification circuit connected to a memory bus and configurable to classify network packets based on session metadata, and placing the classified network packets into first multiple input/output queues,a scheduling circuit configured to reorder the network packets received from the classification circuit through the first multiple input/output queues and placing the classified network packets into second multiple input/output queues,an arbitration circuit for directing network packets received from the scheduling circuit through the second multiple input/output queues to multiple output ports, andmultiple offload processors, each coupled to one of the multiple output ports, the offload processors configured to modify network packets and direct the modified packets to the memory bus.

11. The system of claim 10 wherein the scheduling circuit is configured to direct network packets based on availability of respective multiple offload processors.

12. The system of claim 10 wherein the scheduling circuit is configured to reorder network packets according to session priority of the network packets.

13. The system of claim 10 wherein the scheduling circuit is configured to initiate a context switch for at least one of the multiple offload processors.

14. The system of claim 10 wherein the scheduling circuit is configured to transfer network packets into a defined traffic management queue.

15. The system of claim 10 wherein the scheduling circuit is configured to determine when network packet processing for each of the multiple offload processors is complete.

16. The system of claim 10 wherein the scheduling circuit is configured to operate in a preemption mode to control session execution.