Claims
- 1. In a method of depositing silicon containing insulating material on conductive lines on a substrate separated by a gaps, with at least one pair of said conductive lines having a narrow gap of about 0.5 microns or less and an aspect ratio of 2 to 1 or greater, comprising the steps of:
- depositing silicon containing insulating material on and between the conductive lines;
- masking the insulation over the conductive lines in all but those areas having the conductive lines with the narrow gap of about 0.5 microns or less;
- removing the insulating material above and in said narrow gap; and
- depositing a nonconformal silicon containing insulating material on the conductive lines adjacent said narrow gap under conditions to provide a poor step coverage between the bottom of the gaps and the top of the conductive lines so that the material forms shoulders on top of the conductive lines and bridges across the narrow gaps, thereby forming a relatively large void in said narrow gap having an effective dielectric constant of less than about 3 and covered by a nonconformal silicon insulating layer.
- 2. The method of claim 1 wherein said insulating material above and in the narrow gap is removed by plasma etching.
- 3. The method of claim 2 wherein the insulating material is an oxide of silicon and the plasma contains fluorine ions.
- 4. The method of claim 2 wherein said plasma etching is anisotropic.
- 5. The method of claim 1 wherein the conductive lines are either aluminum or an aluminum alloy and a thin layer of not greater than 500 .ANG. is deposited before the nonconformal insulating material is deposited.
- 6. The method of claim 1 wherein the silicon source of the nonconformal insulating material is silane.
- 7. The method of claim 1 wherein the initial step coverage is less than 50%.
- 8. The method of claim 1 wherein, during the formation of the void, the step coverage is not greater than 20%.
- 9. The method of claim 1 wherein said relative large void is at least one-third of the volume in the narrow gap.
CROSS REFERENCES TO RELATED APPLICATIONS
This is a Divisional of Ser. No. 08/481,030 filed on Jun. 7, 1995, now U.S. Pat. No. 5,691,573. This application is related to U.S. patent application Ser. No. 08/478,315, entitled BIAS PLASMA DEPOSITION FOR SELECTIVE LOW DIELECTRIC INSULATION, filed on an even date herewith; and U.S. patent application Ser. No. 08/481,906, entitled UNIFORM NONCONFORMAL DEPOSITION FOR FORMING LOW DIELECTRIC CONSTANT INSULATION BETWEEN CERTAIN CONDUCTIVE LINES, also filed on an even date herewith.
US Referenced Citations (8)
Divisions (1)
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Number |
Date |
Country |
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481030 |
Jun 1995 |
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