Patent Application
20250105053
In semiconductor manufacturing, layer transfer techniques are used to transfer a layer from one substrate to another, typically at wafer-level scale. These techniques require a full layer to be transferred in its entirety regardless of whether the entire layer is needed. As a result, any unneeded portions of a transferred layer must be etched off after the transfer, which increases costs and process complexity.
In semiconductor manufacturing, layer transfer techniques are used to transfer a layer from one substrate to another, typically at wafer-level scale. Layer transfers are useful for a variety of applications in semiconductor manufacturing, including two-dimensional (2D) material fabrication, Group III-V semiconductors over complementary metal-oxide semiconductors (CMOS), and traditional CMOS applications such as metal-insulator-metal (MIM) devices and thin device and/or interconnect layer transfers. Current layer transfer techniques are limited to full layer transfers, however, which may impact cost and performance when the full layer is not needed. For example, blanket layer transfer techniques, such as ion-cut and laser debonding layer transfers, require a full layer to be transferred in its entirety. As a result, any unneeded areas of the transferred layer must be etched off after the transfer, which results in added cost and process complexity.
Alternatively, pick-and-place techniques can be used to transfer specific dies or chiplets. For example, a chiplet generally refers to an integrated circuit (IC) that contains a well-defined subset of functionality, which is designed to be combined with other chiplets to form a single IC package. To transfer chiplets (e.g., for MIM chiplet integration in a system-on-a-chip (SoC)), chiplet devices are fabricated on a donor substrate (e.g., a wafer or panel), the donor substrate is singulated into chiplets, and the chiplets are then individually attached to a receiver substrate (e.g., an SoC wafer or package) using pick-and-place machines. This adds significant cost due to the extra processing required to singulate the wafer and individually attach the respective chiplet dies. For example, chiplets are generally manufactured on relatively thick substrates to enable them to be handled during the singulation and attach steps without being damaged, and after the attach step, additional processing is performed to thin the chiplets and/or remove the carrier substrate, which further increases the cost and process complexity. In particular, chiplets are typically manufactured on substrates that are over 700 micrometers (μm or microns) thick to provide structural and mechanical stability during fabrication, and after the singulation/attach steps, they may be thinned to approximately 20-100 μm by grinding the backside. However, grinding typically causes chipping along the edges of the chiplet dies. Further, it can be challenging to thin chiplets beyond 20 μm without producing defects. Similarly, chiplets are typically singulated with a die area on the millimeter level scale, as pick-and-place assembly becomes very challenging for chiplets smaller than 1 millimeter (mm) 2.
Integrated circuits can also be manufactured monolithically, where all IC components and interconnections are fabricated sequentially on the same underlying substrate or wafer. Monolithic ICs have various limitations, however, including design limitations due to incompatible processes, lack of flexibility, and low yield.
Accordingly, this disclosure presents selective layer transfer techniques for selectively transferring portions of a layer between substrates, along with devices and systems formed using the same. For example, the described techniques enable select areas of a donor substrate to be transferred to a receiver substrate, which enables the donor substrate to be reused multiple times, while also addressing the limitations described above for blanket layer transfers and pick and place techniques. In particular, the described solution uses a selective release technology on a donor substrate (e.g., wafer, panel, or die) in conjunction with a patterned bonding template on a receiver substrate (e.g., wafer, panel, or die) to allow select areas of a layer on the donor substrate to be transferred to the receiver substrate. For purposes of this disclosure, a layer may refer to one or more layers formed over a substrate, such as an individual layer of material, or a stack of layers that collectively form a layer of IC components (e.g., dies, interconnects, bridges, capacitors, and/or other semiconductor devices). A layer may also include stacked wafers, such as wafer-to-wafer bonded and stacked logic and/or memory wafers. As an example, a donor wafer may include a layer of IC components (e.g., IC dies), and a selective layer transfer may be used to selectively and simultaneously transfer a specific subset of those IC components to a receiver wafer.
The described solution provides various advantages. For example, the described solution enables select areas of a donor wafer to be transferred as opposed to an entire layer, which enables the donor wafer to be reused for multiple products, thus amortizing the cost of expensive devices (e.g., high-density MIM capacitors or high-density passive interposers) across multiple wafers. This solution also eliminates the need to etch away superfluous areas as required by full layer transfers (and as a result, unlike the etched areas after a full layer transfer, selectively transferred areas may not have tapered edges from etching or may have reversed tapering due to the etch to singulate before transfer).
Further, layers of IC components can be selectively transferred at any level of granularity, including full IC dies and packages, interconnects, transistors, resistors, capacitors, partial layers or layer stacks, etc.
This solution also enables areas of ultra-thin layers to be selectively transferred without the added processing and yield loss resulting from the handling challenges of chiplet pick-and-place methods (e.g., singulation, individually attaching each chiplet, post-attach thinning of chiplets). This helps reduce the Z-height of a product (e.g., for formfactor, thermal, and/or power delivery reasons) as well as the overall process complexity. For example, very thin IC dies or chiplets can be formed on any substrate and selectively transferred directly from that substrate. As a result, selectively transferring the dies not only eliminates the need for post-attach thinning, it also enables the dies to be much thinner than dies that are singulated, pick-and-place attached, and then subsequently thinned. In some cases, for example, the described solution may enable transfers of dies with thicknesses ranging from 100 nanometers (nm) to 5 μm or more. Further, since no post-attach thinning is needed, the selectively transferred dies may have no or minimal chipping on the die edges since no grinding is performed, unlike chiplets that are thinned after attachment.
Similarly, this solution supports selective transfers of very small areas on a donor substrate, such as very small dies or chiplets, which is extremely challenging using pick-and-place techniques. In some cases, for example, the described solution may enable transfers of dies (or other IC components) with an area less than 1 mm2, such as 100 μm2 (10×10 μm), 10,000 μm2 (100×100 μm), 810,000 μm2 (900×900 μm), etc. (with no limits on the maximum size of an area that can be selectively transferred).
This solution also supports selective transfers of dies with non-standard shapes and designs that are difficult to handle using pick-and-place machines, such as dies with atypical, arbitrary, irregular, or non-convex shapes (e.g., L shape, U shape, shapes with acute angles), dies with high aspect ratios (e.g., 8:1 aspect ratio or higher), dies with holes, and so forth.
Further, this solution has very low topography and supports high surface cleanliness and planarization (e.g., using chemical mechanical polishing (CMP) processing), which makes it compatible with hybrid bonding and fusion bonding processing. Additional advantages are described throughout this disclosure and apparent from the description below.
Accordingly, this solution enables complex IC packages and products to be manufactured by selectively transferring certain components (e.g., active circuitry such as IC dies, passive circuitry) instead of incorporating them using traditional processes, such as: (i) full layer transfers with superfluous areas etched away; (ii) pick-and-place assembly of individual IC components; and/or (iii) monolithic IC fabrication.
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The layer 104 to be selectively transferred is formed over the release layer 102 of the donor substrate 100, such as by fabricating the layer 104 directly or blanket transferring the layer 104. The selective transfer layer 104 may include one or more layers of material, such as a single layer of material or a stack of layers that collectively form a layer of IC components (e.g., full IC dies, chiplets, interconnects, bridges, capacitors, transistors, and/or other semiconductor devices). In some embodiments, for example, the selective transfer layer 104 may be a prefabricated semiconductor wafer containing unsingulated integrated circuit (IC) dies, which is blanket transferred to the release layer 102 on a donor wafer 100.
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Next, a bonding template 114 is formed on the surface of the receiver substrate 110 (e.g., above the release layer 112, if included). The bonding template 114 includes a pattern of bonding features or adhesive areas 114 that enable specific areas of the donor substrate 100 to be selectively transferred to the receiver substrate 110. For example, the positions of the bonding features 114 on the receiver substrate 110 correspond to the areas or IC components 106 on the donor substrate 100 that will be transferred to the receiver substrate 110.
In some embodiments, for example, the bonding features 114 may include “island” or “mesa” structures that are similar in size to the target areas to be transferred from the donor substrate 100. For example, each island or mesa structure 114 may be a raised structure on the surface of the receiver substrate 110 with a similar footprint (e.g., shape/surface area) as a corresponding IC component 106 on the donor substrate 100. In other embodiments, the mesas 114 may be replaced by lithographically or additively manufactured surface treatments that enhance the adhesion in the target areas of the receiver substrate 110 (e.g., the areas where the mesas 114 are shown) and prevents adhesion in the other areas, including, without limitation, surface topography variations, use of materials with high and/or low adhesion, treatments using hydrophobic materials and/or self-assembled monolayers (SAMs), and/or surface activation techniques, among other examples.
In various embodiments, these bonding features 114 may be made of dielectric materials, conductive materials (e.g., metal), or both, depending on whether electrical connections are needed between the bonded IC components 106 and the receiver substrate 110. For example, the bonding features 114 may be blanket dielectric structures with no electrical contacts, or they may be dielectric structures with electrical contacts through them (e.g., hybrid bonding pads) if electrical connections are needed through the bonding interface.
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It should be appreciated that the illustrated process flow for selective layer transfers is merely presented as an example and many other process variations are also possible. For example, the donor and receiver substrates 100, 110 may be wafers, panels, IC packages, chiplets, dies, or any combination thereof (e.g., for transfers from wafer to panel, chiplet to wafer, etc.). Moreover, each substrate 100, 110 may be made of a variety of materials, including, without limitation, inorganic materials such as silicon, silicon on insulator (SOI), quartz, glass, and/or Group III-V materials, organic materials such as IR or UV transparent epoxies, and so forth.
The materials used in the release layers 102, 112 may vary depending on the type of release or debonding technology used. For example, for infrared (IR) laser debonding, the release layers 102, 112 may include one or more materials capable of absorbing and/or reflecting infrared (IR) light, such as a thin metal layer or multiple metal layers (e.g., aluminum (Al), tungsten (W), copper (Cu), titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN)). For ultraviolet (UV) laser debonding, the release layers 102. 112 may include one or more materials capable of absorbing UV light (e.g., a wide range of organic polymers, including, but not limited to, polyimides). In some embodiments, the release layers 102, 112 may additionally or alternatively include one or more layers of dielectric materials (e.g., silicon dioxide (SiO2), silicon nitride (Si3N4), silicon oxynitride (SiON), silicon carbide (SiC), silicon carbon nitride (SiCN), silicon oxycarbon nitride (SiOCN), aluminum oxide (Al2O3), low-k dielectrics such as carbon-doped oxide (CDO) or porous silicon dioxide (SiO2), titanium dioxide (TiO2), tantalum oxide (Ta2O5)), which may be used to buffer laser ablation and thermal energy, control thin film interference or adhesion, and/or provide residual adhesion after other materials and/or layers in the release layers 102, 112 are weakened, removed, and/or ablated by a laser.
The number of layers 104 on the donor substrate 100, the arrangement/structure of the layers 104, the materials in each layer 104, and the type of IC components 106 formed in those layers 104 may vary.
The adhesive areas or bonding features 114 on the receiver substrate 110 may be formed using any suitable surface treatments or other techniques to control the level of adhesion in different areas, including, without limitation, surface topography variations (e.g., mesas, recesses), use of materials with high and/or low adhesion, treatments using hydrophobic materials and/or self-assembled monolayers (SAMs), and/or surface activation techniques, among other examples. Moreover, the bonding features or adhesive areas 114 on the receiver substrate 110 may vary in size, shape, height, topography, pattern, and materials. For example, the bonding features 114 may be formed using inorganic dielectrics such as silicon dioxide (SiO2), silicon nitride (Si3N4), silicon oxy nitride (SiON), and/or silicon carbon nitride (SiCN), organic dielectrics such as photoresists and adhesives, conductive materials such as metals, and combinations thereof.
The donor and receiver substrates 100, 110 may be (partially) bonded using any suitable bonding techniques, including, without limitation, hybrid bonding, fusion bonding, and adhesive bonding. The donor and receiver substrates 100, 110 may be debonded or released using any suitable debonding techniques, including, without limitation, IR and UV laser debonding. Further, there may be additional cleaning steps to reuse the donor substrate 100 before or after each selective layer transfer to a receiver substrate 110.
Further, in some embodiments, additional bonding and/or alignment features may be included at the wafer level and/or die level (e.g., on the donor dies, donor wafer, receiver wafer, and/or final product). For example, the donor and/or receiver wafer may include ridge or cross structures to facilitate bonding, such as a single ridge (e.g., a line or strip of dielectric material) extending across and/or through the center of the wafer, or multiple orthogonal ridges forming a cross-like pattern. Alignment features for wafers, die-lets, and/or die arrays may also be included to facilitate bonds with proper alignment. Further, multiple dies may be connected by small (e.g., dielectric) bridges to help them collectively bond and transfer together. For example, if some of the bridge-connected dies successfully bond to the receiver, the bridges may help others bond as well. Thus, these inter-die bridges may be present on the donor before the transfer, and on the receiver and final product after the transfer.
Further, in some cases, the debonding process may cause some unique damage or delamination near the edge and/or on the back of the dies, which does not impact process performance but may be indicative of this solution being used.
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Next, a bonding template 214 is formed on the surface of the receiver substrate 210 (e.g., above the release layer 212, if included). The bonding template 214 includes a pattern of bonding features or adhesive areas 214, such as mesas, that enable specific areas of the donor substrate 200 to be selectively transferred to the receiver substrate 210. In various embodiments, however, any suitable surface treatments or other techniques may be used to control the level of adhesion on different areas of the receiver substrate 210 (e.g., to form adhesive and non-adhesive areas for selective transfers), including, without limitation, surface topography variations (e.g., mesas, recesses), use of materials with high and/or low adhesion, treatments using hydrophobic materials and/or self-assembled monolayers (SAMs), and/or surface activation techniques, among other examples.
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Alternatively, in some embodiments, instead of (or in addition to) performing blanket laser exposure in
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Alternatively, in some embodiments, instead of (or in addition to) performing blanket laser exposure in
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The process may repeat in this manner until all IC components 306 on the donor die 301 have been transferred. At that point, the bond head 320 may pick up another donor die 301 and continue transferring IC components 306 from the new donor die 301 to the same or different receiver substrate 310.
After all transfers to the receiver substrate 310 are complete, the receiver 310 may be ready for continued processing, such as dielectric fill around the transferred IC components 306, planarization, selectively transferring or pick-and-place attaching additional IC dies or other IC components, via formation, formation of interconnect/metallization layers, attaching a structural substrate, debonding the receiver substrate (e.g., via the optional receiver release layer 312), and/or any other processing required for the finished product (e.g., an IC package).
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Additional processing may then be performed on the receiver substrate 450, such as cleaning steps (e.g., removing the leftover bonding structures 424, 444 from the transferred IC components 414, 434), dielectric fill around the transferred IC components 414, 434, planarization, selectively transferring or pick-and-place attaching additional IC dies or other IC components, via formation, formation of interconnect/metallization layers, attaching a structural substrate, debonding the receiver substrate (e.g., via the optional receiver release layer 452), and/or any other processing required for the finished product (e.g., an IC package).
It should be appreciated that the illustrated process flow for selective layer transfers is merely presented as an example and many other process variations are also possible, including, but not limited to, the process variations described throughout this disclosure.
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The bonding mesa 516 is used to selectively transfer a D2D interconnect 506 from the donor 502 to the receiver 512 (e.g., using any of the selective transfer flows described throughout this disclosure). For example, the donor 502 and receiver 512 are aligned face to face, stacked, and then partially bonded together such that one of the D2D interconnects 506 on the donor 502 is bonded to the bonding mesa 516 on the receiver 512.
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Notably, since the D2D interposer 506 was selectively transferred while the surrounding dielectric layers 510 were fabricated directly on the receiver 512, there is a scam 511 between the transferred D2D interposer 506 and the surrounding layers 510, as shown in
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The dies 518a-b may be attached using standard assembly techniques, such as pick and place, or using the selective transfer techniques described herein (e.g., similar to the transferred D2D interconnect 506).
If the dies 518a-b are attached using pick-and-place assembly, they are typically formed on a thick substrate for handling purposes and then subsequently thinned after the attach.
If the dies 518a-b are selectively transferred, however, they can be formed on—and transferred directly from—a very thin substrate. As a result, selectively transferring the dies 518a-b not only eliminates the need for post-attach thinning, it also enables the dies 518a-b to be much thinner than dies that are pick-and-place attached and subsequently thinned. Further, if the dies 518a-b are selectively transferred, there may be a seam 511 between the dies 518a-b and portions of the layers 510 surrounding the dies 518a-b, similar to the seam 511 shown around the transferred D2D interconnect 506, as described above. Moreover, because the dies 518a-b are selectively transferred, they can be different types of dies, formed on separate pieces of substrate material (e.g., separate wafers or panels) using separate processes, and then selectively transferred to the same layer of an IC device 500.
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At this point, the IC package 500 may be complete, or alternatively, additional processing may be performed. For example, if the processing is performed at the wafer or panel level, the resulting IC packages 500 on the structural substrate 520 may be singulated.
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While the illustrated example depicts a selective transfer between two wafers, selective transfers can be performed between panels or other substrates of any shape or size, including substrates with mismatched shapes and sizes.
The flowchart begins at block 702 by receiving a first substrate with a layer of integrated circuit (IC) components, which may be referred to as the donor substrate. In some embodiments, the donor substrate may include a base substrate, a release layer over the base substrate, and a (partially singulated) layer of IC components over the release layer.
In some embodiments, the donor substrate may be formed by receiving the base substrate, forming the release layer over the base substrate, forming the layer of IC components over the release layer (e.g., by fabricating or transferring the layer of IC components over the release layer), and partially singulating the layer of IC components (e.g., by dicing through the layer of IC components without dicing through the base substrate).
In various embodiments, the layer of IC components may include one or more IC dies, interconnects, transistors, diodes, resistors, capacitors, inductors, transformers, optical/opto-electrical components (e.g., optical waveguides, ring resonators, drivers, photodetectors, transimpedance amplifiers, electronic integrated circuits, optical transceivers, optical interfaces), and/or any other active or passive circuitry or components.
The base substrate may be made of one or more materials that include elements such as silicon (Si), oxygen (O), carbon (C), hydrogen (H), and/or Group III-V elements (e.g., aluminum (Al), gallium (Ga), indium (In), nitrogen (N), phosphorus (P), arsenic (As), antimony (Sb)), including, without limitation, silicon (Si), silicon dioxide (silica or SiO2), silicon on insulator (SOI), quartz, glass, Group III-V materials (e.g., gallium nitride (GaN), aluminum gallium nitride (GaN), gallium arsenide (GaAs), indium gallium arsenide (InGaAs), indium phosphide (InP)), and epoxies/resins (e.g., IR or UV transparent epoxies).
The release layer may include one or more layers of varying materials depending on the type of release or debonding technology used. For example, for IR laser debonding, the release layer may include one or more layers of material(s) capable of absorbing and/or reflecting infrared (IR) electromagnetic radiation, such as a thin metal layer or multiple metal layers (e.g., aluminum (Al), tungsten (W), copper (Cu), titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN)). For UV laser debonding, the release layer may include one or more layers of material(s) capable of absorbing ultraviolet (UV) electromagnetic radiation (e.g., organic polymers such as polyimides). In some embodiments, the release layer may additionally or alternatively include one or more layers of dielectric materials to buffer laser ablation and thermal energy, control thin film interference or adhesion, and/or provide residual adhesion after other materials and/or layers in the release layers are weakened, removed, and/or ablated by a laser (e.g., silicon dioxide (SiO2), silicon nitride (Si3N4), silicon oxynitride (SiON), silicon carbide (SiC), silicon carbon nitride (SiCN), silicon oxycarbon nitride (SiOCN), aluminum oxide (Al2O3), low-k dielectrics such as carbon-doped oxide (CDO) or porous silicon dioxide (SiO2), titanium dioxide (TiO2), tantalum oxide (Ta2O5)). Thus, in some embodiments, the release layer(s) may be made of one or more materials that include elements such as aluminum (Al), tungsten (W), copper (Cu), titanium (Ti), tantalum (Ta), silicon (Si), oxygen (O), nitrogen (N), hydrogen (H), and carbon (C), including, without limitation, any of the materials referenced above.
The flowchart then proceeds to block 704 to receive a second substrate with one or more adhesive areas, which may be referred to as the receiver substrate. In some embodiments, the receiver substrate may include a base substrate patterned with one or more adhesive areas on the surface, such as a layer of raised bonding structures or “mesas” over the base substrate. The receiver substrate may also optionally include a release layer over the base substrate (e.g., to enable the base substrate to be subsequently debonded after the transfer) and/or one or more additional buildup layers and/or IC components.
In some embodiments, the receiver substrate may be formed by receiving the base substrate, optionally forming a release layer over the base substrate, optionally forming additional buildup layers and/or IC components over the base substrate (e.g., over the optional release layer, if included), and forming the adhesive areas (e.g., bonding structures) on the surface of the receiver substrate (e.g., over the previously referenced layers, if included). In some embodiments, the base substrate and the optional release layer of the receiver may be made of any of the materials referenced above for the base substrate and the release layer of the donor, respectively.
In some embodiments, the adhesive areas may include mesa structures with similar footprints as the corresponding IC components to be transferred from the donor (although, in some cases, the mesas may be slightly larger or smaller than the IC components to accommodate alignment and manufacturing tolerances). The mesa structures may be made of varying materials depending on the type of bond and/or whether electrical connections are needed through the bond interface for the subsequently bonded IC components (e.g., dielectric material, metal, or both). For example, the mesa structures may include blanket dielectric structures with no conductive contacts (e.g., for dielectric-to-dielectric bonds), dielectric structures with conductive contacts (e.g., for hybrid dielectric and metal bonds), and/or conductive contacts by themselves (e.g., for metal-to-metal bonds). Thus, in some embodiments, the mesa structures may be made of one or more materials that include elements such as silicon (Si), oxygen (O), hydrogen (H), nitrogen (N), carbon @, aluminum (Al), tungsten (W), copper (Cu), titanium (Ti), tantalum (Ta), including, without limitation, inorganic dielectrics such as silicon dioxide (SiO2), silicon nitride (Si3N4), and/or silicon carbon nitride (SiCN), organic dielectrics such as photoresists and adhesives, and/or conductive materials such as metals and alloys (e.g., any of the foregoing metal elements and/or compounds/alloys thereof).
In various embodiments, however, any suitable technique(s) may be used to control the level of adhesion on different areas of the receiver substrate. For example, a variety of surface treatments (e.g., lithographically or additively manufactured) can be used to enhance and/or reduce adhesion in select areas of the receiver substrate, including, without limitation, modifying the surface topography (e.g., raised vs. recessed areas, smooth vs. rough areas), use of materials with high and/or low adhesion (e.g., forming layers with adhesive and non-adhesive materials in select areas), treatments using hydrophobic materials and/or self-assembled monolayers (SAMs), and/or surface activation techniques (e.g., plasma or wet activation), among other examples.
For example, the surface topography of the receiver substrate may be modified (e.g., using techniques such as deposition, lithography, etching, roughening) to form areas with different levels of adhesion, such as raised (e.g., adhesive) and recessed (e.g., non-adhesive) areas, smooth (e.g., adhesive) and rough (e.g., non-adhesive) areas, etc.
As another example, the surface of the receiver substrate may be patterned with materials having high and/or low adhesion in select areas. For example, a layer patterned with different areas of adhesive and non-adhesive materials may be formed on the receiver substrate. In some embodiments, the adhesive material may include silicon dioxide (SiO2) or silicon carbon nitride (SiCN) to promote strong oxide fusion bonds, silicon carbide (SiC) to provide lower thermal contact resistance compared to SiO2 or SiCN, and/or metal to form electrical connections. Further, in some embodiments, the non-adhesive material may include silicon nitride (Si3N4) to form weak or no bonds.
As another example, treatments using hydrophobic materials and/or self-assembled monolayers (SAMs) may be used to enhance and/or reduce adhesion in select areas of the receiver substrate (e.g., using a SAM treatment to create monolayers with high and/or low adhesion in select areas). In some embodiments, the hydrophobic material may include a SAM material such as an alkyl or fluoroalkyl silane (e.g., ODS, FDTS), a thiol (e.g., hexadecane thiol), a phosphonic acid (e.g., octadecyl or perfluorooctane phosphonic acid), or an alkanoic acid (e.g., heptadecanoic acid). However, non-SAM based materials or films may also be used. In some embodiments, the hydrophobic material may include a thin polymer film such as a siloxane (e.g., PDMS and derivatives, HMDSO), a silazane (HMDS), a polyolefin (e.g., PP), or a fluorinated polymer (e.g., PTFE, PFPE, PFDA, C4F8 plasma polymerized films, etc.). Other hydrophobic materials may be used in other embodiments.
As another example, surface activation techniques may be used to enhance and/or reduce adhesion in select areas of the receiver substrate, including, without limitation, plasma or wet activation.
The flowchart then proceeds to block 706 to partially bond the donor substrate to the receiver substrate (e.g., face to face), such that one or more target IC components on the donor substrate are selectively bonded to the one or more adhesive areas on the receiver substrate. The donor and receiver substrates may be partially bonded using any suitable bonding techniques, including, without limitation, hybrid bonding, fusion bonding, and/or adhesive bonding.
The flowchart then proceeds to block 708 to release the target IC components from the donor substrate and separate the donor substrate from the receiver substrate. In this manner, when the donor and receiver substrates are separated, the target IC components are separated from the donor substrate and remain on the receiver substrate.
In some embodiments, the donor and receiver substates may be debonded/separated from each other by releasing, at least partially, the target IC components from the release layer of the donor substrate and then mechanically separating the donor and receiver substrates. For example, in some embodiments, the target IC components may be fully released from the donor substrate by selectively debonding them from the donor release layer using a laser (e.g., an IR or UV laser), or alternatively, the target IC components may be partially released from the donor substrate by weakening the donor release layer using a laser (e.g., an IR or UV laser). After fully or partially releasing the target IC components from the donor, the donor and receiver substrates are mechanically separated, and post separation, the target IC components remain bonded to the receiver and are no longer on the donor.
Alternatively, or additionally, the donor release layer and the receiver bonding structures may be formed with respective materials that have disparate bond strengths-such that the target IC components have a stronger bond to the receiver than the donor-thus causing the target IC components to debond from the donor and remain on the receiver when the donor and receiver are mechanically separated.
The flowchart then proceeds to block 710 to perform any remaining processing, such as dielectric filling and planarization, attaching additional IC dies or components (e.g., via selective transfers or pick-and-place assembly), forming interconnects (e.g., vias, traces), attaching a structural substrate, debonding the receiver base substrate (e.g., via the optional receiver release layer), and/or any other processing required for the finished product (e.g., an IC package, device, system, etc.).
The completed product may include a variety of components and circuitry (some of which may have been selectively transferred), including electrical components (e.g., electronic integrated circuits (EICs), processors, XPUs, controllers, memory), optical components (e.g., optical interfaces, photonic integrated circuits (PICs), optical connectors, fibers), and/or radio frequency (RF) or high-voltage components (e.g., high-voltage electrostatic discharge (ESD) devices, power amplifiers (PAs), low noise amplifiers (LNAs), voltage controlled oscillators (VCOs), surface acoustic wave (SAW)/bulk acoustic wave (BAW) devices or filters, bandpass filters (BPFs), intermediate-frequency (IF) amplifiers, frequency synthesizers, mixers, RF digital-to-analog converters (DACs), RF analog-to-digital converters (ADCs), thick gate oxide devices, Group III-V devices/chiplets, passive RF devices such as interconnects, antennas, and inductors).
Further, in some embodiments, the resulting IC package or product may be electrically coupled to a circuit board and/or incorporated into an electronic device or system (e.g., with other electronic components).
At this point, the flowchart may be complete. In some embodiments, however, the flowchart may restart and/or certain blocks may be repeated. For example, in some embodiments, the flowchart may restart at block 702 to continue performing selective transfers.
Typical silicon photonics architectures may have some components fabricated in situ (e.g., waveguides, ring resonators), other components assembled through hybrid assembly techniques (e.g., by transferring a blank semiconductor component and then processing it in situ, such as for certain laser fabrication techniques), and the remaining components assembled through standard assembly techniques (e.g., pick-and-place assembly for electronic integrated circuit (EIC) components such as drivers and transimpedance amplifiers (TIAs)). While this combination attempts to utilize the capabilities of each individual technique to hit performance and cost targets, there are various drawbacks. Other embodiments are also possible, for example all the components may be fabricated monolithically on the same substrate (e.g., using a combined CMOS and optical/optoelectronic manufacturing process).
For example, in-situ manufacturing techniques typically involve a full transfer or growth of an active layer (e.g., gallium nitride (GaN) or indium phosphide (InP)) followed by etching out the unneeded portions. This approach is cost inefficient since a big portion of the transferred or grown material is effectively etched away.
Hybrid manufacturing techniques typically involve transferring blocks of active layers (e.g., GaN or InP materials) and then processing them in situ. While this approach is more cost efficient than in-situ techniques with full layer transfers, the manufacturing is not well parallelized since most of the wafer is effectively masked while the transferred components are being fabricated.
Pick-and-place assembly techniques typically involve mechanically transferring fabricated devices (e.g., arrays of optoelectronic components) to a photonics substrate. In this manner, all components can be manufactured in parallel on their respective ideal substrates (e.g., logic/Si, GaN, InP, etc.), and the finished components can then be attached to the final photonics substrate. However, standard assembly techniques have limitations on the size and thickness of the respective components, which limits the applicability of this approach to relatively large components or to transferring larger components then etching them to reduce their size which limits the efficiency and increases the cost. Further, die handling can cause edge dislocations, which may render the substrate materials (e.g., InP) inefficient and susceptible to defects.
Accordingly, this disclosure presents techniques for parallel transfer of optical and opto-electronic components using selective transfer technology, along with devices and systems formed using the same. In particular, selective transfer technology (e.g., as described above in connection with
The described solution provides various advantages. For example, this solution enables parallel manufacturing and transfer of the respective components of optical devices, which increases manufacturing speed and reduces costs compared to in-situ fabrication techniques and standard pick-and-place assembly. This solution also enables all components to be manufactured on their respective substrates with significantly less wasted processing area compared to hybrid manufacturing techniques. Further, this solution enables direct assembly of all components, which simplifies the manufacturing flow, reduces costs, and improves performance.
This solution also enables granular integration of different optical and opto-electronic components with high placement accuracy and very few limitations on the area of transferred components. As a result, optical and electronic components can be placed very close together, which results in much lower parasitics and higher energy efficiency.
This solution also enables integration of components from incompatible process technologies. For example, photonic integrated circuits (PICs) include a variety of components fabricated using different process technologies, some of which may be incompatible with each other. In particular, silicon/silicon dioxide (Si/SiO2) waveguide, germanium (Ge) photodiode, and gallium nitride (GaN) transistor technologies incorporate high-temperature fabrication steps, which may not be compatible with process technologies for the ring modulator and laser. This solution enables all of those components to be fabricated using separate and distinct process technologies, in different fabs, and eventually, assembled using selective transfers.
This solution also enables the use of novel base substrates for optical devices. In particular, since typical in-situ manufacturing steps can be completely replaced with selective transfers, this solution provides the flexibility to use base substrates made of materials other than silicon, such as glass substrates, silicon-on-insulator (SOI) substrates, or silicon carbide (SIC) substrates, among other examples. In some cases, for example, a glass substrate may be used for lower loss, improved electrical losses, and/or operating at different frequencies. Substrates in panel formats may be used to enable wafer-scale systems. Further, in some cases, substrates and/or components may be selectively transferred directly on top of a silicon substrate within a CMOS fabrication process flow.
In the illustrated embodiment, optical transceiver 800 includes an electronic integrated circuit (EIC) 802, a transmitter 810, and a receiver 820.
The EIC 802 includes various high-speed electronics and/or control electronics (e.g., in-plane or stacked), such as carrier phase recovery (CPR), clock and data recovery (CDR), error correction, serializers/deserializers (serdes), equalizers, samplers, mixers, amplifiers, temperature control (e.g., heaters), analog-to-digital converters (ADC) and digital-to-analog converters (DAC), control and switching, controllers/compute engines, power delivery, and/or power conversion. The EIC 802 typically also includes drivers 811 and transimpedance amplifiers (TIAs) 821, but in the illustrated embodiment, the drivers 811 and TIAs 821 are disaggregated from the EIC 802 (e.g., implemented on separate IC dies) and placed near the modulators 812a-b and photodetectors (PDs) 823, respectively, to improve performance, as described below.
The transmitter 810 includes a laser source 818, a waveguide 816 to guide light from the laser source 818, an optical coupler 817 to couple the waveguide 816 to another optical component such as a fiber (not shown), multiple modulators 812a-b to modulate different wavelengths of light (λ1, λ2) on the transmitter waveguide 816, and multiple drivers 811 to control the respective modulators 812a-b. In the illustrated embodiment, ring resonator modulators 812a-b are used. Each modulator 812a-b includes an electrode 813, a ring resonator 814, and a waveguide 815. When the corresponding driver 811 applies a voltage to the ring resonator 814 via the electrode 813, light of a particular wavelength (e.g., λ1 or λ2) on the transmitter waveguide 816 is absorbed by the ring resonator 814 and output to the modulator waveguide 815, thus effectively filtering the particular wavelength of light from the transmitter waveguide 816. In this manner, multiple wavelengths of light can be multiplexed on the transmitter waveguide 816 using the respective drivers 811 and modulators 812a-b, which is referred to as wavelength-division multiplexing (WDM). Other types of modulators are also possible, such as Mach-Zehnder modulators and variants thereof.
The receiver 820 includes a waveguide 826 to guide light received from another component (not shown) via an optical coupler 827, multiple detectors 822a-b to detect different wavelengths of light (λι, λ2) on the receiver waveguide 826, and multiple photodetectors (PDs) 823 and transimpedance amplifiers (TIAs) 821 to convert the detected light waves into electrical signals and amplify them. Each detector 822a-b includes a ring resonator 824 and a waveguide 825. When light of a particular wavelength (e.g., λ1 or λ2) is received on the receiver waveguide 826, those light waves are transmitted by the corresponding ring resonator 824 to the detector waveguide 825, and then passed as input to the PD 823. The PD 823 converts the light waves (e.g., optical signals) into electric current, and the TIA 821 converts the current into corresponding voltage (e.g., current-to-voltage conversion), which is then passed to the EIC 802 to generate/output an electrical (e.g., digital) signal based on the voltage. In this manner, multiple wavelengths of light can be received on the receiver waveguide 826, demultiplexed, and then converted into corresponding electrical signals (e.g., using the respective TIAs 821, PDs 823, and detectors 822a-b). For simplicity, not all components of an optical transceiver 800 are shown in the illustrated example (e.g., there may be heaters and corresponding control circuitry to control the temperature of the different optical/opto-electronic components, among other components).
In the illustrated embodiment, certain components that are typically integrated within the EIC 802 are disaggregated or disintegrated from the EIC 802 to improve performance. For example, the TIAs 821 are disaggregated from the EIC 802 and placed closer to the PDs 823 to reduce parasitics, maximize receiver sensitivity, and provide higher energy efficiency. Similarly, the drivers 811 are disaggregated from the EIC 802-enabling them to be implemented using a different (e.g., optimized) semiconductor process—and placed closer to the respective modulators 812a-b. In some embodiments, these disaggregated components may be assembled in the optical transceiver 800 using selective transfer technology, which enables the components to be fabricated in parallel on optimal substrate materials using optimal process technologies, and then selectively transferred to optimal locations in the optical transceiver circuit 800, without the downsides of other techniques (e.g., constraints on size, area, and thickness for components assembled using pick-and-place techniques).
In some embodiments, other components of the optical transceiver 800 may similarly be assembled using selective transfer technology, including the EIC 802, waveguides 815, 816, 825, 826, ring resonators 814, 824, electrodes 813, PDs 823, and laser source 818, among other examples.
It should be appreciated that the illustrated embodiment of optical transceiver 800 is merely presented as an example and numerous other variations are also possible. For example, the optical transceiver 800 may include any number of EICs 802, transmitter units 810, receiver units 820, waveguides 816, 826, modulators 812, detectors 822, drivers 811, TIAs 821, PDs 823, and so forth. The optical transceiver 800 may include other components not shown, and/or certain components may be omitted, combined, separated, and/or rearranged.
Selective transfer technology, in combination with quasi-monolithic chip (QMC) building blocks, can be used to transfer electrical components very close to optical components to improve overall system performance. In particular, certain components that are typically integrated within the electronic integrated circuit (EIC) 906 may be disaggregated or disintegrated from the EIC 906 (e.g., such that the EIC and the disaggregated components are implemented on separate IC dies) to enable them to be placed closer to corresponding optical components. As an example, the TIA circuit 905 can be disaggregated from the EIC 906 and fabricated as a standalone chiplet, and the TIA chiplet 905 can be selectively transferred near the photodetector (PD) 904 on a photonic substrate 902, which enables a very close connection between the TIA 905 and the PD 904 to maximize receiver sensitivity. Similarly, a driver circuit could be disaggregated from the EIC 906 and selectively transferred near an optical modulator.
In this manner, the electrical components can be fabricated in parallel on optimal substrate materials using optimal process technologies, and then selectively transferred to optimal locations in the photonic substrate 902, without the downsides of other techniques (e.g., incompatible process technologies, dimensional constraints on pick-and-place assembly). In some embodiments, for example, certain high-speed electronics may be implemented using Group III-V semiconductor devices, such as GaN transistors, which are well-suited for high-voltage and high-frequency driver electronics and low-noise amplifiers due to their wide bandgap and high mobility channel.
An example process flow is shown in
In
In
In
Other interconnects may also be formed on the substrate 902 to enable additional electrical connections. In some embodiments, for example, the photonic IC may also function as an electrical interposer to enable electrical connections between multiple top chiplets, and thus an interconnect may be formed for the interposer capability. Further, the interconnects may be fabricated monolithically as shown, or other chiplets that can provide the electrical connection functionality may be fabricated and then assembled and/or selectively transferred.
In
Further, the EIC 906 may be attached to the top surface using standard assembly techniques, such as pick-and-place assembly with hybrid bonding (e.g., via the respective hybrid bonding pads 908d,e and dielectric layers 907) or with solder assembly if the density and added parasitics are acceptable. Alternatively, in some embodiments, highly disaggregated EIC chiplets may be attached using selective transfer techniques with on-chip routing to enable electrical connectivity.
In
It should be appreciated that the illustrated process flow for forming an optical transceiver 900 using selective transfer technology is merely presented as an example and many other process variations and architectures are also possible, including those described in connection with other figures. Moreover, other electrical and/or optical components can be selectively transferred to the photonic substrate 902 in a similar manner, including EICs, drivers, photodetectors 904, optical waveguides, mirrors, ring resonators, modulators, detectors, diffraction grating, isolation, and/or anti-reflection structures, heater elements, and so forth.
Further, the selective transfers may be performed using any of the selective transfer techniques described throughout this disclosure (e.g., in connection with
In some embodiments, for example, the donor wafer 910 may include a variety of IC components, such as TIA ICs, driver ICs, telemetry ICs, and so forth. Moreover, during the stamp 920 bond/debond transfer steps, the stamp 920 may pick up and selectively transfer the TIA ICs to the photonic wafer 902 first, followed by the driver ICs, then the telemetry ICs, etc. Alternatively, or additionally, there may be multiple donor wafers 910 that each contain separate intellectual property (IP) blocks, such as a donor 910 with TIA ICs, a donor 910 with driver ICs, etc. During the stamp 920 bond/debond selective transfer steps, the stamp 920 may first pick up and transfer TIAs from the TIA donor wafer 910 to the photonic wafer 902, then transfer driver ICs from the driver donor wafer 910, etc. In the case of stamp 920 selective transfers, there may not be corresponding lower mesas on the transferred components, but if other selective transfer techniques are used, there may be corresponding mesas.
In
In
In
In
In
For example, selective transfer technology can be used to transfer optical components, such as photodetectors, optical waveguides, mirrors, ring resonators, modulators, detectors, diffraction grating, isolation, and/or anti-reflection structures, and heater elements, among other examples. The respective components can be selectively transferred in plane (e.g., within a single layer) to maintain the same architecture capability, or they can be stacked across multiple layers to further reduce the system size and/or reduce losses.
Examples of a micro-ring resonator device transferred into a single layer and across multiple layers are respectively shown in
In
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As shown in
As shown in
These various components are integrated on an interposer 1202 with a waveguide network 1208 for optical input/output (I/O) among the compute hubs 1210a-i, along with an electrical interconnect 1206 for power (e.g., from the IC package (not shown)) and I/O (e.g., I/O among components within each compute hub 1210a-i, I/O among the compute hubs 1210a-i or other components in the system 1200, and I/O among other components in the same IC package). The compute platform 1200 also includes inter-layer dielectric (ILD) materials 1206 separating the respective components and a carrier substrate 1201 for structural support (e.g., a silicon thermal handle carrier).
In the illustrated embodiment, selective transfer technology is used to interconnect both compute and photonic devices across an interposer 1202, such as a passive glass or silicon interposer or an active interposer. The waveguide network 1208 may be fabricated directly on top of the interposer 1202 or fabricated elsewhere and selectively transferred to the interposer 1202. Additionally, sub-components can be pre-made using the same approach or transferred sequentially to create a high-speed transmission (Tx) data encoding system 1214 with ring resonators 1215 within the footprint and coupled to the waveguides 1208 vertically across the network to maintain a tight spacing to the underlying waveguides 1208. This has the advantage of allowing thermal control with good isolation. A mixed fusion and hybrid bonded interconnect 1206 is used to maintain interconnection to a nearby XPU 1211 and/or memory solution as well as power from the package. Additionally, discrete photodiodes (PDs) 1212 may be selectively transferred over the waveguide array 1208 and evanescent coupling (among other approaches) may be utilized to maximize the current output. In some embodiments, the transimpedance amplifier (TIA) 1213 may be fabricated or selectively transferred over the photodiode layer (not shown) or situated at a tight spacing nearby such that vertical interconnects (e.g., TSVs) can be employed to allow direct vertical electrical coupling to the XPU 1211 (e.g., with a 3D interconnect). This system architecture allows for off-package I/O as well as XPU-to-XPU or memory hub interconnection with high data rates, which is crucial for extreme lateral system scaling. In some embodiments, electrical connections may be formed between the different top chiplets using monolithic interconnects or using assembled interconnect chiplets.
In the illustrated embodiment, the optical package 1300 includes an XPU 1308 and multiple optical interfaces (e.g., optical transceivers) 1310 on a package substrate 1302, along with optical cables 1320 plugged into the respective optical interfaces 1310.
Each optical interface 1310 includes an optical coupler 1312, a photonic integrated circuit (PIC) 1304, and an electronic integrated circuit (EIC) 1306. The EICs 1306 are attached to the top surface of the package substrate 1302, the PICs 1304 are attached to the top surface of corresponding EICs 1306, and the optical couplers 1312 are attached to the side/edge of corresponding PICs 1304.
The EICs 1306 are used to control the PICs 1304 and output digital signals based on optical signals received by the PICs 1304. In some embodiments, the EICs 1306 may receive and output analog and digital input and output signals. The EICs 1306 may contain digital, analog, and/or telemetry (e.g., performance monitoring) circuitry to perform control functions and signals processing, including components and circuitry such as drivers, transimpedance amplifiers (TIA), carrier phase recovery (CPR), clock and data recovery (CDR), error correction, serializers/deserializers (serdes), equalizers, samplers, mixers, amplifiers, temperature control (e.g., heaters), analog-to-digital converters (ADC) and digital-to-analog converters (DAC), control and switching, controllers/compute engines, power delivery, power conversion, and so forth. The EICs 1306 are electrically coupled to the package substrate 1302 via conductive contacts 1307 (e.g., bumps/micro-bumps), and the EICs 1306 are further electrically coupled to the XPU 1308 via the bridges 1303 embedded in the substrate 1302.
The PICs 1304 are used to send and/or receive optical signals via fiber arrays 1324 (e.g., on behalf of the XPU 1308). Each PIC 1304 includes components and circuitry for sending and receiving optical signals, such as laser diodes (LD)/modulators (LD-MOD) (e.g., for transmitting optical signals), photodiodes (PD) (e.g., for receiving optical signals), optical waveguides, optical couplers, collimation/refocusing lenses, reflection mirrors, and so forth. Each PIC 1304 is controlled by an associated EIC 1306 and is electrically coupled to the top surface of the EIC 1306 via conductive contacts 1305 (e.g., bumps/micro-bumps).
An optical coupler 1312 is also attached to each PIC 1304. The optical coupler 1312, which may also be referred to as an optical interposer, is used to optically couple, or route optical signals (e.g., light) between, the PIC 1304 and another optical component, such as an optical cable 1320. In some embodiments, the optical coupler 1312 may include an interface attached to the PIC 1304, an interface to mate with an optical ferrule 1322 on an optical cable 1320, and waveguides to route optical signals between the respective interfaces. The optical coupler 1312 may optionally include various other optical and/or electrical routing features, such as through-glass vias, reflection mirrors, and so forth.
Each optical cable 1320 includes an optical ferrule 1322 attached to a bundle of optical (e.g., glass) fibers 1324, which may be referred to as a fiber array or fiber array unit (FAU). The optical ferrule 1322 may be used to optically couple, or route optical signals between, the fiber array 1324 and an optical coupler 1312. In some embodiments, the optical ferrule 1322 may include an interface attached to the fiber array 1324 (e.g., holes in the ferrule 1322 in which the fibers 1324 are inserted), an interface to mate with an optical coupler 1312, and waveguides to route optical signals between the respective interfaces.
In some embodiments, for example, the optical coupler 1312 and the optical ferrule 1322 may include complementary pluggable interfaces that are designed to mate. For example, the optical coupler 1312 may include an optical socket and the optical ferrule 1322 may include a corresponding optical plug designed to mate with the optical socket (or vice versa). In this manner, each PIC 1304 is optically coupled to an associated fiber array 1324 via the mated optical coupler 1312 and optical ferrule 1322.
Further, in some embodiments, the optical coupler 1312 and optical ferrule 1322 may include complementary mating and alignment features (e.g., mating protrusions and receptacles, pins and pin holes, grooves) to ensure they mate with each other with the requisite degree of alignment, as the waveguides in the ferrule 1322 must be precisely aligned with the waveguides in the optical coupler 1312. For example, when the optical ferrule 1322 is plugged into to the optical coupler 1312, their respective mating and alignment features engage, which causes the waveguides in the ferrule 1322 to precisely align with the waveguides in the optical coupler 1312. In this manner, the PIC 1304 is optically coupled to the fiber array 1324 via the mated optical coupler 1312 and ferrule 1322, which enables the PIC 1304 to send and receive optical signals via the fiber array 1324.
In some embodiments, the optical coupler 1312 and/or optical ferrule 1322 may be made of glass, and their respective features (e.g., interfaces, mating/alignment features, waveguides) may be patterned in the glass (e.g., using laser etching techniques).
The fiber array 1324 may be used to send and receive optical signals to and from other components (not shown). For example, the other end of the fiber array 1324 may be optically coupled to other components (not shown), such as other computing components that are part of the same device or system as optical package 1300 (e.g., processors, XPUs, network interface controllers (NICs), storage, memory, I/O devices, other integrated circuits), an external device or system, a switch, another optical connector (e.g., a connector similar to optical coupler 1312 and/or optical ferrule 1322, a standard optical connector such as a mechanical transfer (MT) or multi-fiber push on (MPO) connector), a fiber cable, and so forth.
The XPU 1308 is attached to the top surface of the package substrate 1302. Moreover, the XPU 1308 is electrically coupled to the package substrate 1302 via conductive contacts 1309 (e.g., bumps/micro-bumps), which serve as the first level interconnect (FLI) for the XPU 1308. The XPU 1308 is also electrically coupled to the EICs 1306 via bridges 1303 embedded in the substrate 1302 (e.g., embedded multi-die interconnect bridges (EMIB)). In this manner, the XPU 1308 can use the EICs 1306 to communicate over the respective optical interfaces 1310.
The XPU 1308 may include any type or combination of integrated circuitry that uses the optical interfaces 1310 for optical communication. For example, the XPU 1308 may include any type or combination of processing units or other computing components, including, but not limited to, microcontrollers, microprocessors, processor cores, central processing units (CPUs), graphics processing units (GPUs), vision processing units (VPUs), tensor processing units (TPUs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), input/output (I/O) controllers and devices, switches, network interface controllers (NICs), persistent storage devices, and memory.
The package substrate 1302 includes conductive contacts 1301 (e.g., balls, pads) on the bottom surface, which serve as the second level interconnect (SLI) to a next-level component, such as a printed circuit board (e.g., a motherboard) and/or another integrated circuit package (not shown). The package substrate 1302 also includes conductive traces (not shown) patterned in the substrate to provide power and input/output (I/O) to the respective components in package 1300 (e.g., XPU 1308, EICs 1306, PICs 1304).
In some embodiments, the optical package 1300 may be part of an electronic device or system, such as a mobile device, a wearable device, a computer, a server, a video playback device, a video game console, a display device, a camera, or an appliance. For example, the optical package 1300 and various other electronic components may be electrically coupled to a circuit board within the electronic device.
It should be appreciated that optical package 1300 is merely presented as an example. In other embodiments, certain components may be omitted, added, rearranged, modified, or combined. For example, embodiments may include any number, combination, or arrangement of PICs and EICs (e.g., for higher bandwidth and/or redundancy), optical connectors, optical couplers, optical ferrules, optical interposers, fibers, bridges, XPUs or other computing components, substrates, surface cavities in the substrate, conductive contacts, conductive traces, vias, integrated circuit packages, and so forth.
The integrated circuit device 1500 may include one or more device layers 1504 disposed on the die substrate 1502. The device layer 1504 may include features of one or more transistors 1540 (e.g., metal oxide semiconductor field-effect transistors (MOSFETs)) formed on the die substrate 1502. The transistors 1540 may include, for example, one or more source and/or drain (S/D) regions 1520, a gate 1522 to control current flow between the S/D regions 1520, and one or more S/D contacts 1524 to route electrical signals to/from the S/D regions 1520. The transistors 1540 may include additional features not depicted for the sake of clarity, such as device isolation regions, gate contacts, and the like. The transistors 1540 are not limited to the type and configuration depicted in
A transistor 1540 may include a gate 1522 formed of at least two layers, a gate dielectric and a gate electrode. The gate dielectric may include one layer or a stack of layers. The one or more layers may include silicon oxide, silicon dioxide, silicon carbide, and/or a high-k dielectric material.
The high-k dielectric material may include elements such as hafnium, silicon, oxygen, titanium, tantalum, lanthanum, aluminum, zirconium, barium, strontium, yttrium, lead, scandium, niobium, and zinc. Examples of high-k materials that may be used in the gate dielectric include, but are not limited to, hafnium oxide, hafnium silicon oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate. In some embodiments, an annealing process may be carried out on the gate dielectric to improve its quality when a high-k material is used.
The gate electrode may be formed on the gate dielectric and may include at least one p-type work function metal or n-type work function metal, depending on whether the transistor 1540 is to be a p-type metal oxide semiconductor (PMOS) or an n-type metal oxide semiconductor (NMOS) transistor. In some implementations, the gate electrode may consist of a stack of two or more metal layers, where one or more metal layers are work function metal layers and at least one metal layer is a fill metal layer. Further metal layers may be included for other purposes, such as a barrier layer.
For a PMOS transistor, metals that may be used for the gate electrode include, but are not limited to, ruthenium, palladium, platinum, cobalt, nickel, conductive metal oxides (e.g., ruthenium oxide), and any of the metals discussed below with reference to an NMOS transistor (e.g., for work function tuning). For an NMOS transistor, metals that may be used for the gate electrode include, but are not limited to, hafnium, zirconium, titanium, tantalum, aluminum, alloys of these metals, carbides of these metals (e.g., hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide, and aluminum carbide), and any of the metals discussed above with reference to a PMOS transistor (e.g., for work function tuning).
In some embodiments, when viewed as a cross-section of the transistor 1540 along the source-channel-drain direction, the gate electrode may consist of a U-shaped structure that includes a bottom portion substantially parallel to the surface of the die substrate 1502 and two sidewall portions that are substantially perpendicular to the top surface of the die substrate 1502. In other embodiments, at least one of the metal layers that form the gate electrode may simply be a planar layer that is substantially parallel to the top surface of the die substrate 1502 and does not include sidewall portions substantially perpendicular to the top surface of the die substrate 1502. In other embodiments, the gate electrode may consist of a combination of U-shaped structures and planar, non-U-shaped structures. For example, the gate electrode may consist of one or more U-shaped metal layers formed atop one or more planar, non-U-shaped layers.
In some embodiments, a pair of sidewall spacers may be formed on opposing sides of the gate stack to bracket the gate stack. The sidewall spacers may be formed from materials such as silicon nitride, silicon oxide, silicon carbide, silicon nitride doped with carbon, and silicon oxynitride. Processes for forming sidewall spacers are well known in the art and generally include deposition and etching process steps. In some embodiments, a plurality of spacer pairs may be used; for instance, two pairs, three pairs, or four pairs of sidewall spacers may be formed on opposing sides of the gate stack.
The S/D regions 1520 may be formed within the die substrate 1502 adjacent to the gate 1522 of individual transistors 1540. The S/D regions 1520 may be formed using an implantation/diffusion process or an etching/deposition process, for example. In the former process, dopants such as boron, aluminum, antimony, phosphorous, or arsenic may be ion-implanted into the die substrate 1502 to form the S/D regions 1520. An annealing process that activates the dopants and causes them to diffuse farther into the die substrate 1502 may follow the ion-implantation process. In the latter process, the die substrate 1502 may first be etched to form recesses at the locations of the S/D regions 1520. An epitaxial deposition process may then be carried out to fill the recesses with material that is used to fabricate the S/D regions 1520. In some implementations, the S/D regions 1520 may be fabricated using a silicon alloy such as silicon germanium or silicon carbide. In some embodiments, the epitaxially deposited silicon alloy may be doped in situ with dopants such as boron, arsenic, or phosphorous. In some embodiments, the S/D regions 1520 may be formed using one or more alternate semiconductor materials such as germanium or a group III-V material or alloy. In further embodiments, one or more layers of metal and/or metal alloys may be used to form the S/D regions 1520.
Electrical signals, such as power and/or input/output (I/O) signals, may be routed to and/or from the devices (e.g., transistors 1540) of the device layer 1504 through one or more interconnect layers disposed on the device layer 1504 (illustrated in
The interconnect structures 1528 may be arranged within the interconnect layers 1506-1510 to route electrical signals according to a wide variety of designs; in particular, the arrangement is not limited to the particular configuration of interconnect structures 1528 depicted in
In some embodiments, the interconnect structures 1528 may include lines 1528a and/or vias 1528b filled with an electrically conductive material such as a metal. The lines 1528a may be arranged to route electrical signals in a direction of a plane that is substantially parallel with a surface of the die substrate 1502 upon which the device layer 1504 is formed. For example, the lines 1528a may route electrical signals in a direction in and out of the page and/or in a direction across the page from the perspective of
The interconnect layers 1506-1510 may include a dielectric material 1526 disposed between the interconnect structures 1528, as shown in
A first interconnect layer 1506 (referred to as Metal 1 or “M1”) may be formed directly on the device layer 1504. In some embodiments, the first interconnect layer 1506 may include lines 1528a and/or vias 1528b, as shown. The lines 1528a of the first interconnect layer 1506 may be coupled with contacts (e.g., the S/D contacts 1524) of the device layer 1504. The vias 1528b of the first interconnect layer 1506 may be coupled with the lines 1528a of a second interconnect layer 1508.
The second interconnect layer 1508 (referred to as Metal 2 or “M2”) may be formed directly on the first interconnect layer 1506. In some embodiments, the second interconnect layer 1508 may include via 1528b to couple the lines 1528 of the second interconnect layer 1508 with the lines 1528a of a third interconnect layer 1510. Although the lines 1528a and the vias 1528b are structurally delineated with a line within individual interconnect layers for the sake of clarity, the lines 1528a and the vias 1528b may be structurally and/or materially contiguous (e.g., simultaneously filled during a dual-damascene process) in some embodiments.
The third interconnect layer 1510 (referred to as Metal 3 or “M3”) (and additional interconnect layers, as desired) may be formed in succession on the second interconnect layer 1508 according to similar techniques and configurations described in connection with the second interconnect layer 1508 or the first interconnect layer 1506. In some embodiments, the interconnect layers that are “higher up” in the metallization stack 1519 in the integrated circuit device 1500 (i.e., farther away from the device layer 1504) may be thicker that the interconnect layers that are lower in the metallization stack 1519, with lines 1528a and vias 1528b in the higher interconnect layers being thicker than those in the lower interconnect layers.
The integrated circuit device 1500 may include a solder resist material 1534 (e.g., polyimide or similar material) and one or more conductive contacts 1536 formed on the interconnect layers 1506-1510. In
In some embodiments in which the integrated circuit device 1500 is a double-sided die, the integrated circuit device 1500 may include another metallization stack (not shown) on the opposite side of the device layer(s) 1504. This metallization stack may include multiple interconnect layers as discussed above with reference to the interconnect layers 1506-1510, to provide conductive pathways (e.g., including conductive lines and vias) between the device layer(s) 1504 and additional conductive contacts (not shown) on the opposite side of the integrated circuit device 1500 from the conductive contacts 1536. These additional conductive contacts may serve as any of the conductive contacts described throughout this disclosure.
In other embodiments in which the integrated circuit device 1500 is a double-sided die, the integrated circuit device 1500 may include one or more through silicon vias (TSVs) through the die substrate 1502; these TSVs may make contact with the device layer(s) 1504, and may provide conductive pathways between the device layer(s) 1504 and additional conductive contacts (not shown) on the opposite side of the integrated circuit device 1500 from the conductive contacts 1536. These additional conductive contacts may serve as any of the conductive contacts described throughout this disclosure. In some embodiments, TSVs extending through the substrate can be used for routing power and ground signals from conductive contacts on the opposite side of the integrated circuit device 1500 from the conductive contacts 1536 to the transistors 1540 and any other components integrated into the die 1500, and the metallization stack 1519 can be used to route I/O signals from the conductive contacts 1536 to transistors 1540 and any other components integrated into the die 1500.
Multiple integrated circuit devices 1500 may be stacked with one or more TSVs in the individual stacked devices providing connection between one of the devices to any of the other devices in the stack. For example, one or more high-bandwidth memory (HBM) integrated circuit dies can be stacked on top of a base integrated circuit die and TSVs in the HBM dies can provide connection between the individual HBM and the base integrated circuit die. Conductive contacts can provide additional connections between adjacent integrated circuit dies in the stack. In some embodiments, the conductive contacts can be fine-pitch solder bumps (microbumps).
In some embodiments, the circuit board 1602 may be a printed circuit board (PCB) including multiple metal (or interconnect) layers separated from one another by layers of dielectric material and interconnected by electrically conductive vias. The individual metal layers comprise conductive traces. Any one or more of the metal layers may be formed in a desired circuit pattern to route electrical signals (optionally in conjunction with other metal layers) between the components coupled to the circuit board 1602. In other embodiments, the circuit board 1602 may be a non-PCB substrate. The integrated circuit device assembly 1600 illustrated in
The package-on-interposer structure 1636 may include an integrated circuit component 1620 coupled to an interposer 1604 by coupling components 1618. The coupling components 1618 may take any suitable form for the application, such as the forms discussed above with reference to the coupling components 1616. Although a single integrated circuit component 1620 is shown in
The integrated circuit component 1620 may be a packaged or unpackaged integrated circuit product that includes one or more integrated circuit dies (e.g., the dic 1402 of
In embodiments where the integrated circuit component 1620 comprises multiple integrated circuit dies, they dies can be of the same type (a homogeneous multi-die integrated circuit component) or of two or more different types (a heterogeneous multi-die integrated circuit component). A multi-die integrated circuit component can be referred to as a multi-chip package (MCP) or multi-chip module (MCM).
In addition to comprising one or more processor units, the integrated circuit component 1620 can comprise additional components, such as embedded DRAM, stacked high bandwidth memory (HBM), shared cache memories, input/output (I/O) controllers, or memory controllers. Any of these additional components can be located on the same integrated circuit die as a processor unit, or on one or more integrated circuit dies separate from the integrated circuit dies comprising the processor units. These separate integrated circuit dies can be referred to as “chiplets”. In embodiments where an integrated circuit component comprises multiple integrated circuit dies, interconnections between dies can be provided by the package substrate, one or more silicon interposers, one or more silicon bridges embedded in the package substrate (such as Intel® embedded multi-die interconnect bridges (EMIBs)), or combinations thereof.
Generally, the interposer 1604 may spread connections to a wider pitch or reroute a connection to a different connection. For example, the interposer 1604 may couple the integrated circuit component 1620 to a set of ball grid array (BGA) conductive contacts of the coupling components 1616 for coupling to the circuit board 1602. In the embodiment illustrated in
In some embodiments, the interposer 1604 may be formed as a PCB, including multiple metal layers separated from one another by layers of dielectric material and interconnected by electrically conductive vias. In some embodiments, the interposer 1604 may be formed of an epoxy resin, a fiberglass-reinforced epoxy resin, an epoxy resin with inorganic fillers, a ceramic material, or a polymer material such as polyimide. In some embodiments, the interposer 1604 may be formed of alternate rigid or flexible materials that may include the same materials described above for use in a semiconductor substrate, such as silicon, germanium, and other group III-V and group IV materials. The interposer 1604 may include metal interconnects 1608 and vias 1610, including but not limited to through hole vias 1610-1 (that extend from a first face 1650 of the interposer 1604 to a second face 1654 of the interposer 1604), blind vias 1610-2 (that extend from the first or second faces 1650 or 1654 of the interposer 1604 to an internal metal layer), and buried vias 1610-3 (that connect internal metal layers).
In some embodiments, the interposer 1604 can comprise a silicon interposer. Through silicon vias (TSV) extending through the silicon interposer can connect connections on a first face of a silicon interposer to an opposing second face of the silicon interposer. In some embodiments, an interposer 1604 comprising a silicon interposer can further comprise one or more routing layers to route connections on a first face of the interposer 1604 to an opposing second face of the interposer 1604.
The interposer 1604 may further include embedded devices 1614, including both passive and active devices. Such devices may include, but are not limited to, capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, electrostatic discharge (ESD) devices, and memory devices. More complex devices such as radio frequency devices, power amplifiers, power management devices, antennas, arrays, sensors, and microelectromechanical systems (MEMS) devices may also be formed on the interposer 1604. The package-on-interposer structure 1636 may take the form of any of the package-on-interposer structures known in the art. In embodiments where the interposer is a non-printed circuit board
The integrated circuit device assembly 1600 may include an integrated circuit component 1624 coupled to the first face 1640 of the circuit board 1602 by coupling components 1622. The coupling components 1622 may take the form of any of the embodiments discussed above with reference to the coupling components 1616, and the integrated circuit component 1624 may take the form of any of the embodiments discussed above with reference to the integrated circuit component 1620.
The integrated circuit device assembly 1600 illustrated in
Additionally, in various embodiments, the electrical device 1700 may not include one or more of the components illustrated in
The electrical device 1700 may include one or more processor units 1702 (e.g., one or more processor units). As used herein, the terms “processor unit”, “processing unit” or “processor” may refer to any device or portion of a device that processes electronic data from registers and/or memory to transform that electronic data into other electronic data that may be stored in registers and/or memory. The processor unit 1702 may include one or more digital signal processors (DSPs), application-specific integrated circuits (ASICs), central processing units (CPUs), graphics processing units (GPUs), general-purpose GPUs (GPGPUs), accelerated processing units (APUs), field-programmable gate arrays (FPGAs), neural network processing units (NPUs), data processor units (DPUs), accelerators (e.g., graphics accelerator, compression accelerator, artificial intelligence accelerator), controller cryptoprocessors (specialized processors that execute cryptographic algorithms within hardware), server processors, controllers, or any other suitable type of processor units. As such, the processor unit can be referred to as an XPU (or xPU).
The electrical device 1700 may include a memory 1704, which may itself include one or more memory devices such as volatile memory (e.g., dynamic random access memory (DRAM), static random-access memory (SRAM)), non-volatile memory (e.g., read-only memory (ROM), flash memory, chalcogenide-based phase-change non-voltage memories), solid state memory, and/or a hard drive. In some embodiments, the memory 1704 may include memory that is located on the same integrated circuit die as the processor unit 1702. This memory may be used as cache memory (e.g., Level 1 (L1), Level 2 (L2), Level 3 (L3), Level 4 (L4), Last Level Cache (LLC)) and may include embedded dynamic random access memory (eDRAM) or spin transfer torque magnetic random access memory (STT-MRAM).
In some embodiments, the electrical device 1700 can comprise one or more processor units 1702 that are heterogeneous or asymmetric to another processor unit 1702 in the electrical device 1700. There can be a variety of differences between the processing units 1702 in a system in terms of a spectrum of metrics of merit including architectural, microarchitectural, thermal, power consumption characteristics, and the like. These differences can effectively manifest themselves as asymmetry and heterogeneity among the processor units 1702 in the electrical device 1700.
In some embodiments, the electrical device 1700 may include a communication component 1712 (e.g., one or more communication components). For example, the communication component 1712 can manage wireless communications for the transfer of data to and from the electrical device 1700. The term “wireless” and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communications channels, etc., that may communicate data through the use of modulated electromagnetic radiation through a nonsolid medium. The term “wireless” does not imply that the associated devices do not contain any wires, although in some embodiments they might not.
The communication component 1712 may implement any of a number of wireless standards or protocols, including but not limited to Institute for Electrical and Electronic Engineers (IEEE) standards including Wi-Fi (IEEE 802.11 family), IEEE 802.16 standards (e.g., IEEE 802.16-2005 Amendment), Long-Term Evolution (LTE) project along with any amendments, updates, and/or revisions (e.g., advanced LTE project, ultra mobile broadband (UMB) project (also referred to as “3GPP2”), etc.). IEEE 802.16 compatible Broadband Wireless Access (BWA) networks are generally referred to as WiMAX networks, an acronym that stands for Worldwide Interoperability for Microwave Access, which is a certification mark for products that pass conformity and interoperability tests for the IEEE 802.16 standards. The communication component 1712 may operate in accordance with a Global System for Mobile Communication (GSM), General Packet Radio Service (GPRS), Universal Mobile Telecommunications System (UMTS), High Speed Packet Access (HSPA), Evolved HSPA (E-HSPA), or LTE network. The communication component 1712 may operate in accordance with Enhanced Data for GSM Evolution (EDGE), GSM EDGE Radio Access Network (GERAN), Universal Terrestrial Radio Access Network (UTRAN), or Evolved UTRAN (E-UTRAN). The communication component 1712 may operate in accordance with Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Digital Enhanced Cordless Telecommunications (DECT), Evolution-Data Optimized (EV-DO), and derivatives thereof, as well as any other wireless protocols that are designated as 3G, 4G, 5G, and beyond. The communication component 1712 may operate in accordance with other wireless protocols in other embodiments. The electrical device 1700 may include an antenna 1722 to facilitate wireless communications and/or to receive other wireless communications (such as AM or FM radio transmissions).
In some embodiments, the communication component 1712 may manage wired communications, such as electrical, optical, or any other suitable communication protocols (e.g., IEEE 802.3 Ethernet standards). As noted above, the communication component 1712 may include multiple communication components. For instance, a first communication component 1712 may be dedicated to shorter-range wireless communications such as Wi-Fi or Bluetooth, and a second communication component 1712 may be dedicated to longer-range wireless communications such as global positioning system (GPS), EDGE, GPRS, CDMA, WiMAX, LTE, EV-DO, or others. In some embodiments, a first communication component 1712 may be dedicated to wireless communications, and a second communication component 1712 may be dedicated to wired communications.
The electrical device 1700 may include battery/power circuitry 1714. The battery/power circuitry 1714 may include one or more energy storage devices (e.g., batteries or capacitors) and/or circuitry for coupling components of the electrical device 1700 to an energy source separate from the electrical device 1700 (e.g., AC line power).
The electrical device 1700 may include a display device 1706 (or corresponding interface circuitry, as discussed above). The display device 1706 may include one or more embedded or wired or wirelessly connected external visual indicators, such as a heads-up display, a computer monitor, a projector, a touchscreen display, a liquid crystal display (LCD), a light-emitting diode display, or a flat panel display.
The electrical device 1700 may include an audio output device 1708 (or corresponding interface circuitry, as discussed above). The audio output device 1708 may include any embedded or wired or wirelessly connected external device that generates an audible indicator, such speakers, headsets, or earbuds.
The electrical device 1700 may include an audio input device 1724 (or corresponding interface circuitry, as discussed above). The audio input device 1724 may include any embedded or wired or wirelessly connected device that generates a signal representative of a sound, such as microphones, microphone arrays, or digital instruments (e.g., instruments having a musical instrument digital interface (MIDI) output). The electrical device 1700 may include a Global Navigation Satellite System (GNSS) device 1718 (or corresponding interface circuitry, as discussed above), such as a Global Positioning System (GPS) device. The GNSS device 1718 may be in communication with a satellite-based system and may determine a geolocation of the electrical device 1700 based on information received from one or more GNSS satellites, as known in the art.
The electrical device 1700 may include other output device(s) 1710 (or corresponding interface circuitry, as discussed above). Examples of the other output device(s) 1710 may include an audio codec, a video codec, a printer, a wired or wireless transmitter for providing information to other devices, or an additional storage device.
The electrical device 1700 may include other input device(s) 1720 (or corresponding interface circuitry, as discussed above). Examples of the other input device(s) 1720 may include an accelerometer, a gyroscope, a compass, an image capture device (e.g., monoscopic or stereoscopic camera), a trackball, a trackpad, a touchpad, a keyboard, a cursor control device such as a mouse, a stylus, a touchscreen, proximity sensor, microphone, a bar code reader, a Quick Response (QR) code reader, electrocardiogram (ECG) sensor, PPG (photoplethysmogram) sensor, galvanic skin response sensor, any other sensor, or a radio frequency identification (RFID) reader.
The electrical device 1700 may have any desired form factor, such as a hand-held or mobile electrical device (e.g., a cell phone, a smart phone, a mobile internet device, a music player, a tablet computer, a laptop computer, a 2-in-1 convertible computer, a portable all-in-one computer, a netbook computer, an ultrabook computer, a personal digital assistant (PDA), an ultra mobile personal computer, a portable gaming console, etc.), a desktop electrical device, a server, a rack-level computing solution (e.g., blade, tray or sled computing systems), a workstation or other networked computing component, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a stationary gaming console, smart television, a vehicle control unit, a digital camera, a digital video recorder, a wearable electrical device or an embedded computing system (e.g., computing systems that are part of a vehicle, smart home appliance, consumer electronics product or equipment, manufacturing equipment). In some embodiments, the electrical device 1700 may be any other electronic device that processes data. In some embodiments, the electrical device 1700 may comprise multiple discrete physical components. Given the range of devices that the electrical device 1700 can be manifested as in various embodiments, in some embodiments, the electrical device 1700 can be referred to as a computing device or a computing system.
Illustrative examples of the technologies described throughout this disclosure are provided below. Embodiments of these technologies may include any one or more, and any combination of, the examples described below. In some embodiments, at least one of the systems or components set forth in one or more of the preceding figures may be configured to perform one or more operations, techniques, processes, and/or methods as set forth in the following examples.
Example 1 includes a microelectronic assembly, comprising: one or more optical waveguides; a photodetector to convert optical signals received on the one or more optical waveguides into electric current; a transimpedance amplifier (TIA) to convert the electric current into voltage; and an electronic integrated circuit (EIC) to output a digital signal based on the voltage, wherein the EIC and the TIA are on separate integrated circuit (IC) dies.
Example 2 includes the microelectronic assembly of Example 1, further comprising a mesa structure under the TIA, wherein the mesa structure has a similar footprint as the TIA.
Example 3 includes the microelectronic assembly of Example 2, wherein: the mesa structure comprises at least one of a dielectric material or a metal; and the TIA is bonded to the mesa structure via a dielectric bond, a metal bond, or a hybrid dielectric and metal bond.
Example 4 includes the microelectronic assembly of any of Examples 1-3, further comprising a mesa structure under the photodetector, wherein the mesa structure has a similar footprint as the photodetector.
Example 5 includes the microelectronic assembly of any of Examples 1-4, wherein: the TIA is adjacent to the photodetector; or the TIA is over the photodetector.
Example 6 includes the microelectronic assembly of any of Examples 1-5, wherein: the TIA has a thickness of 5 micrometers (μm) or less; or the TIA has an area of less than 1 millimeter (mm) 2.
Example 7 includes the microelectronic assembly of any of Examples 1-6, further comprising: a modulator to modulate optical signals for transmission on the one or more optical waveguides; and a driver to control the modulator, wherein the driver and the EIC are on separate IC dies.
Example 8 includes the microelectronic assembly of Example 7, further comprising a mesa structure under the driver, wherein the mesa structure has a similar footprint as the driver.
Example 9 includes the microelectronic assembly of any of Examples 1-8, wherein the EIC comprises one or more of: carrier phase recovery circuitry; clock and data recovery circuitry; error correction circuitry; serializer and deserializer circuitry; equalizer circuitry; sampler circuitry; mixer circuitry, amplifier circuitry; temperature control circuitry; or analog-to-digital and digital-to-analog conversion circuitry.
Example 10 includes the microelectronic assembly of any of Examples 1-9, further comprising: a processing unit; and an optical transceiver to send and receive optical signals on behalf of the processing unit, wherein the optical transceiver comprises the one or more optical waveguides, the photodetector, the TIA, and the EIC.
Example 11 includes an electronic device, comprising: a plurality of integrated circuit (IC) components, wherein the plurality of IC components include: a plurality of optical waveguides; a ring resonator to modulate optical signals for transmission on one or more of the optical waveguides; a driver to control the ring resonator; a photodetector to convert optical signals received on one or more of the optical waveguides into electric current; and a transimpedance amplifier (TIA) to convert the electric current into voltage; and one or more mesa structures under one or more of the plurality of IC components, wherein individual mesa structures are under a corresponding IC component of the plurality of IC components and have a similar footprint as the corresponding IC component.
Example 12 includes the electronic device of Example 11, wherein: individual mesa structures comprise at least one of a dielectric material or a metal; and individual IC components are bonded to individual mesa structures via a dielectric bond, a metal bond, or a hybrid dielectric and metal bond.
Example 13 includes the electronic device of any of Examples 11-12, wherein: the plurality of IC components further include an electronic integrated circuit (EIC) to output a digital signal based on the voltage; and the EIC, the TIA, and the driver are on separate IC dies.
Example 14 includes the electronic device of any of Examples 11-13, wherein the electronic device is an optical transceiver.
Example 15 includes the electronic device of any of Examples 11-13, wherein the plurality of IC components further include a processing unit, wherein the processing unit comprises a central processing unit, a graphics processing unit, an application-specific integrated circuit, or a field-programmable gate array.
Example 16 includes a method, comprising: receiving a first substrate, wherein the first substrate comprises a release layer and a layer of integrated circuit (IC) components over the release layer, wherein the layer of IC components comprises one or more optical waveguides, ring resonators, drivers, photodetectors, transimpedance amplifiers, or electronic integrated circuits; receiving a second substrate, wherein the second substrate comprises one or more adhesive areas; partially bonding the first substrate to the second substrate, wherein one or more IC components on the first substrate are bonded to the one or more adhesive areas on the second substrate, wherein the one or more IC components are from the layer of IC components; and separating the first substrate from the second substrate, wherein the one or more IC components are separated from the first substrate and remain on the second substrate.
Example 17 includes the method of Example 16, further comprising, before separating the first substrate from the second substrate: weakening the release layer using a laser; or removing portions of the release layer using a laser.
Example 18 includes the method of any of Examples 16-17, wherein the release layer comprises at least one of a metallic layer or a dielectric layer.
Example 19 includes the method of any of Examples 16-18, wherein receiving the first substrate comprises forming the first substrate, wherein forming the first substrate comprises: receiving a base substrate; forming the release layer over the base substrate; forming or transferring the layer of IC components over the release layer; and partially singulating the layer of IC components.
Example 20 includes the method of any of Examples 16-19, wherein the one or more adhesive areas include one or more raised structures, wherein the one or more raised structures comprise at least one of a dielectric material or a metal.
While the concepts of the present disclosure are susceptible to various modifications and alternative forms, specific embodiments thereof have been shown by way of example in the drawings and are described herein in detail. It should be understood, however, that there is no intent to limit the concepts of the present disclosure to the particular forms disclosed, but on the contrary, the intention is to cover all modifications, equivalents, and alternatives consistent with the present disclosure and the appended claims.
In the drawings, some structural or method features may be shown in specific arrangements and/or orderings. However, it should be appreciated that such specific arrangements and/or orderings may not be required. Rather, in some embodiments, such features may be arranged in a different manner and/or order than shown in the illustrative figures. Additionally, the inclusion of a structural or method feature in a particular figure is not meant to imply that such feature is required in all embodiments and, in some embodiments, may not be included or may be combined with other features. Further, it should be understood that the various embodiments shown in the figures are illustrative representations and are not necessarily drawn to scale.
Moreover, the illustrations and/or descriptions of various embodiments may be simplified or approximated for ease of understanding, and as a result, they may not necessarily reflect the level of precision nor variation that may be present in actual embodiments. For example, while some figures generally indicate straight lines, right angles, and smooth surfaces, actual implementations of the disclosed embodiments may have less than perfect straight lines and right angles, and some features may have surface topography or otherwise be non-smooth, given real-world limitations of fabrication processes. Similarly, illustrations and/or descriptions of how components are arranged may be simplified or approximated for ease of understanding and may vary by some margin of error in actual embodiments (e.g., due to fabrication processes, etc.).
Unless otherwise specified, the use of the ordinal adjectives “first,” “second,” and “third,” etc., to describe a common object, merely indicate that different instances of like objects to which are being referred and are not intended to imply that the objects so described must be in a given sequence, either temporally, spatially, in ranking or in any other manner.
The terms “substantially,” “close,” “approximately,” “near,” and “about,” generally refer to being within +/−10% of a target value (unless otherwise specified). Similarly, terms describing spatial relationships, such as “perpendicular,” “orthogonal,” or “coplanar,” may refer to being substantially within the described spatial relationships (e.g., within +/−10 degrees of orthogonality).
Certain terminology may also be used in the foregoing description for the purpose of reference only, and thus are not intended to be limiting. For example, terms such as “upper,” “lower,” “above,” “below,” “bottom,” and “top” refer to directions in the drawings to which reference is made. Terms such as “front,” “back,” “rear,” and “side” describe the orientation and/or location of portions of the component within a consistent but arbitrary frame of reference which is made clear by reference to the text and the associated drawings describing the component under discussion. Such terminology may include the words specifically mentioned above, derivatives thereof, and words of similar import.
The terms “over”, “under”, “between”, “adjacent”, “to”, and “on” as used herein may refer to a relative position of one layer or component with respect to other layers or components. For example, one layer “over”, “under”, or “on” another layer, “adjacent” to another layer, or bonded “to” another layer may be directly in contact with the other layer or may have one or more intervening layers. One layer “between” layers may be directly in contact with the layers or may have one or more intervening layers.
The meaning of “a,” “an,” and “the” include plural references. The meaning of “in” includes “in” and “on.”
For the purposes of the present disclosure, phrases “A and/or B” and “A or B” mean (A), (B), or (A and B). For the purposes of the present disclosure, the phrase “A, B, and/or C” means (A), (B), (C), (A and B), (A and C), (B and C), or (A, B and C).
Views labeled “cross-sectional”, “profile” and “plan” correspond to orthogonal planes within a cartesian coordinate system. Thus, cross-sectional and profile views are taken in the x-z plane, and plan views are taken in the x-y plane. Typically, profile views in the x-z plane are cross-sectional views.
The term “package” generally refers to a self-contained carrier of one or more dice, where the dice are attached to or embedded in the package substrate, and may be encapsulated for protection, with integrated or wire-bonded interconnects between the dice, along with leads, pins, or bumps located on the external portions of the package substrate. The package may contain a single die, or multiple dice, providing respective functions. The package may be mounted on a printed circuit board for interconnection with other packaged integrated circuits and discrete components, forming a larger circuit.
The term “cored” generally refers to a substrate of an integrated circuit package built upon a board, card, or wafer comprising a non-flexible stiff material. Typically, a small printed circuit board is used as a core, upon which integrated circuit device and discrete passive components may be soldered. Typically, the core has vias extending from one side to the other, allowing circuitry on one side of the core to be coupled directly to circuitry on the opposite side of the core. The core may also serve as a platform for building up layers of conductors and dielectric materials.
The term “coreless” generally refers to a substrate of an integrated circuit package having no core. The lack of a core may allow for higher-density package architectures, as the through-vias may have relatively large dimensions and pitch compared to high-density interconnects.
The term “land side” generally refers to the side of the substrate of the integrated circuit package closest to the plane of attachment to a printed circuit board, motherboard, or other package. This is in contrast to the term “die side”, which generally refers to the side of the substrate of the integrated circuit package to which the die or dice are attached.
The terms “dielectric” and “dielectric material” generally refer to any type or number of non-electrically conductive materials. In some cases, dielectric material may be used to make up the structure of a package substrate. For example, dielectric material may be incorporated into an integrated circuit package as layers of laminate film or as a resin molded over integrated circuit dice mounted on the substrate.
The term “metallization” generally refers to metal layers formed on, over, and/or through the dielectric material of the package substrate. The metal layers are generally patterned to form metal structures such as traces and bond pads. The metallization of a package substrate may be confined to a single layer or in multiple layers separated by layers of dielectric.
The term “bond pad” generally refers to metallization structures that terminate integrated traces and vias in integrated circuit packages and dies. The term “solder pad” may be occasionally substituted for “bond pad” and may carry the same or similar meaning.
The term “bump” generally refers to a conductive layer or structure formed on a bond pad, which is typically made of solder or metal and has a round or curved shape, hence the term “bump”.
The term “substrate” generally refers to a planar platform comprising dielectric and/or metallization structures. A substrate may mechanically support and electrically couple one or more IC dies on a single platform, with encapsulation of the one or more IC dies by a moldable dielectric material. A substrate may include bumps or pads as bonding interconnects on one or both sides. For example, one side of the substrate, generally referred to as the “die side”, may include bumps or pads for chip or die bonding. The opposite side of the substrate, generally referred to as the “land side”, may include bumps or pads for bonding the package to a printed circuit board.
The term “assembly” generally refers to a grouping of parts into a single functional unit. For example, certain parts may be permanently bonded together, integrated together, and/or mechanically assembled (e.g., where parts may be removable) into a functional unit.
The terms “coupled” or “connected” means a direct or indirect connection, such as a direct electrical, mechanical, magnetic, or fluidic connection between the things that are connected or an indirect connection, through one or more passive or active intermediary devices.
The term “circuit” or “module” may refer to one or more passive and/or active components that are arranged to cooperate with one another to provide a desired function. The term “signal” may refer to at least one current signal, voltage signal, magnetic signal, or data/clock signal.
