Patent Application
20060024879
This invention generally relates to formation of MOSFET devices in integrated circuit manufacturing processes and more particularly to MOSFET devices and methods of forming the same to selectively provide strain-induced charge carrier band modification for enhanced charge carrier mobility and improved MOSFET device drive current.
Mechanical stresses are known to play a role in charge carrier mobility which affects drive current and Voltage threshold shifts. The effect of mechanical stresses is to induce a strain on a MOSFET channel region and thereby improve a MOSFET device drive current which is proportional to charge carrier mobility.
Generally, various manufacturing processes are known to introduce strain into the MOSFET device channel region. For example, strain may be introduced into the channel region by the use of selectively strained SiGe substrates. However, several integration problems inherent in SiGe processing technology as well as the cost of SiGe substrates remain issues limiting the cost-effective implementation of strained SiGe approaches to gain the benefits of strain-induced band modification.
Prior art processes have attempted to introduce offsetting stresses into the channel region by forming stressed dielectric layers over gate structures following a silicide formation process. These approaches have met with limited success, however, since the formation of the stressed dielectric layer of a particular type of stress e.g., tensile or compressive, has a degrading electrical performance effect on a CMOS device with an opposite type of polarity e.g., N vs. P majority charge carriers. For example, as NMOS device performance is improved by forming tensile stressed dielectric layers, PMOS device performance is typically degraded.
Other shortcomings in prior art approaches are the adverse affect of the dielectric stressed layers on subsequent gap filling ability of a subsequently deposited dielectric layers as well as associated thermal processing temperatures which detrimentally affect previously formed materials such as stressed dielectric layers and metal silicides. For example, typical processes of forming pre-metal dielectric (PMD) layers over stressed dielectric layers may lead to stress relaxation or thinning of stressed dielectric layers making device performance improvement, if any, unpredictable.
In addition, prior art processes in forming stressed dielectric layers have the limitation of requiring different processing tools for a given stress type, thereby increasing the cost of production and reducing throughput. In addition, prior art approaches of forming stressed dielectric layers have been limited by the range of stress levels that may be formed, typically depending primarily on thickness to achieve a desired stress level. When producing highly stressed dielectric layers, this approach has the offsetting effect of limiting a gap filling ability in a subsequent PMD layer deposition process thereby leading to the formation of voids, compromising device yield and reliability.
These and other shortcomings demonstrate a need in the semiconductor device integrated circuit manufacturing art for improved strained channel MOSFET devices and methods for forming the same to improve both NMOS and PMOS device performance, reliability, and yield.
It is therefore an object of the present invention to provide improved strained channel MOSFET devices and methods for forming the same to improve both NMOS and PMOS device performance, reliability, and yield, while overcoming other shortcomings of the prior art.
To achieve the foregoing and other objects, and in accordance with the purposes of the present invention, as embodied and broadly described herein, the present invention provides a MOSFET device pair with improved drive current and a method for producing the same to selectively introduce strain into a respective N-type and P-type MOSFET device channel region.
In a first embodiment, the method includes providing a first and second MOSFET device having a respective first polarity and second polarity opposite from the first polarity selected from the group consisting of P and N type on a semiconducting substrate; forming a first stressed nitride layer having a first stress type selected from the group consisting of compressive and tensile stress over the first and second MOSFET device active areas; removing the first stressed nitride layer overlying the second MOSFET device active area; forming a second stressed nitride layer having a second stress type opposite the first stress type over the first and second MOSFET device active areas; removing the second stressed nitride layer overlying the first MOSFET device active area; and, forming a dielectric insulating layer over the first and second MOSFET device active areas having a less compressive or tensile stress.
These and other embodiments, aspects and features of the invention will be better understood from a detailed description of the preferred embodiments of the invention which are further described below in conjunction with the accompanying Figures.
BRIEF DESCRIPTION OF THE DRAWINGS
Although the method of the present invention is explained with reference to exemplary NMOS and PMOS MOSFET devices, it will be appreciated that the method of the present invention may be applied to the formation of any MOSFET device where a strain is controllably introduced into a charge carrier channel region by selective formation of stressed dielectric layers overlying the respective NMOS and/or PMOS device regions with subsequent preferred PMD layer formation.
Referring to
Still referring to
The gate dielectric portions e.g., 16A and 16B may be formed of silicon oxide, silicon oxynitride, silicon nitride, nitrogen doped silicon oxide, high-K dielectrics, or combinations thereof. The high-K dielectrics may include metal oxides, metal silicates, metal nitrides, transition metal-oxides, transition metal silicates, metal aluminates, and transition metal nitrides, or combinations thereof. The gate dielectric portions e.g., 16A and 16B may be formed by any process known in the art, e.g., thermal oxidation, nitridation, sputter deposition, or chemical vapor deposition. When using a high permittivity (high-K) gate dielectric, the dielectric constant is preferably greater than about 8. For example, the high-K dielectric may be include one or more of aluminum oxide (e.g., Al2O3), hafnium oxide (e.g., HfO2), hafnium oxynitride (e.g., HfON), hafnium silicate (e.g., HfSiO4), zirconium oxide (e.g., ZrO2), zirconium oxynitride (e.g., ZrON), zirconium silicate (e.g., ZrSiO2), yttrium oxide (e.g., Y2O3), lanthanum oxide (e.g., La2O3), cerium oxide (e.g., CeO2), titanium oxide (e.g., TiO2), tantalum oxide (e.g., Ta2O5), or combinations thereof.
The gate electrode portions e.g., 18A and 18B may be formed of polysilicon, polysilicon-germanium, metals, metal silicides, metal nitrides, or conductive metal oxides. In a preferred embodiment, the gate electrodes are formed of polysilicon. Metals silicides as explained below are preferably formed be used in an upper portion of the gate electrodes e.g., 16A, 16B to form conductive contact regions. In a preferred embodiment, the contact regions are formed of metal silicides including cobalt silicide (e.g., CoSi2) or nickel silicide (e.g., NiSi), as the method of the present invention which includes forming a stressed nitride contact etch stop layer by a mixed frequency PECVD process as explained below overcomes processing difficulties of the prior art in using these metal silicide materials, particularly NiSi.
Following formation of the gate electrodes, source/drain extension (SDE) regions e.g., 20A and 20B on either side of a channel region are formed by a conventional ion implant process adjacent the gate structures beneath the silicon substrate surface according to a low energy ion implantation. It will be appreciated that offset spacer liner layers e.g., 21A, 21B, of silicon oxide, silicon nitride, or silicon oxynitride may be formed adjacent the gate structures prior to or following formation of the SDE regions.
Still referring to
Following sidewall spacer formation, the NMOS and PMOS device areas are sequentially doped according to a conventional high dose ion implantation (HDI) process to form the high density implant portions of doped source/drain (S/D) regions e.g., 20C and 20D in the substrate 12 adjacent the sidewall spacers.
Still referring to
Referring to
For example, referring briefly to
Conventional reactive gas (plasma source gas) feeds, e.g., 46, a gas dispersion showerhead e.g., 48, and dielectric window (not shown) are provided in an upper portion of the plasma chamber 42. The mixed frequency PECVD reactor is preferably provided with a dual frequency RF source power generators e.g., 50A and 50B, one RF power source e.g., 50A a low frequency power source for generating RF power at a frequency of about 300 to about 500 KHz and a high frequency power source e.g., 50B for generating RF power at a frequency of about 13.56 MHz for generating a mixed frequency RF power signal, e.g., through frequency mixer 50C, which is coupled to plasma chamber 42 for generating a plasma.
For example, the mixed frequency PECVD deposition method includes supplying a precursor such as silane (SiH4), NH3, and N2 at a deposition temperature of from about 300° C. to about 600° C., more preferably less than about 550° C. at pressures of from about 2 Torr to about 5 Torr and mixed frequency RF powers of from about 100 Watts to about 1000 Watts. It will be appreciated other silane precursors or silane precursor mixtures alternatively or in addition to silane (SiH4) may be used such as disilane (Si2H6), trisilane (Si3H8), dichlorosilane (SiH2Cl2), trichlorosilane (SiHCl3), and the like.
It will be appreciated that the level of stress can be varied by a number of factors, the most important being the mixed frequency signal including the frequency of the lower frequency RF power source to produce a mixed frequency RF source component. For example, the compressive stress of the stressed nitride layers increases with increasing power and low frequency component of the mixed frequency RF power signal. Other factors, such as the thickness of the stressed dielectric layer, for example from about 100 Angstroms to about 1000 Angstroms, more preferably from about 100 Angstroms to about 700 Angstroms in thickness, can also be varied to achieve a desired stress level. In addition, the relative reactant flow rates, deposition pressure, and temperature may be varied to alter the composition of the dielectric layer thereby further selectively producing a desired stress level. Advantageously, by using a mixed frequency method to produce the stressed nitride layer 30A, a single deposition tool may be advantageously used to achieve both tensile and compressive stress films as explained below.
Preferably the stressed nitride layer 30A is formed with a compressive or tensile stress level (absolute value) greater than about 7×10ˆ9 dynes/cm2. It will be appreciated that a tensile stress level is represented by a positive value and a compressive stress represented by a negative value.
Referring to
Referring to
Referring to
Referring to
Advantageously, by avoiding a high sputter rate HDP-CVD process, thinning of the stressed nitride layers is avoided thereby preserving the stress type and level formed in the stressed nitride layers e.g., 30A and 30B. Following deposition of the PMD layer conventional steps such as CMP planarization step and conventional photolithographic patterning and etching processes are carried out to form metal filled contacts e.g., 36A, 36B, 36C to form electric contact wiring to the source/drain and/or gate electrode metal salicide regions. Advantageously, deterioration of metal silicide regions, especially NiSi is avoided compared to prior art processes by forming the stressed nitride layers e.g., 30A and 30B at temperatures less than about 550° C.
Thus, a method has been presented for improving NMOS and PMOS device performance by selectively forming stressed nitride layers of a desired type over NMOS and PMOS devices to introduce strain into a MOSFET device channel region. By using a mixed frequency PECVD deposition method, a wider range of stress levels may be more precisely achieved as well as forming nitride layers with either type of stress, e.g., compressive or tensile. In addition, step coverage is improved by the mixed frequency method of formation of stressed nitride layers. Moreover, the lower deposition temperatures by the mixed frequency PECVD process required to achieve a desired stress level compared to prior art deposition processes avoids detrimental deterioration of NiSi or CoSi2 resistivity. Preferred formation of the PMD layer avoids stress relaxation or diminishing of the stress levels of the stressed nitride layers.
Device performance has been demonstrably improved. For example, MOSFET devices with CoSi2 or NiSi metal silicides with the formation of stressed nitride layers of greater than about 7×109 dynes/cm2 have shown an improvement of about 2.5% to about 6.5% improvement in drive current (Idsat-Ioff) compared to prior art single frequency PECVD deposition methods. Additionally, formation of the PMD layer according to preferred embodiments, further improves drive current without accompany drive current degradation effects for opposite polarity devices.
Referring to
The preferred embodiments, aspects, and features of the invention having been described, it will be apparent to those skilled in the art that numerous variations, modifications, and substitutions may be made without departing from the spirit of the invention as disclosed and further claimed below.
