Kelley, "Imbedded Memory Test Methods", IBM Tech. Discl. Bulletin, vol. 21, No. 12, May 1979, pp. 4911-4913. |
"A Users Handbook of Semiconductor Memories" by E. R. Hnatek, 1977, John Wiley & Sons, Inc., p. 447. |
"Electronic Chip-In-Place Test" by P. Goel and M. T. McMahon, AC, IEE Nineteenth Design Automation Conference Proceedings, Jun. 14-16, 1982, IEEE Catalog No. 82CH1759-0 ACM Order No. 477820, pp. 482-488. |
"Logic Card Test Apparatus" by P. B. Shattuck, IBM TDB, vol. 13, No. 3, Aug. 1970, p. 605. |
"Integrated Circuit Testing" by P. V. Jordan, IBM TDB, vol. 13, No. 5, Oct. 1970, pp. 1093-1094. |
"Pattern Generating System" by E. Legnard et al., IBM TDB, vol. 14, No. 2, Jul. 1971, pp. 482-484. |
"Arrangement for Minimized Functional Test of LSI Logic Chips" by F. Tsui, IBM TDB, vol. 15, No. 9, Feb. 1973, pp. 2870-2872. |
"Single Clock Shift Register Latch" by T. W. Williams, IBM TDB, vol. 16, No. 6, Nov. 1973, p. 1961. |
"Comparative Circuit Tester" by E. B. Carey et al., IBM TDB, vol. 16, No. 10, Mar. 1974, pp. 3151-3152. |
"Troubleshooting Large-Scale Integrated Circuit Units" by L. D. Howe et al., IBM TDB, vol. 17, No. 7, Dec. 1974, pp. 1941-1944. |
"Testing LSI Memory Arrays Using On-Chip I/O Shift Register Latches" by P. S. Balasubramanian et al., IBM TDB, vol. 17, No. 7, Dec. 1974, pp. 2019-2020. |
"Combined Test Scanning and Serial-Deserializing Shift Register" by B. M. Ross et al., IBM TDB, vol. 19, No. 2, Jul. 1976, pp. 480-481. |
"Memory Testing" by J. Bappert et al., IBM TDB, vol. 19, No. 5, Oct. 1976, p. 1621. |
"Pattern Generator for a Multipart Number Test System" by J. N. Arnold et al., IBM TDB, vol. 19, No. 9, Feb. 1977, pp. 3487-3488. |
"Delay Testing and Diagnosis of LSSD Shift Register Strings" by K. E. Dimitri, IBM TDB, vol. 20, No. 1, Jun. 1977, pp.307-312. |
"Selective Control of Off-Subassembly Drivers to Test Logic Systems" by F. Hsu et al., IBM TDB, vol. 20, No. 11B, Apr. 1978, pp. 4728-4730. |