Patent Application
20220406943
The present disclosure relates to a semiconductor device suitable for use in a power device and the like. The present disclosure also relates to a crystal growth method capable of obtaining crystal suitable for use in a power device and the like.
Hitherto, there has been a problem in that a crack and a lattice defect occur when crystal growth is performed on a heterogeneous substrate. With regard to this problem, the alignment of the lattice constant and the thermal expansion coefficient between a substrate and a film, for example, has been examined. A film formation approach such as ELO has also been examined when such misalignment occurs.
A method of forming a buffer layer on the heterogeneous substrate and causing the crystal growth of a zinc oxide semiconductor layer on the buffer layer has been known. A method of forming a nanodot mask on the heterogeneous substrate and then forming a monocrystalline semiconductor material layer has been known. An approach of causing the crystal growth of GaN on sapphire via a nano-column of GaN has been known. An approach of reducing defects such as pits by causing the crystal growth of GaN on Si(111) with use of a periodic SiN interlayer has been known.
However, in all of the technologies, it has been difficult to obtain a high-quality epitaxial film due to the film formation speed being wrong, a crack, a dislocation, a warp, and the like being generated in the substrate, or a dislocation, a crack, and the like occurring in the epitaxial film, for example. There also has been trouble regarding the diameter increase of the substrate and the thickening of the epitaxial film.
A semiconductor device using gallium oxide (Ga2O3) having a great band gap has been gathering attention as a next-generation switching element capable of realizing high voltage resistance, low loss, and high thermal resistance and has been expected to be applied to a power semiconductor device such as an inverter. Application as a light receiving/emitting apparatus such as an LED and a sensor has also been expected due to the wide band gap. It becomes possible to perform band gap control by obtaining mixed crystal formed by mixing each of indium or aluminum or a combination of indium and aluminum with the gallium oxide, and the gallium oxide configures an extremely attractive family of material as an InAlGaO-based semiconductor. Here, InAlGaO-based semiconductors indicate InXAlYGaZO3 (0≤X≤2, 0≤Y≤2, 0≤Z≤2, X+Y+Z=1.5 to 2.5) and may be regarded as a family of power device including gallium oxide.
However, gallium oxide has β-gallia structure in the most stabilized phase. Therefore, it is difficult to form a crystal film having a corundum structure unless a special film formation method is used, and there also still has been many problems regarding the crystal quality and the like. With respect to the above, several examinations have currently been made regarding the film formation of a crystalline semiconductor having a corundum structure.
According to an example of the present disclosure, there is provided a semiconductor device, including at least: a semiconductor layer; and a gate electrode that is arranged directly or via another layer on the semiconductor layer, the semiconductor device being configured in such a manner as to cause a current to flow in the semiconductor layer at least in a first direction that is along with an interface between the semiconductor layer and the gate electrode, the semiconductor layer having a corundum structure, a direction of an m-axis in the semiconductor layer being the first direction.
According to an example of the present disclosure, there is provided a semiconductor device, including at least: a semiconductor layer having a corundum structure; a first electrode disposed on a first plane side of the semiconductor layer; and a second electrode disposed on a second plane side that is a side opposite from the first plane side, the first plane being an m-plane, the second electrode being longer than the first electrode in at least a first direction, and the first direction being a c-axis direction of the semiconductor layer.
Thus, a semiconductor device of the present disclosure is excellent in the semiconductor property, in particular, the electrical property.
According to an example of the present disclosure, there is provided a crystal growth method, including causing crystal growth of crystal having a corundum structure on a c-plane of a crystal substrate for crystal growth having a corundum structure, the crystal substrate having an uneven portion provided thereon such that a dislocation in accordance with the crystal growth further extends in an m-axis direction than in an a-axis direction.
Thus, in a method of the present disclosure, it becomes possible to industrially form the crystal, the crystal film, and/or the semiconductor layer in which dislocation is reduced in an advantageous manner.
The inventors of the present disclosure found out that the electrical property has anisotropy in the relationship between a crystal axis of gallium oxide crystal having a corundum structure and the direction in which the current flows, and have succeeded in inventing a semiconductor device including at least: a semiconductor layer; and a first electrode and a second electrode each disposed on a first plane side of the semiconductor layer. In the semiconductor device, current flows in a first direction from the first electrode toward the second electrode in the semiconductor layer, the semiconductor layer has a corundum structure, and a direction of an m-axis of the semiconductor layer is parallel to the first direction.
The inventors of the present disclosure found out that the electrical property has anisotropy in the relationship between the crystal axis of the gallium oxide crystal having a corundum structure and the direction in which the current flows, and have succeeded in inventing a semiconductor device including at least: a semiconductor layer having a corundum structure; a first electrode disposed on a first plane side of the semiconductor layer; and a second electrode disposed on a second plane side that is a side opposite from the first plane side. In the semiconductor device, the second electrode is longer than the first electrode in at least a first direction, the first plane is an m-plane, and the first direction is a c-axis direction of the semiconductor layer.
The inventors of the present disclosure found a crystal growth method including causing crystal growth of crystal having a corundum structure on a c-plane of a crystal substrate for crystal growth having a corundum structure, the crystal substrate having an uneven portion provided thereon such that a dislocation in accordance with the crystal growth further extends in an m-axis direction than in an a-axis direction. The inventors of the present disclosure have found that such crystal growth method is capable of reducing dislocation by utilizing the anisotropy of the dislocation.
Embodiments of the present disclosure will be described below with reference to the accompanying drawings. In the following description, the same parts and components are designated by the same reference numerals. The present embodiment includes, for example, the following disclosures.
A semiconductor device, including at least: a semiconductor layer; and a gate electrode that is arranged directly or via another layer on the semiconductor layer, the semiconductor device being configured in such a manner as to cause a current to flow in the semiconductor layer at least in a first direction that is along with an interface between the semiconductor layer and the gate electrode, the semiconductor layer having a corundum structure, a direction of an m-axis in the semiconductor layer being the first direction.
A semiconductor device, including at least: a semiconductor layer having a corundum structure; a first electrode disposed on a first plane side of the semiconductor layer; and a second electrode disposed on a second plane side that is a side opposite from the first plane side, the first plane being an m-plane, the second electrode being longer than the first electrode in at least a first direction, and the first direction being a c-axis direction of the semiconductor layer.
The semiconductor device according to [Structure 1] or [Structure 2], wherein the semiconductor layer includes a metal oxide containing at least one metal selected from gallium, indium, rhodium, iridium, and aluminum.
The semiconductor device according to [Structure 1] or [Structure 2], wherein a major component of the semiconductor layer is metal oxide containing at least gallium.
The semiconductor device according to [Structure 1], wherein the semiconductor layer has a carrier concentration of 1×1019/cm3 or less.
The semiconductor device according to [Structure 2], wherein the first plane is a c-plane.
The semiconductor device according to [Structure 1], wherein the semiconductor layer includes at least a dislocation that extends in the first direction.
The semiconductor device according to [Structure 1], wherein the semiconductor layer does not substantially include a dislocation that extends in a direction that is vertical or substantially vertical to the first direction.
The semiconductor device according to any one of [Structure 1] to [Structure 8], wherein the semiconductor device is a power device.
The semiconductor device according to [Structure 9], wherein the semiconductor device is a power module, an inverter, or a converter.
The semiconductor device according to [Structure 9], wherein the semiconductor device is a power card.
The semiconductor device according to [Structure 10], further including a cooler and an insulation member, wherein the cooler is provided on each of both sides of the semiconductor layer via at least the insulation member.
The semiconductor device according to [Structure 11], wherein: a heat release layer is provided on each of both sides of the semiconductor layer; and the cooler is provided on an outer side of the heat release layer via at least the insulation member.
A semiconductor system, including a semiconductor device, wherein the semiconductor device is the semiconductor device according to any one of [Structure 1] to [Structure 13].
A crystal growth method, including causing crystal growth of crystal having a corundum structure on a c-plane of a crystal substrate for crystal growth having a corundum structure, the crystal substrate having an uneven portion provided thereon such that a dislocation in accordance with the crystal growth further extends in an m-axis direction than in an a-axis direction.
The method according to any one of [Structure 15], wherein the crystal contains metal oxide containing at least one metal selected from gallium, indium, rhodium, iridium, and aluminum.
The method according to [Structure 15] or [Structure 16], wherein a major component of the crystal is metal oxide containing at least gallium.
The method according to any one of [Structure 15] to [Structure 17], wherein the uneven portion includes at least two or more of inclined planes that are m-planes adjacent to each other.
The method according to any one of [Structure 15] to [Structure 18], wherein the uneven portion includes at least two or more of inclined planes that are m-planes facing each other.
A semiconductor device in one embodiment of the present disclosure includes at least: a semiconductor layer; and a first electrode and a second electrode each disposed on a first plane side of the semiconductor layer. In the semiconductor device, current flows in a first direction from the first electrode toward the second electrode in the semiconductor layer, the semiconductor layer has a corundum structure, and a direction of an m-axis of the semiconductor layer is parallel to the first direction.
A semiconductor device in another embodiment of the present disclosure includes at least: a semiconductor layer having a corundum structure; a first electrode disposed on a first plane side of the semiconductor layer; and a second electrode disposed on a second plane side that is a side opposite from the first plane side. In the semiconductor device, the first plane is an m-plane, the second electrode is longer than the first electrode in at least a first direction, and the first direction is a c-axis direction of the semiconductor layer.
In the embodiment of the present disclosure, the semiconductor layer contains metal oxide containing at least one metal selected from gallium, indium, rhodium, iridium, and aluminum. In the embodiment of the present disclosure, it becomes possible to exhibit a semiconductor property that is better in terms of high voltage resistance and the like when the major component of the semiconductor layer is metal oxide containing at least gallium. The “major component” means that the metal oxide is contained by 50% or more, preferably 70% or more, and more preferably 90% or more at atomic ratio with respect to all components in the semiconductor layer and may be 100% depending on the embodiment. It is preferred that the metal oxide contain at least gallium and further contain indium, rhodium, or iridium. It is also preferred that the metal oxide contain at least gallium and further contain indium or/and aluminum. It is more preferred that the metal oxide contain at least gallium because it becomes possible to cause the property as a power device such as a switching property to be better. In the embodiment of the present disclosure, it is preferred that the first plane be a c-plane because it becomes possible to cause the electrical property to be better.
One example of an embodiment of a crystal growth method of the present disclosure is a crystal growth method including causing crystal growth of crystal having a corundum structure on a c-plane of a crystal substrate for crystal growth having a corundum structure, the crystal substrate having an uneven portion provided thereon such that a dislocation in accordance with the crystal growth further extends in an m-axis direction than in an a-axis direction. One example of the embodiment of the present disclosure is a crystal growth method that is a method of causing crystal growth of crystal having a corundum structure with use of a crystal substrate for crystal growth. In the crystal growth method, an uneven portion that causes a dislocation that extends in an m-axis direction of the crystal to move from a direction of the crystal growth is provided on a crystal-growth-plane side of the crystal substrate. In the embodiment of the present disclosure, it is preferred that a protruding portion of the uneven portion be a mask. It is preferred that the mask be a mask containing TiO2. It is preferred that a principal plane of the crystal substrate on which the uneven portion is provided be a c-plane. As one example of the embodiment, it is preferred that the crystal contain metal oxide containing at least one metal selected from gallium, indium, rhodium, chromium, iridium, and aluminum, and it is more preferred that the crystal contain metal oxide containing at least one metal selected from gallium, indium, rhodium, iridium, and aluminum. In the embodiment of the present disclosure, it is more preferred that the major component of the crystal be metal oxide containing at least gallium. It is preferred that the crystal growth be performed by at least one method selected from CVD, MOCVD, MOVPE, mist CVD, mist epitaxy, MBE, HVPE, pulsed growth, and ALD. As another example of the embodiment of the present disclosure, it is also preferred that the uneven portion include at least two or more inclined planes that are m-planes adjacent to each other. In the embodiment, it is preferred that the uneven portion include at least two or more of inclined planes that are m-planes facing each other. By causing crystal growth of the crystal having a corundum structure such that the direction of the crystal growth includes the c-axis direction, the a-axis direction, and the m-axis direction, it becomes possible to easily obtain crystal in which dislocation is reduced in the a-axis direction.
The crystal growth method in a preferred embodiment of the present disclosure is advantageous in obtaining crystal with excellent semiconductor property, and the crystal is suitably usable as a semiconductor layer in a semiconductor device.
It is preferred that the semiconductor layer be a crystalline oxide semiconductor layer and include a crystalline oxide semiconductor. It is preferred that the crystalline oxide semiconductor contain the metal oxide and contain at least gallium as described above, and it is more preferred that the crystalline oxide semiconductor contain gallium oxide and mixed crystal thereof as the major component. The crystal structure and the like of the crystalline oxide semiconductor are not particularly limited. However, in the present disclosure, it is preferred that the crystalline oxide semiconductor contain metal oxide having a corundum structure as the major component. The metal oxide is not particularly limited, but preferably contains at least one type or two or more types of metal from period 4 to period 6 in the periodic table, more preferably contains at least gallium, indium, rhodium, or iridium, and most preferably contains gallium. In the present disclosure, it is also preferred that the metal oxide contain gallium, indium, or/and aluminum. The metal oxide containing gallium includes α-Ga2O3 or mixed crystal thereof, for example. The semiconductor layer containing such preferred metal oxide as the major component may have better crystal property and heat release property and may also have even better semiconductor property. For example, when the metal oxide is α-Ga2O3, the atomic ratio of gallium contained in the semiconductor layer only needs to be as follows. Specifically, α-Ga2O3 only needs to be contained in the semiconductor layer at a rate of 50% or more with respect to all metal components of the semiconductor layer. In the present disclosure, the atomic ratio of gallium in the metal components of the semiconductor layer is preferably 70% or more and more preferably 80% or more with respect to all of the metal components in the semiconductor layer. The semiconductor layer may be monocrystal or may be polycrystal. The semiconductor layer is normally in a film form but is not particularly limited unless it interferes with the present disclosure and may be in a plate form or a sheet form.
The semiconductor layer may also contain a dopant. The dopant is not particularly limited unless it interferes with the present disclosure. The dopant may be an n-type dopant or a p-type dopant. Examples of the n-dopant include tin, germanium, silicon, titanium, zirconium, vanadium, or niobium. The carrier concentration may be set, as appropriate. Specifically, the carrier concentration may be from about 1×1016/cm3 to about 1×1022/cm3, for example, or the carrier concentration may be a low concentration of about 1×1017/cm3 or less, for example. As one example of the embodiment, for example, the carrier concentration of the semiconductor layer may be contained by a high concentration of about 1×1020/cm3 or more. However, in the embodiment of the present disclosure, it becomes possible to cause the anisotropy to be more effective and the semiconductor property to be more satisfactory when the carrier concentration of the semiconductor layer becomes lower. Therefore, the carrier concentration is preferably 1×1019/cm3 or less, more preferably 5×1018/cm3 or less, and most preferably 1×1018/cm3 or less, for example.
The semiconductor layer is obtainable by a suitable film formation method as follows, for example. For example, the semiconductor layer is obtainable by producing a semiconductor device by forming the semiconductor layer by causing epitaxial crystal growth by mist CVD or mist epitaxy such that the current flows in the first direction from the first electrode toward the second electrode with use of a crystal substrate in which a second edge is set to be shorter than a first edge. The first direction is the m-axis direction.
The crystal substrate is not particularly limited unless it interferes with the present disclosure and may be a well-known substrate. The crystal substrate may be an insulator substrate, a conductive substrate, or a semiconductor substrate. The crystal substrate may be a monocrystalline substrate or a polycrystalline substrate. Examples of the crystal substrate include a substrate containing a crystal substance having a corundum structure as the major component. The expression of “major component” means that the crystal substance is contained by 50% or more, preferably 70% or more, and more preferably 90% or more at composition ratio in the substrate. Examples of the crystal substrate having a corundum structure include a sapphire substrate, an α-type gallium oxide substrate, and an α-type mixed crystal substrate which contains Ga2O3 and Al2O3 and in which Al2O3 is more than 0 wt % and equal to or less than 60 wt %.
In the present disclosure, it is preferred that the crystal substrate be a sapphire substrate. Examples of the sapphire substrate include a c-plane sapphire substrate, an m-plane sapphire substrate, an a-plane sapphire substrate, and an r-plane sapphire substrate. However, in the embodiment of the present disclosure, it is preferred that the c-plane sapphire substrate and a c-plane α-Ga2O3 substrate be used. The sapphire substrate may have an off-angle. The off-angle is not particularly limited and is 0.01 degrees or more, for example, but is preferably 0.2 degrees or more and more preferably from 0.2 degrees to 12 degrees. It is also preferred that the sapphire substrate be a c-plane sapphire substrate having an off-angle of 0.2 degrees or more.
The thickness of the crystal substrate is not particularly limited but is normally from 10 μm to 20 mm and is more preferably from 10 μm to 1000 μm.
In the present disclosure, the direction of the crystal growth and the like may be controlled with use of an ELO mask such that the second edge easily becomes shorter than the first edge, the linear thermal expansion coefficient of a first crystal axial direction easily becomes smaller than the linear thermal expansion coefficient of a second crystal axial direction, a first edge direction easily becomes parallel or substantially parallel to the first crystal axial direction, and a second edge direction easily becomes parallel or substantially parallel to the second crystal axial direction in the semiconductor layer.
Examples of the suitable shape of the crystal substrate include polygonal shapes such as a triangular shape, a quadrilateral shape (for example, a rectangular shape or a trapezoidal shape), a pentagonal shape, or a hexagonal shape, a U-shape, an inverted U-shape, an L-shape, or a squared U-shape.
In the present disclosure, other layers such as a buffer layer and a stress alleviation layer may be provided on the crystal substrate. Examples of the buffer layer include a layer formed by metal oxide having the same crystal structure as the crystal structure of the crystal substrate or the semiconductor layer. Examples of the stress alleviation layer include an ELO mask layer.
A preferred aspect of the crystal substrate suitably used in the present disclosure is described below with reference to the drawings.
Means for epitaxial crystal growth is not particularly limited unless it interferes with the present disclosure and may be well-known means. Examples of the epitaxial crystal growth means include CVD, MOCVD, MOVPE, mist CVD, mist epitaxy, MBE, HVPE, pulsed growth, or ALD. In the present disclosure, it is preferred that the epitaxial crystal growth means be mist CVD or mist epitaxy.
The mist CVD or the mist epitaxy is performed by atomizing a raw material solution containing metal (atomization process), causing droplets to float and carrying the obtained atomized droplets to the vicinity of the crystal substrate by carrier gas (carrying process), and then causing thermal reaction of the atomized droplets (film formation process).
The raw material solution is not particularly limited as long as metal is contained as the raw material for film formation and atomization is possible and may contain an inorganic material or an organic material. The metal may be elemental metal or a metal compound and is not particularly limited unless it interferes with the present disclosure. However, examples of the metal include one type or two or more types of metal selected from gallium (Ga), iridium (Ir), indium (In), rhodium (Rh), aluminum (Al), gold (Au), silver (Ag), platinum (Pt), copper (Cu), iron (Fe), manganese (Mn), nickel (Ni), palladium (Pd), cobalt (Co), ruthenium (Ru), chromium (Cr), molybdenum (Mo), tungsten (W), tantalum (Ta), zinc (Zn), lead (Pb), rhenium (Re), titanium (Ti), tin (Sn), magnesium (Mg), calcium (Ca), and zirconium (Zr). However, in the present disclosure, the metal preferably contains at least one type or two or more types of metal in period 4 to period 6 of the periodic table, and more preferably contains at least gallium, indium, rhodium, or iridium. In the present disclosure, it is also preferred that the metal contain gallium, indium, or/and aluminum. By using the preferred metal as above, it becomes possible to perform film formation of the semiconductor layer usable in the semiconductor device and the like in a more suitable manner.
In the present disclosure, as the raw material solution, a raw material solution obtained by causing the metal to be dissolved or dispersed in an organic solvent or water in a form of a complex or salt is suitably usable. Examples of the form of a complex include an acetylacetonato complex, a carbonyl complex, an ammine complex, and a hydride complex. Examples of the form of salt include organometallic salt (for example, metal acetate salt, metal oxalate salt, and metal citrate salt), metal sulfate salt, metal nitrate salt, metal phosphate salt, and metal halide salt (for example, metal chloride salt, metal bromide salt, and metal iodine salt).
The solvent of the raw material solution is not particularly limited unless it interferes with the present disclosure and may be an inorganic solvent such as water, an organic solvent such as alcohol, or a mixed solvent of an inorganic solvent and an organic solvent. In the present disclosure, it is preferred that the solvent contain water.
In the raw material solution, additives such as hydrohalic acid and oxidant may be mixed. Examples of the hydrohalic acid include hydrobromic acid, hydrochloric acid, and hydriodic acid. Examples of the oxidant include peroxide such as hydrogen peroxide (H2O2), sodium peroxide (Na2O2), barium peroxide (BaO2), benzoyl peroxide (C6H5CO)2O2, and organic peroxide such as hypochlorous acid (HClO), perchloric acid, nitric acid, ozone water, peracetic acid, and nitrobenzene.
A dopant may be contained in the raw material solution. The dopant is not particularly limited unless it interferes with the present disclosure. Examples of the dopant include an n-type dopant or a p-type dopant of tin, germanium, silicon, titanium, zirconium, vanadium, niobium, or the like. The concentration of the dopant may be from about 1×1016/cm3 to about 1×1022/cm3, for example, or concentration of the dopant may be a low concentration of about 1×1017/cm3 or less, for example. According to the present disclosure, the dopant may be contained at a high concentration of about 1×1020/cm3 or more.
The atomization process adjusts a raw material solution containing metal, atomizes the raw material solution, causes droplets to float, and generates atomization droplets. The blending ratio of the metal is not particularly limited but is preferably from 0.0001 mol/L to 20 mol/L with respect to the entire raw material solution. The atomization means is not particularly limited as long as atomization of the raw material solution is possible, and the atomization means may be well-known atomization means, but is preferably atomization means using ultrasonic vibration in the present disclosure. It is more preferred that the mist used in the present disclosure float on air and be mist that is not sprayed like a spray, for example, but has zero initial velocity, floats on air, and is able to be carried as gas. The droplet size of the mist is not particularly limited but may be a droplet of about several millimeters, but is preferably 50 μm or less and more preferably from 1 μm to 10 μm.
In the carrying process, the atomization droplets are carried to the base by the carrier gas. The type of the carrier gas is not particularly limited unless it interferes with the present disclosure, and suitable examples thereof include oxygen, ozone, inert gas (for example, nitrogen and argon), or reducing gas (hydrogen gas, forming gas, and the like). The type of the carrier gas may be one type but also may be two or more types, and diluent gas (for example, ten-fold dilution gas) obtained by changing the carrier gas concentration, for example, may further be used as second carrier gas. The supplying place of the carrier gas does not necessarily need to be one place and may be two or more places. The flow rate of the carrier gas is not particularly limited but is preferably 1 LPM or less and more preferably from 0.1 LPM to 1 LPM.
In the film formation process, a film is formed on the crystal substrate by causing the atomization droplets to react. The reaction is not particularly limited as long as a film is formed from the atomization droplets in the reaction but is preferably thermal reaction in the present disclosure. The thermal reaction only needs to be a reaction in which the atomization droplets react by heat, and the reaction conditions and the like are not particularly limited unless it interferes with the present disclosure. In the present process, the thermal reaction is normally performed at a temperature equal to or more than an evaporation temperature of the solvent of the raw material solution but is preferably a temperature that is not too high and is more preferably 650° C. or less. The thermal reaction may be performed under any atmosphere out of vacuum, non-oxygen atmosphere, reducing gas atmosphere, and oxygen atmosphere and may be performed under any condition out of atmospheric pressure, pressurization, and depressurization unless it interferes with the present disclosure. However, in the present disclosure, it is preferred that the thermal reaction be performed under atmospheric pressure because it becomes easier to calculate the evaporation temperature and it becomes possible to simplify equipment and the like, for example. The film thickness is settable by adjusting the amount of time of the film formation.
A film formation apparatus 19 suitably used in the present disclosure is described below with reference to the drawings. The film formation apparatus 19 in
As illustrated in
It is also preferred that the mist CVD apparatus 19 be used as the film formation apparatus illustrated in
With use of the suitable film formation apparatus, it becomes possible to form the semiconductor layer on the crystal growth plane of the crystal substrate in an easier manner. The semiconductor layer is normally formed by epitaxial crystal growth.
The semiconductor layer is suitable for use in a semiconductor device, in particular, a power device. Examples of the semiconductor device formed with use of the semiconductor layer include transistors such as a MIS and a HEMT, a TFT, a Schottky barrier diode using a metal-semiconductor junction, a JBS, a PN or PIN diode combined with another P layer, and a light receiving/emitting element. In the present disclosure, the semiconductor layer is obtainable by growing the crystalline oxide semiconductor and is usable in the semiconductor device as the semiconductor layer (film) by performing peeling from the crystal substrate, for example, if desired. It is also possible to use the semiconductor layer by disposing the semiconductor layer on a substrate of which thermal conductivity is higher than the crystal substrate, for example.
It is preferred that the semiconductor device be used in a horizontal element (horizontal device) in which an electrode is formed on one plane side of a semiconductor layer. Suitable examples of the semiconductor device include a Schottky barrier diode (SBD), a junction barrier Schottky diode (JBS), a metal-semiconductor field-effect transistor (MESFET), a high electron mobility transistor (HEMT), a metal-oxide-semiconductor field-effect transistor (MOSFET), a static induction transistor (SIT), a junction field-effect transistor (JFET), an insulated gate bipolar transistor (IGBT), or a light emitting diode (LED).
Suitable examples of the semiconductor device when the semiconductor layer in the embodiment of the present disclosure is applied to an n-type semiconductor layer (an n+-type semiconductor layer, an n− semiconductor layer, and the like) are described below with reference to the drawings, but the present disclosure is not limited to those examples.
As one example of the semiconductor device in the embodiment of the present disclosure, one example when the semiconductor device is a horizontal MOSFET is illustrated in
The material of the electrode may be a well-known electrode material, and examples of the electrode material include metal such as Al, Mo, Co, Zr, Sn, Nb, Fe, Cr, Ta, Ti, Au, Pt, V, Mn, Ni, Cu, Hf, W, Ir, Zn, In, Pd, Nd, or Ag or an alloy thereof, metal oxide conductive films of tin oxide, zinc oxide, rhenium oxide, indium oxide, indium tin oxide (ITO), indium zinc oxide (IZO), and the like, an organic conductive compound such as polyaniline, polythiophene, or polypyrrole, or a mixture and a laminated body thereof.
The formation of the electrode is performable by well-known means such as vacuum deposition or spattering, for example. More specifically, for example, when an electrode is formed with use of two types of the metal, in other words, first metal and second metal out of the metal, it is possible to form the electrode by laminating a layer formed by the first metal and a layer formed by the second metal and applying patterning using an approach of photolithography on the layer formed by the first metal and the layer formed by the second metal.
The materials of the Schottky electrode and the ohmic electrode may be well-known electrode materials, and examples of the electrode materials include metal such as Al, Mo, Co, Zr, Sn, Nb, Fe, Cr, Ta, Ti, Au, Pt, V, Mn, Ni, Cu, Hf, W, Ir, Zn, In, Pd, Nd, or Ag or an alloy thereof, a metal oxide conductive film of tin oxide, zinc oxide, rhenium oxide, indium oxide, indium tin oxide (ITO), indium zinc oxide (IZO), and the like, an organic conductive compound such as polyaniline, polythiophene, or polypyrrole, or a mixture and a laminated body thereof.
The formation of the Schottky electrode and the ohmic electrode is performable by well-known means such as vacuum deposition or spattering, for example. More specifically, for example, when the Schottky electrode is formed with use of two types of metal, in other words, first metal and second metal out of the metal, it is possible to form the electrode by laminating a layer formed by the first metal and a layer formed by the second metal and applying patterning using an approach of photolithography on the layer formed by the first metal and the layer formed by the second metal.
When a reverse bias is applied to the SBD in
When description is made from the lower side of
The semiconductor layer 141 has at least one trench 143, and the depth direction of the at least one trench 143 is a direction parallel to the m-axis of the semiconductor layer. In the embodiment of the present disclosure, the semiconductor layer 141 has a plurality of semiconductor layers, and a plurality of the trenches 143 are disposed. The semiconductor layer 141 has the n−-type semiconductor layer serving as the first semiconductor layer 141a, the n+-type semiconductor layer serving as the second semiconductor layer 141b disposed in contact with the second plane side of the first semiconductor layer 141a, and the n+-type semiconductor layer serving as the third semiconductor layer 141c disposed in contact with a first plane of the first semiconductor layer 141a. In the present embodiment, the trenches 143 pass through the third semiconductor layer (n+ semiconductor layer) 141c, and the plurality of trenches 143 with a depth that reaches to a place in the middle of the first semiconductor layer (n−-type semiconductor layer) 141a are formed. In each of the trenches 143, the gate electrode 145a is formed in an embedded manner via a gate insulating film 144 having a thickness of from 10 nm to 1 μm, for example.
In the ON state of the MOSFET in
Formation means for each layer of the semiconductor device in
A material having a high barrier height is normally used in the guard rings. Examples of the material used in the guard rings include an electrically conducting material of which barrier height is 1 eV or more and the material may be the same as the electrode material. In the present disclosure, it is preferred that the material used in the guard ring be the metal because the design freedom of a voltage-resistant structure is high, a large number of guard rings are providable, and it becomes possible to flexibly cause the voltage resistance to be more satisfactory. The shape of each of the guard rings is not particularly limited and examples thereof include a hollow quadrilateral shape, a circular shape, a squared U-shape, an L-shape, and a strip-like shape. The number of the guard rings is not particularly limited either but is preferably three or more and is more preferably six or more.
The oxide semiconductor film containing crystal containing gallium oxide and/or the oxide semiconductor film containing crystal having a corundum structure are obtainable by performing film formation with use of a method of epitaxial crystal growth. The method of epitaxial crystal growth is not particularly limited unless it interferes with the present disclosure and may be well-known means. Examples of the method of epitaxial crystal growth include CVD, metal organic chemical vapor deposition (MOCVD), metalorganic vapor-phase epitaxy (MOVPE), mist CVD, mist epitaxy, molecular beam epitaxy (MBE), hydride vapor phase epitaxy (HVPE), or pulsed growth. In the embodiment of the present disclosure, it is preferred that the mist CVD or the mist epitaxy be used when the oxide semiconductor film is formed by the epitaxial crystal growth.
Examples of the material of the first electrode, the second electrode, and/or the third electrode include metal such as Al, Mo, Co, Zr, Sn, Nb, Fe, Cr, Ta, Ti, Au, Pt, V, Mn, Ni, Cu, Hf, W, Ir, Zn, In, Pd, Nd, or Ag or an alloy thereof, a metal oxide conductive film of tin oxide, zinc oxide, rhenium oxide, indium oxide, indium tin oxide (ITO), indium zinc oxide (IZO), and the like, an organic conductive compound such as polyaniline, polythiophene, or polypyrrole, or a mixture thereof. The film formation method of the electrodes is not particularly limited, and the electrodes are formable on the substrate in accordance with a method selected, as appropriate, from a wet method such as printing, spraying, and coating, a physical method such as vacuum deposition, spattering, and ion plating, a chemical method such as CVD and plasma CVD, and the like by taking suitability with respect to the material into consideration.
In addition to the abovementioned features, by further using a well-known method, the semiconductor device in the embodiment of the present disclosure is suitably used as a power module, an inverter, or a converter, and is further suitably used in a semiconductor system using a power source apparatus, for example. The power source apparatus is producible from the semiconductor device or as the semiconductor device by connection to a wiring pattern and the like by a common procedure.
In the present disclosure, it is preferred that the semiconductor device be a power card. It is more preferred that the semiconductor device include a cooler and an insulation member, and the cooler be provided on each of both sides of the semiconductor layer via at least the insulation member. It is most preferred that a heat release layer be provided on each of both sides of the semiconductor layer, and the cooler be provided on the outer side of the heat release layer via at least the insulation member.
The semiconductor chip 301a is joined onto a principal plane on the inner side of the metal heat transfer plate 302b by a solder layer 104, and the metal heat transfer plate (protruding terminal portion) 302b is joined to the remaining principal plane of the semiconductor chip 301a by the solder layer 304. As a result, an anode electrode plane and a cathode electrode plane of a flywheel diode are connected to a collector electrode plane and an emitter electrode plane of the IGBT in a so-called antiparallel manner. Examples of the material of the metal heat transfer plates (protruding terminal portions) 302b and 303b include Mo or W. The metal electric heating plates (protruding terminal portions) 302 and 303b have a difference in thickness that absorbs the difference in thickness between semiconductor chips 101a, 101b. As a result, an outer surface of the metal heat transfer plate 102 becomes a planar surface.
The sealing resin portion 209 is formed by epoxy resin, for example, and is molded so as to cover side planes of the metal heat transfer plates 302b and 303b. The semiconductor chip 301a is molded with the sealing resin portion 209. However, outer principal planes, in other words, contact heat-receiving planes of the metal heat transfer plates 302b and 303b are fully exposed. The metal heat transfer plates (protruding terminal portions) 302b and 303b protrude to the right side in
The insulating plates 208 that are insulating spacers are configured by aluminum nitride film, for example, but may be other insulating films. The insulating plates 208 completely cover the metal heat transfer plates 302b and 303b in close contact therewith. However, the insulating plates 208 and the metal heat transfer plates 302b and 303b may simply be in contact with each other, a material with satisfactory heat transfer property such as silicone grease may be applied, or the insulating plates 208 and the metal heat transfer plates 302b and 303b may be joined to each other by various methods. An insulating layer may be formed by ceramic spraying and the like, or the insulating plates 208 may be joined onto the metal heat transfer plates or may be joined onto or formed on the refrigerant tubes.
The refrigerant tube 202 is produced by cutting a plate material obtained by performing pultrusion molding or extrusion molding of an aluminum alloy into necessary lengths. The cross-section of each of the refrigerant tubes 202 in the thickness direction has a large number of the flow paths 222 partitioned by a large number of the dividing walls 221 extending in the flow path direction so as to be spaced apart from each other at a predetermined interval. The spacers 203 may be soft metal plates of a solder alloy and the like, but also may be films formed by application and the like onto contact planes of the metal heat transfer plates 302b and 303b. The surface of each of the soft spacers 3 easily deforms and reduces thermal resistance by fitting with minute unevenness and a warp of the insulating plate 208 and minute unevenness and a warp of the refrigerant tube 202. Well-known grease with satisfactory thermal conductivity and the like may be applied to the surface and the like of each of the spacers 203, or the spacers 203 may be omitted.
By using a sapphire substrate (a c-plane, an off-angle of 0.25 degrees) having a surface on which an α-Ga2O3 layer was formed as a substrate, a mask layer formed by titanium oxide was formed on the substrate with use of spattering. Then, the formed mask layer was processed into a mask having a predetermined shape with use of photolithography. Specifically, a mask layer (a thickness of 50 nm) of titanium oxide (TiO2) was formed by spattering while by causing O2 gas and Ar gas to flow. A plurality of openings (dot-like openings) (diameter: 3 μm) were formed with use of photolithography. The mask layer was processed such that the plurality of openings were arranged on the substrate such that the distance from the center of each of the openings to the center of the nearest neighboring opening was 25 μm and the centers of openings were positioned in the vertices of a triangular lattice (an equilateral triangular lattice in the present example).
A hydride vapor phase epitaxy (HVPE) apparatus 50 used in the present example is described with reference to
The gallium (Ga) metal source 57 (a purity of 99.99999% or more) was disposed in the metal-containing-raw-material-gas supply pipe 53b, and the sapphire substrate with the mask layer obtained in 1. described above was installed on the substrate holder 56 in the reaction chamber 51 as the substrate. Then, the heaters 52a and 52b were actuated, and the temperature in the reaction chamber 51 was raised to 570° C. (around the Ga metal source) and 540° C. (around the substrate holder).
Hydrogen chloride (HCl) gas (a purity of 99.999% or more) was supplied to the gallium (Ga) metal 57 disposed in the metal-raw material-containing gas supply pipe 53b from the halide-containing-raw-material-gas supply source 53a. Gallium chloride (GaCl/GaCl3) was generated by a chemical reaction between the Ga metal and the hydrogen chloride (HCl) gas. The obtained gallium chloride (GaCl/GaCl3) and O2 gas (a purity of 99.99995% or more) supplied from the oxygen-containing-raw-material-gas supply source 55a were supplied onto the substrate through the reactive-gas supply pipe 54b. Then, film formation was performed on the substrate by causing the gallium chloride (GaCl/GaCl3) and the O2 gas to react on the substrate under atmospheric pressure at 540° C. under the distribution of the HCl gas. The flow rate of the HCl gas supplied from the halide-containing-raw-material-gas supply source 53a was maintained at 10 sccm, the flow rate of the HCl gas supplied from the reactive-gas supply source 54a was maintained at 10 sccm, and the flow rate of the O2 gas supplied from the oxygen-containing oxygen-containing-raw-material-gas supply source 55a was maintained at 100 sccm.
Regarding the multilayer structure obtained in 2-3. described above, atomic force microscope (AFM) observation was performed after surface polishing and washing. The result is shown in
A mask layer (a thickness of 50 nm) was formed as with Example 1 by using a sapphire substrate (a c-plane, an off-angle of 0.25 degrees) having a surface on which an α-Ga2O3 layer was formed as the substrate. In Example 2, a plurality of openings (dot-like openings) (diameter: 3 μm) were formed. The mask layer was processed such that the plurality of openings were arranged on the substrate such that the distance from the center of each of the openings to the center of the nearest neighboring opening was 10 μm and the centers of openings were positioned in the vertices of a triangular lattice (an equilateral triangular lattice in the present example). In the present example, the centers of the plurality of openings provided in the mask layer were positioned in the vertices of the triangular lattice (the equilateral triangular lattice in present example) as illustrated in
A multilayer structure was obtained by causing the crystal to grow and be associated as with 2-1. to 2-3. of Example 1 described above.
Regarding the obtained multilayer structure, atomic force microscope (AFM) observation was performed after surface polishing and washing. The result is shown in
A mask layer (a thickness of 50 nm) was formed as with Example 1 and 2 by using a sapphire substrate (a c-plane, an off-angle of 0.25 degrees) having a surface on which an α-Ga2O3 layer was formed as the substrate and using spattering on the substrate. In Example 3, a plurality of openings (dot-like openings) (diameter: 3 μm) were formed. The mask layer was processed such that the plurality of openings were arranged on the substrate such that the distance from the center of each of the openings to the center of the nearest neighboring opening was 10 μm and the centers of openings were positioned in the vertices of a triangular lattice (an equilateral triangular lattice in the present example). In the present example, the centers of the plurality of openings provided in the mask layer were positioned in the vertices of the triangular lattice, and one edge of each triangular shape of the triangular lattice was arranged so as to be parallel to the m-axis direction as shown in
A multilayer structure was obtained by causing the crystal to grow and be associated as with 2-1. to 2-3. of Example 1 described above.
Regarding the obtained multilayer structure, atomic force microscope (AFM) observation was performed after surface polishing and washing. The result is shown in
According to the embodiment of the present disclosure, it becomes possible to obtain the gallium-oxide semiconductor crystal having a region in which dislocation is reduced mainly in the a-axis direction. As above, it becomes possible to obtain the wide-range semiconductor crystal in which dislocation is reduced.
The semiconductor device in the embodiment of the present disclosure is usable in any field such as semiconductors (for example, compound semiconductor electronic devices), electronic components, electromechanical components, optical and electronic photography related apparatuses, and industrial components, but is particularly suitable for use in a power device and the like.
The embodiments of the present invention are exemplified in all respects, and the scope of the present invention includes all modifications within the meaning and scope equivalent to the scope of claims.
| Number | Date | Country | Kind |
|---|---|---|---|
| 2020-025273 | Feb 2020 | JP | national |
| 2020-025274 | Feb 2020 | JP | national |
| 2020-025275 | Feb 2020 | JP | national |
This application is a continuation-in-part application of International Patent Application No. PCT/JP2021/005763 (Filed on Feb. 16, 2021), which claims the benefit of priority from Japanese Patent Application No. 2020-025273 (filed on Feb. 18, 2020), No. 2020-025274 (filed on Feb. 18, 2020), and No. 2020-025275 (filed on Feb. 18, 2020). The entire contents of the above applications, which the present application is based on, are incorporated herein by reference.
| Number | Date | Country | |
|---|---|---|---|
| Parent | PCT/JP2021/005763 | Feb 2021 | US |
| Child | 17890477 | US |
