Patent Application
20090032821
The present application claims priority from Japanese patent application JP 2007-197630 filed on Jul. 30, 2007, the content of which is hereby incorporated by reference into this application.
1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly to a semiconductor device suitable for a metal oxide field effect transistor (MOSFET) or an insulated gate bipolar transistor (IGBT).
2. Description of the Related Art
When an inverter circuit is composed of a MOSFET or an IGBT, the inverter circuit has a mode in which a current flows in a reverse direction due to inductance of a motor or the like used as a load under the condition that switching devices are in an off state. When an inverter circuit is composed of junction field effect transistors (JFETs), it is therefore necessary that a diode for causing the current to flow back be connected in inverse parallel relationship with each JFET in the inverter circuit. This results in an increase in the cost. In addition, the downsizing of a package is limited. Therefore, a MOSFET or an IGBT is used generally as a switching device of an inverter.
On the other hand, silicon carbide (SiC) has a breakdown electric field than larger by approximately 10 times than that of silicon (Si), and is a material allowing a high voltage resistance drift layer to have a small thickness and a high concentration. Losses of MOSFETs using SiC are lower than those of MOSFETs using Si. The MOSFETs using Sic have been expected as destruction-resistant devices. Especially, a U-shaped metal oxide semiconductor field effect transistor (UMOSFET) using a sidewall of a trench as a channel has an advantage to shrink the device size. Power MOSFETs using Si have been manufactured. Each of the power MOSFETs has a structure capable of reducing an on-state voltage. When the UMOSFET uses SiC, the UMOSFET has a large breakdown electric field. Therefore, a large electric field may occur on a gate oxide film formed on a corner portion of a trench provided in the UMOSFET, and the UMOSFET may be broken. To avoid this problem, a technique for preventing an electric field from being concentrated is used.
In the abovementioned example, when the distance between the electric field relaxation P+ type region 16 and the P type body 12 is small, the depletion layer 20 spreading around the electric field relaxation P+ type region 16 and the depletion layer spreading in the N− type drift layer 11 may be integrated with each other. In order to cause a current to flow between the drain electrode and the source electrode, it is necessary that a channel layer, in which a current flows, be formed. To cause the current to flow in the channel layer, the following are performed: a voltage is applied to the gate electrode; and a portion of the P type body 12, which is located at the boundary between the P type body 12 and the oxide film formed on a sidewall of the trench, is reversed to an N type body; and electrons are accumulated in the boundary between the N− type drift layer 11 and the oxide film formed on the sidewall of the trench. Under the condition that the depletion layers are integrated with each other, the minimum gate voltage necessary for forming the channel layer, i.e., a threshold voltage is large. For example, when the gate oxide film 17 has a thickness of 75 nm, the concentration of the P type body 12 is 1×1018 cm−3, and the distance between the electric field relaxation P+ type region 16 and the P type body 12 is 0.5 μm, the threshold voltage is 18 V. To achieve the on-state of the channel, the gate voltage of 25 V is necessary. As a result, an electric field generated on the oxide film is large. This results in low reliability. In addition, since the channel is pinched off even when a low drain voltage is applied, a saturation current is reduced. To avoid this, the distance between the electric field relaxation P+ type region 16 and the P type body 12 is set to be large so that the depletion layers are not integrated with each other. In this case, however, the length of the channel is large, and resistance of the channel is increased. This results in an increase in the on-state voltage and prevention of an increase in the saturation current. It should be noted that the state in which the depletion layers are integrated with each other can be understood with reference to
It is, therefore, an object of the present invention to provide the structure of a UMOSFET ensuring reliability of a gate oxide film and achieving a large saturation current with a low threshold voltage.
The basic configuration of a semiconductor device according to the present invention is as follows. According to a first aspect of the prevent invention, the semiconductor device at least includes: a first semiconductor layer of a first conductivity type; a second semiconductor layer formed on the first semiconductor layer, having a lower impurity concentration than that of the first semiconductor layer, and constituting a drift region of the first conductivity type; a third semiconductor layer of a second conductivity type opposite to the first conductivity type, the third semiconductor being formed on the second semiconductor layer, a junction being formed between the second semiconductor layer and the third semiconductor layer; a fourth semiconductor layer of the first conductivity type, the fourth semiconductor layer being formed on the third semiconductor layer; a trench at least extending through the third semiconductor layer and forming a recessed portion connected with the second semiconductor layer; an insulating layer formed on a side surface and a bottom surface of the trench; a semiconductor region of the second conductivity type, the semiconductor region being formed in the second semiconductor layer and located around and outside a bottom portion of the trench; a channel region of the first conductivity type, the channel region being formed on the side surface of the trench, extending from the fourth semiconductor layer to the semiconductor region provided in the second semiconductor layer and having a higher impurity concentration than that of the second semiconductor layer constituting the drift region; and a gate electrode insulated by the insulating layer formed on the side surface and the bottom surface of the trench, at least a part of the gate electrode being formed in the trench.
According to a second aspect of the present invention, in the semiconductor device, it is useful that a depletion layer spreading from the third semiconductor layer of the second conductivity type to the second semiconductor layer (constituting the drift region) of the first conductivity type and a depletion layer spreading from the semiconductor region (formed in the second semiconductor layer) of the second conductivity type to the second semiconductor layer constituting the drift region are separated from each other in a thermal equilibrium state.
The semiconductor region of the second conductivity type, which is located in the second semiconductor layer and around and outside the bottom portion of the trench, is an electric field relaxation region. That is, the electric field relaxation region prevents an excessive electric field from being generated on an oxide film formed on a corner portion of the trench. The electric field relaxation region may have a known structure. The trench according to the present invention may be a groove described below in detail, any one of various types of holes and recessed portions.
It is useful that the semiconductor device according to the present invention uses a MOSFET or an IGBT. The configuration of the semiconductor device using a MOSFET or an IGBT is described below.
According to a third aspect of the present invention, in the semiconductor device according to the first or second aspect, the first semiconductor layer is a drain region or a source region. When the first semiconductor layer is the drain region, the fourth semiconductor layer is a source region. When the first semiconductor layer is the source region, the fourth semiconductor layer is a drain region.
In addition, each of the semiconductor devices according to the first to third aspects is highly suitable for practical use when each of the first to fourth semiconductor layers is made of SiC.
From the perspective of voltage resistance of the semiconductor device according to the first to third aspects, a practical approach is to set the impurity concentration of the channel region to be lower than that of the third semiconductor layer.
The semiconductor device according to the present invention is preferably used for an electrical circuit device such as a power device, more particularly for an inverter circuit.
The present invention provides the structure of a UMOSFET ensuring reliability of a gate oxide film and achieving a large saturation current with a low threshold voltage.
A principle for obtaining an effect of the present invention will be described prior to explanation of embodiments of the present invention.
A typical example of a semiconductor device disclosed in the present application is as follows. Specifically, the semiconductor device according to the present invention includes: a drain layer of a first conductivity type, which has a high SiC concentration; a drift layer of the first conductivity type, which is in contact with the drain layer and has a low SiC concentration; a body layer of a second conductivity type, which is formed on the drift layer and has a high SiC concentration; a source layer of the first conductivity type, which is formed on the body layer and has a high SiC concentration; a trench extending from the source layer to a predetermined location placed in the drift layer; an insulating film formed on a side surface and a bottom surface of the trench; an electric field relaxation region of the second conductivity type, which is formed around and outside a bottom portion of the trench; and a channel region of the first conductivity type, which is formed on the side surface of the trench, extends from the source layer to the electric field relaxation region, and has a higher SiC concentration than that of the drift layer.
In short, a UMOSFET according to the present invention has an N type channel region formed at the periphery of the surface of a gate oxide film (formed on a sidewall of the trench) and extending from the N+ type source layer to the P type electric field relaxation region formed around and outside the bottom portion of the trench. Alternatively, in the UMOSFET, a depletion layer spreading from the body layer to the drift layer and a depletion layer spreading from the electric field relaxation region to the drift layer are separated from each other by the channel region in a thermal equilibrium state.
The most important characteristic of the present invention is that the channel region 15 having a higher impurity concentration than that of the N− type drift layer 11 is formed at the periphery of the surface of the gate oxide film formed on the sidewall of the trench and extends from the N+ type source layer 13 to the P type electric field relaxation region 16. This configuration prevents the depletion layer 20 spreading from the P type body 12 and the depletion layer 21 spreading from the P type electric field relaxation region 16 from being integrated with each other under the condition that the UMOSFET is in a thermal equilibrium state. The threshold voltage can therefore be reduced. Electrons can be accumulated in the almost entire part of the channel region 15 (which becomes an accumulation region 22 as shown in
In the semiconductor device according to the present invention, the first conductivity type (described above) of the semiconductor layers may be either a P type or an N type to achieve the configuration of the semiconductor device. In this case, the second conductivity type (described above) is opposite to the first conductivity type. That is, in embodiments described below, even when the P type is replaced with the N type, and the N type is replaced with the P type, the configuration of the semiconductor device according to the present invention can be achieved.
The embodiments of the present invention will be described in detail with reference to the accompanying drawings.
As shown in
After the first mask material 40 is removed, a second mask material 42 is formed and patterned into a predetermined shape. Then, aluminum ions 43 are implanted into the prepared laminated semiconductor body (shown in
After the second mask material 42 is removed, a third mask material 45 is formed and patterned into a predetermined shape. A trench (groove) (having a depth of 2.8 μm) is formed in the prepared laminated semiconductor body by dry etching. Then, aluminum ions 46 are implanted into the laminated semiconductor body (shown in
In the series of the processes described above, the process for implanting aluminum ions to form the P type electric field relaxation region 16 around and outside the bottom portion of the trench may be performed after the process for implanting nitrogen ions from the oblique direction to form the channel region 15 on the sidewall of the trench is performed.
After the third mask material 45 is removed, a heat treatment is performed at a temperature of 1700° C. to activate the implanted aluminum ions and the implanted nitrogen ions. After the heat treatment, the gate oxide film 17 is formed due to thermal oxidation. Polycrystalline silicon 34 constituting the gate electrode 34 is filled in the trench (refer to
The polycrystalline silicon 34 is etched back, and an SiO2 film is formed on the polycrystalline silicon by a CVD method (refer to
Then, an Ni film is formed on the surface of the N+ type wafer to form the drain electrode 31 and the silicide layer 32. In addition, a contact window is patterned on the surface of the N+ type source layer 13 and on the surface of the P+ type semiconductor region 14. An Ni film is formed on the contact window, and an alloying heat treatment is performed. In this way, the silicide layer 32 is formed on the laminated semiconductor body (refer to FIG. 11).
Then, an aluminum layer is formed on the almost entire surface of the element (laminated semiconductor body) to constitute the source electrode 33. Accordingly, the UMOSFET (shown in
Since the channel region 15 extends from the N+ type source layer 13 to the P type electric field relaxation region 16 and has an impurity concentration higher than that of the N− type drift layer 11 and lower than that of the P type body 12, the threshold voltage can be set to a value lower than 10 V and the saturation current can be large. The thus constructed UMOSFET is of normally off type capable of maintaining voltage resistance to a high voltage even when the gate voltage is 0 volts. In the present embodiment, the UMOSFET is resistant to a voltage of 720 volts.
When the impurity concentration of the channel region 15 is increased, the threshold voltage can be further reduced. When the peak impurity concentration of the channel region 15 is 1×1018 cm−3, the voltage to which the UMOSFET is resistant is reduced. As described above, the P type body 12 has an impurity concentration of 1×1018 cm−3. In order to maintain the voltage to which the UMOSFET is resistant, it is preferable that the peak impurity concentration be lower than 1×1018 cm−3, more practically, 3×1017 cm−3 or less. From the perspective of the voltage resistance of the semiconductor device, it is more practical that the impurity concentration of the channel region is lower than that of the P type body (i.e., the third semiconductor layer).
Next, a description will be made of the planar configuration of the UMOSFET described above with reference to the layout of the UMOSFET when viewed from the top surface thereof.
A circuit and a module, which use the semiconductor device according to the present invention, will be described in a second embodiment of the present invention.
In
The characteristic of the present invention is that the current capacity per chip is large and the on-state voltage is low. In terms of another characteristic of the present invention, the size of the chip can be reduced compared with a conventional technique by using a current having the same amount flows. In the present embodiment, the size of the 6-in-1 module can be reduced by half compared with that of a conventional 6-in-1 module.
The basic configuration and effect of the channel region are similar to those of a conventional channel. The channel region 15 according to the present embodiment extends from the N type emitter layer 63 to the P type electric field relaxation region 16. Therefore, a threshold voltage for turning on the IGBT can be reduced, and an on-state voltage of the IGBT can be reduced.
| Number | Date | Country | Kind |
|---|---|---|---|
| 2007-197630 | Jul 2007 | JP | national |
