Patent Application
20250031424
The present application belongs to the field of semiconductor technology, and particularly relates to a semiconductor device and a fabricating method thereof, and a semiconductor wafer.
An increasing number of power electronics, sensor signal conditioning, and RF communication devices are required to operate at high temperatures. These devices require integrated circuits, such as mixed-signal circuits with analog circuits, analog-to-digital converters, embedded microcontrollers and on-chip memories. In the related art, complementary metal-oxide-semiconductor (CMOS) technology based on silicon is often used to form CMOS circuits integrated with PMOS and NMOS transistors to realize various logic functions, but such a structure is not reliable for stable and continuous operation at a high temperature (for example, above 125° C.).
According to a first aspect of embodiments of the present application, a semiconductor device is provided having a first region and a second region, including:
In some embodiments, the first drain electrode is connected to the second source electrode, and the first gate electrode is connected to the second gate electrode.
In some embodiments, the first structural layer serves as a substrate.
Or the semiconductor device comprises a substrate, the substrate being on a surface of the first structural layer away from the second structural layer.
In some embodiments, the first structural layer has a thickness of 100 μm-500 μm if the first structural layer serves as a substrate, and has a thickness of 0.1 μm-10 μm if the semiconductor device comprises other layers in contact with the first structural layer as a substrate; and/or, the second structural layer has a thickness of 2 nm to 30 nm.
In some embodiments, the first structural layer serves as a channel layer of the first region, the second structural layer serves as a barrier layer of the first region, and the semiconductor device comprises:
In some embodiments, the semiconductor device is not provided with a cap layer, wherein the first source electrode and the first drain electrode are both disposed on a surface of the second structural layer away from the first structural layer; or
In some embodiments, the semiconductor device is not provided with a cap layer, wherein the first gate electrode is disposed on a surface of the second structural layer away from the first structural layer, or
In some embodiments, if the first gate electrode penetrates through a partial depth of the second structural layer, a distance between a bottom end of the first gate and a bottom surface of the second structural layer is 2 nm-15 nm.
In some embodiments, a portion of the first structural layer not covered by the second structural layer is provided with an isolation strip for electrically isolating the first region from the second region.
In some embodiments, the isolation strip extends into the first structural layer from a surface of the first structural layer in contact with the second structural layer, an extension depth of the isolation strip is 2 nm to 20 nm, and a width of the isolation strip is 0.1 μm to 5 μm; and/or
In some embodiments, a two-dimensional electron gas is formed at an interface between the first structural layer and the second structural layer in the first region, and a N-type transistor is formed in the first region based on the two-dimensional electron gas; a two-dimensional hole gas is formed at a surface of the first structural layer in the second region, and a P-type transistor is formed in the second region based on the two-dimensional hole gas;
The semiconductor device is a CMOS-like device or an integrated circuit integrating the N-type transistor formed based on the two-dimensional electron gas in the first region and the P-type transistor formed based on the two-dimensional hole gas in the second region.
According to a second aspect of an embodiment of the present application, a semiconductor wafer is provided comprising a plurality of chips arranged in arrays, each chip integrating a plurality of semiconductor devices as described above.
According to a third aspect of the embodiments of the present application, a fabricating method of a semiconductor device is provided, comprising:
In some embodiments, after fabricating the first electrode structure and the second electrode structure, the method comprises:
In some embodiments, prior to forming the first structural layer, the method includes providing a substrate;
In some embodiments, after providing the substrate, the method comprises:
In some embodiments, after forming the second structural layer, the method comprises:
In some embodiments, electrically isolating the portion of the first structural layer located in the first region from the portion of the first structural layer located in the second region comprises:
In some embodiments, the isolation strip extends inward from a surface of the first structural layer in contact with the second structural layer, an extension depth of the isolation strip is 2 nm to 20 nm, and a width of the isolation strip is 0.1 μm to 5 μm; and/or
In some embodiments, forming the second structural layer 2 comprises:
Based on the above technical solutions, in the above semiconductor device, the first structural layer is made using monocrystalline diamond, and the second structural layer located in the first region is made using a monocrystalline AlN film or a doped monocrystalline AlN film, so that a two-dimensional electron gas is formed at the interface between the first structural layer and the second structural layer. A portion of the first structural layer located in the second region is subjected to hydrogen termination treatment to form a two-dimensional hole gas at the surface of a portion of the first structural layer. The diamond material has excellent characteristics such as excellent high temperature resistance and thermal conductivity, large bandgap and high breakdown voltage, high electron mobility and high hole mobility, enabling the semiconductor device to form an integrated circuit integrating a N-type transistor (NMOS) based on two-dimensional electron gas and a P-type transistor (PMOS) based on two-dimensional hole gas, the integrated circuit made therefrom may have the same functions and applications as silicon-based CMOS integrated circuits, implement the same various logic functions as silicon-based CMOS circuits, and can operate more continuously and stably at high temperatures, even at temperatures above 350° C., and can achieve higher output power, operating frequency and breakdown voltage, as compared to using silicon-based complementary metal oxide semiconductor (CMOS) technology.
Exemplary embodiments will be described herein in detail, examples of which are illustrated in the accompanying drawings. Where the following description refers to the drawings, the same numbers in different accompanying drawings indicate the same or similar elements, unless otherwise indicated. The embodiments described in the following exemplary embodiments are not intended to be representative of all embodiments consistent with the present application. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.
The present application provides a semiconductor device, a fabricating method thereof and a semiconductor wafer. The semiconductor device has a first region and a second region, and comprises a first structural layer 1, a second structural layer 2, a first electrode structure and a second electrode structure. The material of the first structural layer 1 comprises monocrystalline diamond, two portions of the first structural layer 1 located in the first region and the second region, respectively, are electrically isolated, and the portion of the first structural layer 1 in the second region is subjected to hydrogen-termination treatment. The second structural layer 2 is disposed on the first structural layer 1 and in the first region, and forms a heterojunction structure with the portion of the first structural layer 1 located in the first region; the material of the second structural layer 2 comprises a monocrystalline AlN film or a doped monocrystalline AlN film. The first electrode structure comprises a first source electrode, a first gate electrode and a first drain electrode, and the first electrode structure is disposed in the first region and at least partially on a side of the second structural layer 2 away from the first structural layer 1. The second electrode structure comprises a second source electrode, a second gate electrode, and a second drain electrode. The second electrode structure is disposed on the first structural layer 1 and in the second region, and is on the same side of the first structural layer 1 as the first electrode structure. In the above semiconductor device, the first structural layer 1 adopts a material comprising monocrystalline diamond, and the second structural layer 2 located in the first region adopts a material comprising a monocrystalline AlN film or a doped monocrystalline AlN film, so as to form a two-dimensional electron gas at the interface between the first structural layer 1 and the second structural layer 2. The portion of the first structural layer 1 located in the second region is subjected to hydrogen-termination treatment, forming a two-dimensional hole gas at a portion of the surface of the first structural layer 1. And the diamond material has excellent characteristics such as excellent temperature stability and thermal conductivity, large bandgap and high breakdown voltage, high electron mobility and high hole mobility, enabling the semiconductor device to form an integrated circuit integrating an N-type transistor based on two-dimensional electron gas and a P-type transistor based on two-dimensional hole gas, which can operate more continuously and stably at high temperatures, even at temperatures of up to 350° C. and above, and can achieve higher output power, operating frequency and breakdown voltage, as compared to silicon-based complementary metal oxide semiconductor (CMOS) technology.
The semiconductor device, the manufacturing method thereof, and the semiconductor wafer are described in detail below with reference to
First, the semiconductor device is described with reference to
The material of the first structural layer 1 comprises monocrystalline diamond, and a portion of the first structural layer 1 in the first region S1 is electrically isolated from a portion of the first structural layer 1 in the second region S2. The second structural layer 2 is disposed on the first structural layer 1 and located in the first region S1. The second structural layer 2 and the first structural layer 1 in the first region S1 form a heterojunction structure. Wherein the material of the second structural layer 2 includes a monocrystalline AlN film or a doped monocrystalline AlN film. The first electrode structure comprises a first source electrode 71, a first gate electrode 72, and a first drain electrode 73. The first electrode structure is disposed in the first region S1 and at least partially on a side of the second structural layer 2 away from the first structural layer 1.
Diamond has unique physical, chemical, and electrical characteristics, for example, diamond has extremely low chemical reactivity allowing it to be used in highly corrosive environments. The room temperature thermal conductivity of diamond is 10 W/cmK-20 W/cmK, which is the highest among known materials and can reach several times that of materials such as copper and silicon. Diamond is an electrical insulator at room temperature with a resistivity of up to 1016 ohm-cm at room temperature. Furthermore, diamond is also a wide bandgap semiconductor material with a bandgap of about 5.5 eV, and has both high electron mobility (4500 cm2/V·s) and high hole mobility (3800 cm2/V·s).
Diamond may be formed subjected to a high pressure high temperature (HPHT) method. For example, the diamonds formed by this method are often cubic structures, octahedral structures and combination forms of the two. Diamond may also be formed by chemical vapor deposition (CVD), such as plasma enhanced chemical vapor deposition (PECVD) and microwave plasma chemical vapor deposition (MPCVD), etc.
Aluminum nitride (AlN) is a group III-V semiconductor material, which has the largest bandgap and direct bandgap in group III-V compound semiconductors. The bandgap of AlN is about 6.2 eV. It also has excellent piezoelectric properties and other excellent characteristics such as high thermal conductivity, high resistivity, strong breakdown field, small dielectric coefficient and so on.
A material comprising monocrystalline diamond may be used as the first structural layer 1 in the present application. The first structural layer 1 may at the same time serve as a substrate layer, that is, the first structural layer 1 additionally has functions of a substrate layer. As described above, diamond has good physical, chemical and mechanical characteristics, and can be directly used as a substrate layer. In the semiconductor device 100 shown in
In the embodiment, in the first region S1, the first structural layer 1 serves as a channel layer, and the second structural layer 2 serves as a barrier layer.
Due to the excellent properties of the diamond and the AlN material, in the first region S1, the first structural layer 1 formed by the monocrystalline diamond material serves as a channel layer, the second structural layer 2 formed by the monocrystalline AlN film or the doped monocrystalline AlN film material serves as a barrier layer. A heterojunction structure is formed by these two layers and a two-dimensional electron gas (2DEG) is formed at the interface.
In this embodiment, in the first region S1, the first structural layer 1 of diamond can be used as a substrate layer and a channel layer at the same time. The thickness of the first structural layer 1 is 100 μm-500 μm. The second structural layer 2 has a thickness of 2 nm to 30 nm. This is merely an example, and the specific thicknesses of the first structural layer 1 and the second structural layer 2 may be set according to specific situations.
As shown in
As shown in
The method for fabricating the first source electrode 71 and the first drain electrode 73 may include process steps such as photoresist coating, alignment/exposure, develop, metal deposit, metal lift-off (or etch), photoresist removal, cleaning, and annealing. The source and drain electrodes are typically alloyed from a combination of several metals by high temperature annealing to reduce contact resistance. These metals include Ti, Al, Ni, Pt, Au or others, and may be one metal or a combination of several metals (e.g., 2-6 types of metals), which are typically deposited onto the aluminum nitride epitaxial layer (i.e., the second structural layer 2) layer by layer by a metal evaporation or sputtering process. For example, the source and the drain electrodes can consist of four metal layers, Ti, Al, Ti and Au. The thickness of the four metal layers is in the range of 2 nm-25 nm, 30 nm-300 nm, 20 nm-100 nm and 50 nm-500 nm respectively. For example, Ti 25 nm, Al 50 nm, Ti 100 nm and Au 250 nm can be selected respectively, and the total thickness is 450 nm in this case. Other combinations and thickness of metal layers are also possible. The annealing process is performed in a rapid thermal annealing (RTA) furnace at a temperature generally between 70° and 1000° C., usually around 850° C. The annealing process is performed in an argon or nitrogen atmosphere for 30 seconds to 90 seconds or longer in order to form an ohmic contact to reduce resistance.
The first gate electrode 72 is typically deposited onto the second structural layer 2 layer by layer by metal evaporation or sputtering. The method for fabricating the first gate electrode 72 includes process steps such as photoresist coating, alignment/exposure, develop, metal deposit, metal lift-off (or etch), photoresist removal, and cleaning, which are not described in detail herein. In the structure shown in
It is understood that, in some other embodiments, a portion of the first source electrode is on a surface of the second structural layer away from the first structural layer, another portion of the first source electrode penetrates through the second structural layer and is in contact with a surface of the first structural layer. A portion of the first drain electrode is on a surface of the second structural layer away from the first structural layer. Another portion penetrates through the second structural layer and is in contact with the surface of the first structural layer 1.
In addition, the first gate electrode may also be partially located on the surface of the second structural layer away from the first structural layer 1, and another portion of the first gate electrode penetrates through a portion of the thickness of the second structural layer 2. The first gate electrode penetrates through a partial depth of the second structural layer, and the distance between the bottom end of the first gate electrode and the bottom surface of the second structural layer is 2 nm-15 nm, so as to improve the control capability of the gate electrode on the two-dimensional electron gas in the channel.
It should also be noted that, in some other embodiments, the regions in the second structural layer for disposing the first source electrode and the first drain electrode may also be N-doped to form N-doped regions, so as to further reduce the contact resistance.
In this embodiment, the first structural layer 1 in the second region S2 is subjected to a hydrogen-termination treatment (H-Terminated), that is, the first structural layer 1 in the second region S2 is hydrogen-terminated by using hydrogen-termination technology. The second electrode structure includes a second source electrode 74, a second gate electrode 75, and a second drain electrode 76. The second electrode structure is disposed on the first structural layer 1 in the second region S2, and is located on the same side of the first structural layer 1 as the first electrode structure. The second source electrode 74 and the second drain electrode 76 may be fabricated in a manner similar to the methods for fabricating the first source electrode 71 and the first drain electrode 73 described above. The second gate electrode 75 may be fabricated by a fabricating method similar to that described above for the first gate electrode 72.
Here, hydrogen-termination technology is used to hydrogen terminate the first structural layer 1 (i.e., the diamond material) in the second region S2, so that a P-type channel can be formed on the surface of the material. The technology exploits the principles of electron exchange between materials and the surface acceptor doping with high electron affinity (such as water molecules) to produce high two-dimensional hole concentration and mobility by hydrogen plasma treatment on the surface of diamond. Transistors fabricated by this mechanism are called hydrogen-terminated diamond field effect transistors (H-Terminated Diamond FETs). There are a variety of hydrogen-termination technologies, generally using microwave plasma generated in hydrogen (H2) or deuterium (D2). In the process of hydrogen termination of diamond, the adjustable parameters are pressure, microwave power and time, for example, the pressure range is 50-300 Torr, the microwave power is 1-10 KW, and the time is 1-20 min. The fabrication steps may also be performed in steps, for example, first performed at low voltage and low power conditions, and then performed at high voltage and high power conditions. By optimizing the process parameters, the diamond surface with high two-dimensional hole concentration can be obtained.
After the first structural layer 1 in the second region S2 is subjected to the hydrogen-termination treatment, a two-dimensional hole gas (2DHG) is formed on the surface of the first structural layer 1, which has a relatively high two-dimensional hole gas concentration and mobility.
Continuing referring to
The material of the gate dielectric layer 3 may be one or more materials such as Al2O3, SiO2, MoO3, WO3, ZrO2, AlN, TiOx, HfO2, LaAlO3 and Ta2O5. The gate dielectric layer 3 may be formed by atomic layer deposition, metal organic chemical vapor deposition, or magnetron sputtering, etc.
These oxides pull electrons out of diamond to form a two-dimensional hole gas (2DHG) in the diamond channel.
Continuing referring to
Continuing referring to
In some embodiments, the isolation strip 101 extends inward from the surface of the first structural layer 1 (i.e., the surface in contact with the second structural layer 2), and the isolation strip 101 extends a depth “h” of, for example, 2 nm-20 nm. The width “w” of the isolation strip 101 is, for example, 0.1 μm-5 μm.
The isolation strip 101 may be formed by etching, oxygen plasma treatment, ion implantation, etc.
Based on the above description of the semiconductor device 100, an N-type transistor is formed in the first region S1 based on the two-dimensional electron gas, wherein the N-type transistor formed in the first region S1 is similar in concept to an NMOS transistor, and a P-type transistor is formed in the second region S2 based on the two-dimensional hole gas, wherein the P-type transistor formed in the second region S2 is similar in concept to a PMOS transistor. The semiconductor device 100 integrally forms a CMOS-like device or an integrated circuit incorporating the N-type transistor formed based on the two-dimensional electron gas of the first region and the P-type transistor formed based on the two-dimensional hole gas of the second region.
It can be understood that the cap layer 4 may cover part or all of the surface of the second structural layer 2.
The material of the cap layer 4 may be GaN. Hereinafter, take the material of the cap layer 4 being GaN as an example. Of course, it may also be other materials, such as silicon nitride, or materials such as AlGaN with a low Al composition (AlGaN with an Al composition lower than 0.2), or a combination of GaN and silicon nitride, or a combination of AlGaN and silicon nitride. The cap layer 4 may have a thickness of, for example, 2 nm-20 nm.
In this embodiment, the cap layer 4 covers a portion of the surface of the second structural layer 2 in the first region S1. Specifically, in the areas where the first source electrode 71 and the first drain electrode 73 are arranged, there is no cap layer 4 being provided. A portion of the first source electrode 71 is on a surface of the second structural layer 2 away from the first structural layer 1, and another portion of the first source electrode 71 penetrates through the second structural layer 2 and is in contact with a surface of the first structural layer 1. The first drain electrode 73 is similarly disposed. The first gate penetrates through the cap layer 4 and is in contact with the surface of the second structural layer 2.
Of course, in some other embodiments, there is a cap layer 4 provided in the areas where the first source electrode 71 and the first drain electrode 73 are arranged, a portion of the first source electrode 71 is on a surface of the cap layer away from the first structural layer 1, and another portion of the first source electrode penetrates through the cap layer into the second structural layer 2; a portion of the first drain electrode 73 is on the surface of the cap layer away from the first structural layer 1, and another portion penetrates through the cap layer into the second structural layer 2. Alternatively, in some other embodiments, a portion of the first source electrode 71 is on a surface of the cap layer away from the first structural layer 1, and another portion of the first source electrode 71 penetrates through the cap layer and the second structural layer 2, and is in contact with a surface of the first structural layer 1; a portion of the first drain electrode 73 is on a surface of the cap layer away from the first structural layer 1, and another portion of the first drain electrode 73 penetrates through the cap layer and the second structural layer 2.
Other structures of the semiconductor device 200 may be described with reference to the corresponding description above.
In this embodiment, the first gate electrode 72 penetrates through part of the depth of the second structural layer 2, so that there is a certain distance between the first gate 72 and the bottom surface of the second structural layer 2. For example, as shown in
The material of the substrate 5 may be silicon (including SOI), silicon carbide, sapphire, etc.
In this embodiment, the thickness of the first structural layer 1 is, for example, 0.1 μm-10 μm.
The thickness of the second structural layer 2 is, for example, 2 nm-30 nm. The specific thicknesses of the first structural layer 1 and the second structural layer 2 may be set according to specific situations.
The present application further provides a semiconductor wafer comprising a plurality of chips arranged in arrays, each chip being integrated with a plurality of the above semiconductor devices. For example, referring to
Referring to
In step S101, a first structural layer is formed, wherein the material of the first structural layer comprises monocrystalline diamond;
In step S103, a second structural layer is formed on the first structural layer and in the first region, forming a heterojunction structure with the first structural layer in the first region, wherein the material of the second structural layer comprises a monocrystalline AlN film or a doped monocrystalline AlN film;
In step S105, the first structural layer located in the second region is subjected to a hydrogen-termination treatment;
In step S107, a portion of the first structural layer in the first region is electrically isolated from a portion of the first structural layer in the second region;
In step S109, a first electrode structure and a second electrode structure are formed, wherein the first electrode structure comprises a first source electrode, a first gate electrode and a first drain electrode, and the first electrode structure is disposed in the first region and at least partially on a side of the second structural layer away from the first structural layer; the second electrode structure comprises a second source electrode, a second gate electrode and a second drain electrode, and the second electrode structure is disposed on the first structural layer and in the second region, and is on the same side of the first structural layer as the first electrode structure.
First, referring to
As shown in
In some embodiments, the first structural layer 1 is formed subjected to a high pressure high temperature (HPHT) method.
In other embodiments, the first structural layer 1 is formed by a chemical vapor deposition (CVD), such as PECVD or MPCVD.
As shown in
As shown in
The thickness of the second structural material layer 20 ranges, for example, from 2 nm to 30 nm.
The second structural material layer 20 may be fabricated by various methods, and a commonly used method is metal organic chemical vapor deposition (MOCVD). Trimethylaluminum (TMAI, C3H9Al) and ammonia (NH3) are generally used as the aluminum source and nitrogen source respectively, and hydrogen is used as the carrier gas. Monocrystalline aluminum nitride films with high quality may be grown by adjusting the pressure, the temperature and the gas flow of the reaction furnace. In order to reduce the stresses and dislocations caused by the lattice mismatch between the diamond material and the aluminum nitride material, a layer of amorphous film, such as silicon oxide, silicon nitride, silicon oxynitride and other materials, may be grown between the grown AlN films. The growing methods include atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), etc. The thickness of the amorphous film is 0.5-5 nm. In order to further improve the concentration and mobility of two-dimensional electron gas, AlN can be doped to increase the piezoelectric coefficient of the material and to enhance the piezoelectric polarization effect. The fabricating method is to add an metalorganic gas source containing the element Sc, Tris(cyclopentadienyl) scandium (III) (the chemical formula is C15H15Sc) in the process of growing AlN. Thus, while the AlN film is fabricated, the ScAIN film is formed by doping scandium. The doping concentration may be 5-50%, or even higher, depending on the requirements of the particular application.
The second structural material layer 20 may also be fabricated by molecular beam epitaxy (MBE) or plasma induced molecular beam epitaxy (PIMBE), using a conventional evaporation source for Al and a radio frequency plasma source to generate nitrogen radicals, thereby growing a high quality monocrystalline AlN film on the diamond surface. In order to further improve the concentration and mobility of two-dimensional electron gas, AlN can be doped to increase the piezoelectric coefficient of the material and to enhance the piezoelectric polarization effect. The fabricating method is that in the process of growing the AlN, besides the Al source, an Sc evaporation source is added to form a ScAIN material. It is also possible to use only one evaporation source, that is, the ScAl alloy fabricated according to a certain proportion is adopted to react with the nitrogen radicals generated by the radio frequency plasma source to form the ScAIN film, that is, the Sc-doped AlN film. The doping concentration may be 5-50% or even higher, which is determined by the proportion of the ScAl alloy material.
In step S1032, a portion of the second structural material layer 20 in the second region S2 is removed to form the second structural layer 2.
Specifically, as shown in
Referring to
Here, hydrogen termination technology is used to hydrogen terminate the first structural layer 1 (i.e., the diamond material) in the second region S2, so that a P-type channel can be formed on the surface of the material. The technology exploits the principles of electron exchange between materials and the doping of surface acceptors with high clectron affinity (such as water molecules) to produce high two-dimensional hole concentration and mobility by hydrogen plasma treatment on the surface of diamond. Transistors fabricated by this mechanism are called hydrogen-terminated diamond field effect transistors (H-Terminated Diamond FETs). There are a variety of hydrogen-termination technologies, generally using microwave plasmas generated in hydrogen (H2) or deuterium (D2). In the process of hydrogen termination of diamond, the adjustable parameters are pressure, microwave power and time, for example, the pressure range is 50-300 Torr, the microwave power is 1-10 KW, and the time is 1-20 min. The fabrication steps may also be performed in steps, for example, first performed at low voltage and low power conditions, and then performed at high voltage and high power conditions. By optimizing the process parameters, the diamond surface with high two-dimensional hole concentration and high hole mobility can be obtained.
With reference to
a gate dielectric layer 3 is formed on the surface of the first structural layer 1 in the second region S2.
The material of the gate dielectric layer 3 may be one or more materials such as Al2O3, SiO2, MoO3, WO3, ZrO2, AlN, TiOx, HfO2, LaAlO3 and Ta2O5. The gate dielectric layer 3 may be formed by atomic layer deposition, metal organic chemical vapor deposition, or magnetron sputtering, etc.
In step S107, a portion of the first structural layer 1 located in the first region S1 is electrically isolated from a portion of the first structural layer 1 located in the second region S2.
Referring to
In some embodiments, the isolation strip 101 extends inward from the surface of the first structural layer 1 (i.e., the surface in contact with the second structural layer 2), and the isolation strip 101 extends a depth “h” of 2 nm-20 nm. The width “w” of the isolation strip 101 is 0.1 μm-5 μm.
The isolation strip 101 may be formed by adopting the technologies of etching, oxygen plasma treatment or ion implantation.
Referring to
In this embodiment, a first electrode structure is first formed, and then a second electrode structure is formed. In other embodiments, the order of forming the first electrode structure and the second electrode structure may also be reversed, or formed simultaneously.
The specific generation of the first electrode structure and the second electrode structure can be referred to the relevant descriptions of the above structural embodiments and will not be repeated herein.
Referring to
The first drain electrode 73 is connected to the second source electrode 74, and the first gate electrode 72 is connected to the second gate electrode 75.
Metal wires may be used to connect the first drain electrode 73 to the second source electrode 74 and the first gate electrode 72 to the second gate electrode 75.
For a semiconductor device with a cap layer, such as shown in
In step S104, a cap layer 4 is formed on the surface of the second structural layer 2 away from the first structural layer 1.
The cap layer 4 may be, for example, gallium nitride or silicon nitride. The cap layer 4 may be AlGaN with a low Al composition, etc., such as AlGaN with an Al composition lower than 0.2. The thickness of the cap layer 4 ranges, for example, from 2 nm-20 nm.
The cap layer 4 may be fabricated in a variety of methods. For example, a common method for fabricating a GaN-based cap layer is metal organic chemical vapor deposition (MOCVD). Trimethylgallium (TMGa, C3H9Ga) and ammonia (NH3) are generally used as the gallium source and nitrogen source respectively, and hydrogen is used as the carrier gas. High-quality monocrystalline gallium nitride films may be grown by adjusting the pressure, temperature and gas flow of the reaction furnace.
It should be noted that, in this embodiment, the first structural layer 1 serves as a substrate.
With reference to
In step S1001, a substrate 5 is provided;
Forming the first structural layer 1 as described in step S101 includes:
The growth quality of the first structural layer 1 (e.g., diamond) may be optimized and the growth rate thereof may be improved by optimizing the fabrication process variables of the first structural layer 1, including pressure and concentration of reaction gas, substrate temperature, and sample stage, etc. The thickness of the first structural layer 1 fabricated is 0.1 μm-10 μm. Preferably, the MPCVD process may be used, and the process conditions are as follows: the power is 1 KW-10 KW, the pressure is 5 kPa-200 kPa, the gas ratio is 1-5% (N2/CH4), and the temperature is 1000° C.-1500° C.
In forming the first structural layer 1, the substrate 5 may preferably be mounted on a molybdenum substrate support to ensure a uniform temperature throughout the substrate, so that the thickness of different regions of the first structural layer 1 formed is relatively consistent.
For a semiconductor device with a substrate 5, after providing the substrate 5, the method optionally comprises:
Forming the first structural layer 1 on top of the substrate 5 comprises:
forming the first structural layer 1 on the polished and cleaned surface of the substrate 5.
Polishing methods herein include mechanical polishing, thermo-chemical polishing, electric spark polishing, laser polishing, ion beam polishing, plasma polishing, etc.
Here, cleaning may be ultrasonic cleaning with acetone or other solutions.
As the material of the substrate 5 and the material of the first structural layer 1 have different lattice constants and thermal expansion coefficients, the difference in lattice constants may cause lattice mismatch between the substrate 5 and the first structural layer 1, leading to dislocation defects. At the same time, the lattice mismatch will also cause the film layer to generate stress and cause the film layer warping and cracking, etc. The material of the substrate 5 and the material of the first structural layer 1 have different thermal expansion coefficients, which is easy to cause problems such as residual stress generated in the film during the fabricating process of the semiconductor device 30. Therefore, by disposing a buffer layer on the substrate, defects such as dislocation, warping, cracking and the like caused by different lattice constants and different thermal expansion coefficients of the substrate 5 and the first structural layer 1 can be eliminated or reduced, thereby contributing to improving the performance of the semiconductor device.
For a semiconductor device having the substrate 5, a buffer layer may also be disposed between the substrate 5 and the first structural layer 1.
Accordingly, after providing the substrate 5 and before forming the first structural layer 1, the method may further comprise:
In the present application, the embodiments describing the structures and the embodiments describing the methods may be complementary to each other in the case of no conflict.
Those skilled in the art can understand that the embodiments described above in conjunction with the accompanying drawings are merely preferred embodiments, the implementation of the present application is not limited to these embodiments, and any modifications and equivalents that can be conceivable by a person skilled in the art should be encompassed within the scope of protection of the present application. Accordingly, the scope of protection of the present application is to be determined by the appended claims.
| Number | Date | Country | Kind |
|---|---|---|---|
| 202310902084.7 | Jul 2023 | CN | national |
The present application is a continuation application of International Application No. PCT/CN2023/128339, filed on Oct. 31, 2023, which claims priority to Chinese Patent Application No. 202310902084.7, filed on Jul. 20, 2023, the disclosures of which are incorporated herein by reference in its entirety for all purposes.
| Number | Date | Country | |
|---|---|---|---|
| Parent | PCT/CN2023/128339 | Oct 2023 | WO |
| Child | 18745918 | US |
