Patent Application
20170263582
This application is based upon and claims the benefit of priority from Japanese Patent Application No. 2016-048898, filed Mar. 11, 2016, the entire contents of which are incorporated herein by reference.
Embodiments described herein relate generally to a semiconductor device and a manufacturing method of the same.
In a semiconductor device, for example, a plurality of semiconductor chips are stacked and electrically connected to each other through bumps. It is desirable to obtain a stable electrical connection in such a structure.
According to an embodiment of the disclosure, there is provided a semiconductor device in which a stable connection can be easily achieved, and a method of manufacturing the semiconductor device.
In general, according to an embodiment, a semiconductor device includes a wiring substrate, a first semiconductor element, a second semiconductor element, a bump, a bonding portion, and a resin portion. The second semiconductor element is between the wiring substrate and the first semiconductor element. The bump is between the first semiconductor element and the second semiconductor element and electrically connects the first semiconductor element and the second semiconductor element. The bonding portion is between the first semiconductor element and the second semiconductor element, bonds the first semiconductor element to the second semiconductor element, and has a first elastic modulus. The resin portion has a second elastic modulus higher than the first elastic modulus. A first portion of the resin portion is between the first semiconductor element and the second semiconductor element. The first semiconductor element and the second semiconductor element are between a second portion of the resin portion and the wiring substrate. A third portion of the resin portion is overlapped with the first semiconductor element and the second semiconductor element in a second direction intersecting with a first direction going from the wiring substrate toward the first semiconductor element.
Hereinafter, embodiments of the disclosure will be described with reference to the drawings. The drawings are drawn schematically and conceptually, and thus may not reflect specific scale views of a particular embodiment. Furthermore, dimensions and ratios of components may be different from drawing to drawing. The same elements as those already described in a previous drawing will be denoted with the same reference symbols in this disclosure and the respective drawings, and the detailed descriptions thereof will be appropriately omitted.
As illustrated in
The plurality of semiconductor elements 10 (for example, semiconductor chips) are stacked in the Z axis direction. Each of the semiconductor elements 10 may be the same as, or different from, any others of the semiconductor elements 10. In this example, the plurality of semiconductor elements 10 are separated from each other in the Z axis direction. The bump 21 and the bonding portion 25 are provided between two semiconductor elements 10. In this example, a lead frame 16 is further provided. The plurality of semiconductor elements 10 are arranged between the lead frame 16 and the wiring substrate 40.
The plurality of semiconductor elements 10 include, for example, a first semiconductor element 11, a second semiconductor element 12, and a third semiconductor element 13. The first semiconductor element 11 and the second semiconductor element 12 are, for example, memory chips. The third semiconductor element 13 is an interface which is used to convert data input from a connection member 45 to be a format which can be input to the semiconductor element 10, or to convert data output from the semiconductor element 10 to be a format which can be output from the connection member 45. A function of the semiconductor element 10 is arbitrary. For example, the size of the third semiconductor element 13 is different from those of the other semiconductor elements (for example, the first semiconductor element 11).
For example, the second semiconductor element 12 is provided between the wiring substrate 40 and the first semiconductor element 11. In this example, the third semiconductor element 13 is provided between the wiring substrate 40 and the second semiconductor element 12. The number of semiconductor elements 10 is arbitrary.
A direction from the wiring substrate 40 toward the first semiconductor element 11 (a first direction) is set to the Z axis direction in
A principal plane of the wiring substrate 40 is in parallel with an X-Y plane for example. The wiring substrate 40 has a plate shape extending along the X-Y plane for example. Each of the plurality of semiconductor elements 10 has a plate shape extending along the X-Y plane. A stacking direction of the plurality of semiconductor elements 10 corresponds to the Z axis direction.
Hereinafter, the description will be made about the first semiconductor element 11 and the second semiconductor element 12 among the plurality of semiconductor elements 10.
The bump 21 is provided between the first semiconductor element 11 and the second semiconductor element 12. The bump 21 electrically connects the first semiconductor element 11 and the second semiconductor element 12.
The bonding portion 25 is provided between the first semiconductor element 11 and the second semiconductor element 12. The bonding portion 25 bonds the first semiconductor element 11 and the second semiconductor element 12. The bonding portion 25 is in parallel with the bump 21 in the X-Y plane. The bonding portion 25 has a first elastic modulus. The first elastic modulus is relatively low.
As illustrated in
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For example, the plurality of semiconductor elements 10 and the wiring substrate 40 are electrically connected by connection members 43. In this example, the wiring substrate 40 includes a substrate 42 and a through electrode 41. The through electrode 41 passes through the substrate 42. The connection member 45 (the bump or the like) is provided at the lower surface of the wiring substrate 40. The semiconductor device 110 is mounted on other mounting components (not illustrated) through the connection member 45.
The resin portion 30 is provided around the plurality of semiconductor elements 10. The resin portion 30 is also provided in a region between the semiconductor elements 10.
As illustrated in
The resin portion 30 has a second elastic modulus. The second elastic modulus is higher than the first elastic modulus of the bonding portion 25. In other words, the first elastic modulus of the bonding portion 25 is lower than the second elastic modulus of the resin portion 30. A material having a low elastic modulus is used in the bonding portion 25. On the other hand, a material having a high elastic modulus is used in the resin portion 30. For example, an acrylic resin having a low elastic modulus is used in the bonding portion 25. On the other hand, an epoxy resin having a high elastic modulus is used in the resin portion 30.
A material having a high elastic modulus is used as the resin portion 30 sealing the periphery of the plurality of semiconductor elements 10, and thus bending of a package can be suppressed for example. For example, resistance against a stress applied from the outside can be increased. The semiconductor element 10 can be protected from being damaged from the outside. The resin portion 30 for sealing is a mold resin for example.
It has been found that a connection defect caused by the bump 21 provided between the plurality of semiconductor elements 10 occurs when such a mold resin having a relatively high elastic modulus is provided even between the plurality of semiconductor elements 10. For example, cracks are easily generated in the surfaces between the bump 21 and the semiconductor element 10. In some cases, there occurs peeling. Alternatively, cracks and peeling may be generated in an electrode layer of the semiconductor element 10 connected to the bump 21.
According to experiments performed by the inventors of this application, it has been found that a symptom of the connection defect is relieved when the bonding portion 25 is provided between the semiconductor elements 10 to bond the semiconductor elements 10. Then, it has been found that the connection defect in the bump 21 can be suppressed by setting the elastic modulus of the bonding portion 25 to be relatively low.
In the embodiment, the semiconductor elements 10 are bonded to each other by the bonding portion 25, and the first elastic modulus of the bonding portion 25 is set to be lower than the second elastic modulus of the resin portion 30. Therefore, the connection defect in the bump 21 can be suppressed. In the embodiment, it is possible to provide a semiconductor device which can achieve a stable connection. In the embodiment, it is possible to achieve a stable electrical connection while suppressing the bending of the package and keeping the resistance against a high stress applied from the outside.
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On the contrary, in the semiconductor device 110, the bonding portion 25 having a low elastic modulus is provided in a portion other than the bump 21. A portion abutting on the bonding portion 25 in the semiconductor element 10 is deformed by the stress caused by the bending. The stress is alleviated by the deformation. Therefore, the stress in the region connected to the bump 21 in the semiconductor element 10 is reduced. The bending is reduced in the region connected to the bump 21 in the semiconductor element 10. Since the stress is reduced in the region connected to the bump 21 in the semiconductor element 10, the cracks or the peeling can be suppressed in the bump 21. Therefore, a stable electrical connection is obtained.
Hereinafter, a result of an experiment performed by the inventors will be described as an example. In the experiment described below, two types of materials are used as the bonding portion 25. An elastic modulus D1 of a first material at a room temperature (23° C.) is 0.2 GPa to 10 GPa. An elastic modulus D1 of a second material at the room temperature (23° C.) is about 15 GPa. With the use of these materials, an area ratio of the bonding portion 25 is changed. For example, if the plurality of bonding portions 25 are provided, and a total area of the plurality of bonding portions 25 is S25 (the area in the X-Y plane), and one of the semiconductor elements 10 has an area in the X-Y plan of S10, an area ratio R1 (%) is (S25/S10)×100(%). Furthermore, four types of materials are used as the resin portion 30. An elastic modulus D2 of these materials at the room temperature (23° C.) is 12 GPa, 15 GPa, 30 GPa, or 35 GPa.
Three types of evaluations are performed on the samples using the bonding portion 25, the area ratio R1, and the resin portion 30. In a first evaluation, package crack in a moisture absorption and ref low test is evaluated. In a second evaluation, bump connection defect in a temperature cycle test is evaluated. In a third evaluation, unfilling of the resin portion 30 into the plurality of semiconductor elements 10 is evaluated.
An evaluation result E1 corresponds to the first evaluation, in which a “+” mark corresponds to a result that the package crack is not detected in the moisture absorption and reflow test. A “−” mark corresponds to a result that the package crack is detected in the moisture absorption and reflow test.
An evaluation result E2 corresponds to the second evaluation, in which a “+” mark corresponds to a result that the bump connection defect does not occur in the temperature cycle test. A “−” mark corresponds to a result that the bump connection defect occurs in the temperature cycle test.
An evaluation result E3 corresponds to the third evaluation, in which a “+” mark corresponds to a result that the unfilling is not detected. A “−” mark corresponds to a result that the unfilling is detected.
In these tables, a “/” mark indicates that the evaluation is not possible. For example, it is not possible to perform the second evaluation (the temperature cycle test) on a sample in which the package crack occurs in the moisture absorption and reflow test in the first evaluation. In these tables, a “+” mark corresponds to a good result.
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On the other hand, in a case where the bonding portion 25 has a low elastic modulus D1, the bump connection defect easily occurs in the temperature cycle test (the second evaluation result E2) when the area ratio R1 is 4.9% or 8.6%. When the area ratio R1 is excessively low, the effect of stress alleviation obtained by providing the bonding portion 25 is reduced. The area ratio R1 is desirably higher than 8.6%, for example equal to or more than 11%.
As illustrated in
For example, a good result is obtained in the moisture absorption and reflow test (the first evaluation result E1), the temperature cycle test (the second evaluation result E2), and the unfilling (the third evaluation result E3) when the elastic modulus D2 of the resin portion 30 at 23° C. is 15 GPa or more and 30 GPa or less. In the embodiment, for example, the elastic modulus D2 (the second elastic modulus) of the resin portion 30 at 23° C. is 15 GPa or more and 30 GPa or less.
For example, the second elastic modulus of the resin portion 30 at 23° C. is desirably 1.5 or more times or 60 or less times the first elastic modulus of the bonding portion 25 at 23° C. A good result is obtained in the first to third evaluation results E1 to E3. In a case where a difference between the second elastic modulus and the first elastic modulus is large, a measuring method of the second elastic modulus may be different from that of the first elastic modulus.
In another semiconductor device 112 according to the embodiment as illustrated in
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In this way, the configuration of the plurality of semiconductor elements 10 in the embodiment may be variously modified.
Hereinafter, description will be provided about an example of a method of manufacturing the semiconductor device according to the embodiment. In the following, the description will be about a case where the semiconductor device 110 is manufactured.
As illustrated in
As illustrated in
The workpiece 110A includes the first semiconductor element 11, the second semiconductor element 12, the bump 21, and the bonding portion 25. The second semiconductor element 12 is provided between the wiring substrate 40 and the first semiconductor element 11. The bump 21 is provided between the first semiconductor element 11 and the second semiconductor element 12, and electrically connects the first semiconductor element 11 and the second semiconductor element 12. The bonding portion 25 is provided between the first semiconductor element 11 and the second semiconductor element 12, and bonds the first semiconductor element 11 and the second semiconductor element 12. The bonding portion 25 has the first elastic modulus.
As illustrated in
Thereafter, the connection member 45 is formed as needed. Therefore, the semiconductor device 110 is formed. According to the embodiment, it is possible to provide a method of manufacturing the semiconductor device in which a stable connection is easily achieved.
According to the embodiment, it is possible to provide the semiconductor device in which a stable connection can be easily achieved, and the method of manufacturing the semiconductor device.
In this disclosure, “vertical” and “parallel” do not mean a strict vertical state and a strict parallel state. For example, a variation may occur in the manufacturing procedure, and they may mean a substantial vertical state and a substantial parallel state.
Hitherto, the embodiments of the disclosure have been described with reference to the specific examples. However, the embodiments of the disclosure are not limited to these specific examples. For example, a person skilled in the art may implement the specific configuration of each element such as the wiring substrate, the semiconductor element, the bump, the bonding portion, and the resin portion included in the semiconductor device by appropriately selecting the elements from a well-known range. Also this case is included in the scope of the disclosure as long as the same effect can be achieved.
In addition, any two or more elements of the respective specific examples combined in a technically possible range are also included in the scope of the disclosure as long as it is included in the spirit of the disclosure.
Besides, all the semiconductor devices and the manufacturing method thereof obtained appropriately modified by a person skilled in the art based on the semiconductor device and the manufacturing method thereof described above as the embodiment of the disclosure may also be included in the scope of the disclosure as long as they do not depart from the spirit of the disclosure.
Further, a person skilled in the art may perceive various modifications and changes within a category of idea of the disclosure. These modifications and changes are also considered as included in the scope of the disclosure.
While certain embodiments have been described, these embodiments have been presented by way of example only, and are not intended to limit the scope of the inventions. Indeed, the novel embodiments described herein may be embodied in a variety of other forms; furthermore, various omissions substitutions and changes in the form of the embodiments described herein may be made without departing from the spirit of the inventions. The accompanying claims and their equivalents are intended to cover such embodiments or modifications as would fall within the scope and spirit of the inventions.
| Number | Date | Country | Kind |
|---|---|---|---|
| 2016-048898 | Mar 2016 | JP | national |
