Patent Application
20240282621
This application claims priority to Chinese Patent Application No. 202111057260.9, entitled “SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREFOR”, filed on Sep. 9, 2021, the content of which is incorporated herein by reference in its entirety.
The present disclosure belongs to the technical field of semiconductor devices manufacturing, and relates to a semiconductor device and a manufacturing method therefor.
The strategy for metal interconnection in IC manufacturing industry is undergoing a drastic change, after many years of development, copper is being used as a main chip interconnect conductor among many conductors available for IC interconnects. Since copper is difficult to etch, early researchers working on copper etching are forced to consider an alternative method for producing metal wires, wherein a dual damascene method became an agreed method for copper metallization.
From a process perspective, the dual damascene process is now divided into two main types, one is Via First, Trench Last, and the other is Trench First, Via Last. Such processes require two or more coating exposures and dry etching processes to achieve, wherein a difference between two critical dimensions (CD) leads to a formation of a pattern of trench or via, and due to the need for multiple processes such as coating exposure, the process cost is high. Moreover, multiple exposures are required on the same film layer, thus the requirement for overlay (OVL) is high, and requires advanced equipment support, that is, the performance requirement of photolithography machine is high, therefore, the photoresist cost is also high. In addition, certain steps currently exist in second coating, thus defects such as brought by unclean development often exist, when exposure developing, a sufficient window is required to solve defects, and problems such as small process window are also prominent.
Accordingly, how to provide a new method for manufacturing a semiconductor device to simplify the process and reduce production costs, has become an important technical problem to be solved by those skilled in the art.
In view of the aforementioned drawbacks of the prior art, an object of the present is to provide a semiconductor device and a manufacturing method therefor to address the problems in the prior art that the formation of two connected conductive layers with different critical dimensions requires multiple photolithographic masks, coatings, exposures, and developments, resulting in a high cost and a small process window.
In order to achieve the above object and other related objects, the present disclosure provides a method for manufacturing a semiconductor device, including the following steps:
Optionally, the patterning the second dielectric layer by using the photoresist layer as the etching blocking layer, forming the first opening pattern extending downward from the upper surface of the second dielectric layer, wherein the bottom of the first opening pattern is provided with the second opening pattern exposing the part of the auxiliary dielectric layer further includes: providing a photoresist opening pattern on the photoresist layer, and forming a second opening pattern exposing the part of the auxiliary dielectric layer at the bottom of the first opening pattern by controlling an inclination of a sidewall of the photoresist opening pattern.
Optionally, the patterning the second dielectric layer by using the photoresist layer as the etching blocking layer, forming the first opening pattern extending downward from the upper surface of the second dielectric layer, wherein the bottom of the first opening pattern is provided with the second opening pattern exposing the part of the auxiliary dielectric layer further includes: preparing a photoresist opening pattern in the photoresist layer by utilizing a phase difference inherent in photolithography machine, wherein the photoresist opening pattern includes a first sidewall and a second sidewall asymmetric to the first sidewall, and an angle between the first sidewall and a bottom surface of the photoresist opening is different from an angle between the second sidewall and the bottom surface of the photoresist opening.
Optionally, the first dielectric layer includes one or more of boro-phospho-silicate glass layer, phospho-silicate glass layer, fluoro-silicate glass layer, undoped silicate glass layer, tetraethyl orthosilicate layer, thermally oxidized silicon dioxide layer, and wet oxidized silicon dioxide layer; a material of the auxiliary dielectric layer includes silicon carbide; the second dielectric layer includes one or more of boro-phospho-silicate glass layer, phospho-silicate glass layer, fluoro-silicate glass layer, undoped silicate glass layer, tetraethyl orthosilicate layer, thermally oxidized silicon dioxide layer, and wet oxidized silicon dioxide layer; and a material of the etching stop layer includes one of silicon nitride and silicon oxynitride.
Optionally, the removing the auxiliary dielectric layer based on the second opening pattern by using the photoresist layer and the remaining second dielectric layer on the bottom of the first opening pattern as the etching blocking layer, and exposing the first dielectric layer at the bottom of the second opening pattern further includes: removing the auxiliary dielectric layer by dry etching, wherein an etching rate of an employed dry etching gas to the auxiliary dielectric layer is greater than an etching rate of the dry etching gas to the second dielectric layer, and when the auxiliary dielectric layer exposed by the second opening pattern is completely dry etched, there is still a remaining second dielectric layer at the bottom of the first opening pattern.
Optionally, the dry etching gas includes at least SF6 and O2.
Optionally, the removing the first dielectric layer and the second dielectric layer based on the first opening pattern and the second opening pattern by continually using the photoresist layer as the etching blocking layer, until the auxiliary dielectric layer is exposed at the bottom of the first opening pattern further includes: removing the first dielectric layer and the second dielectric layer by dry etching, wherein an etching rate of an employed dry etching gas to the first dielectric layer and the second dielectric layer is greater than an etching rate of the dry etching gas to the auxiliary dielectric layer, and a removal thickness of the first dielectric layer based on the second opening pattern is less than a thickness of the first dielectric layer.
Optionally, the dry etching gas includes one or more of gas combination of CF4/CHF3/Ar, CF4/CHF3/Ar/O2, C4F8/O2/Ar, C4F8/O2/CO/Ar, C4F6/O2/Ar, C4F6/O2/CO/Ar, C5F8/O2/Ar and C5F8/O2/CO/Ar.
The present disclosure also provides a semiconductor device manufactured using any one of the aforementioned methods for manufacturing the conductor device, the semiconductor device includes a dielectric layer, and a first trench and a second trench located in the dielectric layer, wherein the first trench extends downward from an upper surface of the dielectric layer, and a trench depth of the first trench is less than a thickness of the dielectric layer, wherein the second trench extends downward from a bottom surface of the first trench and extends through the dielectric layer, and the first trench and the second trench are provided with a conductive layer therein.
Optionally, the second trench is located at an edge of a bottom of the first trench.
Optionally, a material of the conductive layer includes at least one of Cu, W, Al, Ag and Au, and the conductive layer serves as a conductive interconnection layer.
Optionally, a trench depth of the first trench is greater than a trench depth of the second trench.
As described above, the semiconductor device of the present disclosure and the manufacturing method therefor form an asymmetric photoresist opening morphology by utilizing the phase difference inherent in photolithography machine, and etch a stepped opening with asymmetric left and right depths in the dielectric layer combined with subsequent preset etching menu. Based on the depth difference between left and right, and through reasonable matching of a dielectric film layer, the present disclosure achieves a manufacturing of a damascene-like damascene structure by only one coating development, which not only simplifies the process flow, but also reduces the production cost. The support of expensive lithography apparatus is not required, and the apparatus cost is lower. The present disclosure has wide applicability and can be compatible with current CMOS/DMOS/BCD processes, and has a broader application prospect.
The following illustrates embodiments of the present disclosure by particular specific embodiments, and other advantages and effects of the present disclosure can be readily understood by a person skilled in the art from the contents disclosed in this specification. The present disclosure can also be embodied or applied by other different specific embodiments, and various details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present disclosure.
It should be noted that the illustrations provided in this embodiment (referring to
This embodiment provides a method for manufacturing a semiconductor device, referring to
S1: a substrate is provided, and an etching stop layer, a first dielectric layer, an auxiliary dielectric layer, and a second dielectric layer are successively formed on the substrate that are stacked from bottom to top.
S2: the second dielectric layer is patterned by using a photoresist layer as an etching blocking layer, a first opening pattern extending downward from an upper surface of the second dielectric layer is formed. A bottom of the first opening pattern is provided with a second opening pattern exposing a part of the auxiliary dielectric layer.
S3: the auxiliary dielectric layer is removed based on the second opening pattern by using the photoresist layer and the remaining second dielectric layer on the bottom of the first opening pattern as an etching blocking layer, the first dielectric layer at a bottom of the second opening pattern is exposed.
S4: the first dielectric layer and the second dielectric layer are removed based on the first opening pattern and the second opening pattern by continually using the photoresist layer as an etching blocking layer, until the auxiliary dielectric layer is exposed at the bottom of the first opening pattern.
S5: the auxiliary dielectric layer at the bottom of the first opening pattern is removed.
S6: the first dielectric layer is removed by continually using the photoresist layer as an etching blocking layer, a first trench extending through the second dielectric layer and the auxiliary dielectric layer and extending to the first dielectric layer is formed based on the first opening pattern, and a second trench extending from the bottom of the first trench through the first dielectric layer and extending to the etching stop layer is formed based on the second opening pattern.
S7: the photoresist layer and the etching stop layer at the bottom of the second trench are removed, and a conductive layer is formed in the first trench and the second trench.
Firstly, referring to
As an example, the substrate 1 includes but not limited to one of silicon substrate, germanium substrate, germanium-silicon substrate, silicon carbide substrate, group III-V compound substrate. The substrate 1 may be provided with an anterior layer structure, such as shallow trench isolation structure, polycrystalline silicon layer, conductive metal layer, interlayer dielectric layer, and other structures. A material of the auxiliary dielectric layer 4 is different from materials of the first dielectric layer 3 and the second dielectric layer 5.
As an example, a material of the etching stop layer 2 includes one of silicon nitride and silicon oxynitride. The first dielectric layer 3 includes one or more of boro-phospho-silicate glass layer, phospho-silicate glass layer, fluoro-silicate glass layer, undoped silicate glass layer, tetraethyl orthosilicate layer, thermally oxidized silicon dioxide layer, and wet oxidized silicon dioxide layer. A material of the auxiliary dielectric layer 4 includes silicon carbide. The second dielectric layer 5 includes one or more of boro-phospho-silicate glass layer, phospho-silicate glass layer, fluoro-silicate glass layer, undoped silicate glass layer, tetraethyl orthosilicate layer, thermally oxidized silicon dioxide layer, and wet oxidized silicon dioxide layer.
It should be noted that the etching stop layer 2, the first dielectric layer 3, the auxiliary dielectric layer 4, and the second dielectric layer 5 can also be selected as other suitable materials, as long as the etching stop layer 2 and the first dielectric layer 3 have a large etching selectivity ratio under specific etching conditions, the first dielectric layer 3 and the auxiliary dielectric layer 4 have a large etching selectivity ratio under specific etching conditions, and the auxiliary dielectric layer 4 and the second dielectric layer 5 have a large etching selectivity ratio under specific etching conditions, the scope of protection of the present disclosure shall not be unduly limited herein.
Moreover, referring to
Specifically, in this embodiment, the second opening pattern 802 exposing the part of the auxiliary dielectric layer 4 is subsequently formed at the bottom of the first opening pattern 801 by controlling an inclination of a sidewall of the photoresist opening pattern 7.
Specifically, as shown in
Specifically, the asymmetric photoresist opening pattern 7 is obtained utilizing a phase difference inherent in photolithography machine, such that the angle α between the first sidewall 701 and the bottom surface of the photoresist opening is not equal to the angle β between the second sidewall 702 and the bottom surface of the photoresist opening. For example, when the angle α between the first sidewall 701 and the bottom surface of the photoresist opening is 90°, the angle β between the second sidewall 702 and the bottom surface of the photoresist opening is greater than 90°. Of course, both a and B can also be obtuse angles.
Specifically, as shown in
In this embodiment, the angle α between the first sidewall 701 and the bottom surface of the photoresist opening is small, and an etching rate of the material close to the first sidewall 701 is slow, while the angle β between the second sidewall 702 and the bottom surface of the photoresist opening is large, and an etching rate of the material close to the second sidewall 702 is fast, such that a stepped opening pattern consisting of the first opening pattern 801 and the second opening pattern 802 is obtained.
In this embodiment, for the second dielectric layer 5 with silicon oxide material, the second dielectric layer 5 is patterned by dry etching, and an employed etching gas includes a gas combination of CF4/C4F8/Ar/O2. A flow adjustment range of CF4 is 10 to 30 sccm, a flow adjustment range of O2 is 10 to 20 sccm, a flow adjustment range of C4F8 is 10 to 30 sccm, a flow adjustment range of Ar is 100 to 200 sccm, a process pressure adjustment range is 50 to 70 mT, and a downstream radio frequency source power adjustment range is 700 to 900 W. An etching rate of the gas combination of CF4/C4F8/Ar/O2 to the second dielectric layer 5 is much higher than an etching rate of the gas combination to the auxiliary dielectric layer 4, resulting in little loss or no loss of the auxiliary dielectric layer 4.
Referring to
In this embodiment, for the auxiliary dielectric layer 4 with silicon carbide material, the auxiliary dielectric layer 4 is dry etched, and the employed etching gas includes a gas combination of SF6/O2. An etching rate of the gas combination to the auxiliary dielectric layer 4 is much higher than an etching rate of the gas combination to the second dielectric layer 5 and the first dielectric layer 3, resulting in little loss or no loss of the second dielectric layer 5 and the first dielectric layer 3. Therefore, when the auxiliary dielectric layer 4 exposed by the second opening pattern 802 is completely dry etched, there is still a remaining second dielectric layer 5 at the bottom of the first opening pattern 801. And in this step, the photoresist layer 6 is also partially removed in thickness, thus obtaining a photoresist layer 6′.
Referring to
In this embodiment, for the second dielectric layer 5 and the first dielectric layer 3 with silicon oxide material, the second dielectric layer 5 and the first dielectric layer 3 are dry etched, and the employed etching gas includes CF4/CHF3/Ar, CF4/CHF3/Ar/O2, C4F8/O2/Ar, C4F8/O2/CO/Ar, C4F6/O2/Ar, C4F6/O2/CO/Ar, C5F8/O2/Ar, C5F8/O2/CO/Ar or other suitable gas combinations. An etching rate of the gas combination to the first dielectric layer 3 and the second dielectric layer 5 is much higher than an etching rate of the gas combination to the auxiliary dielectric layer 4, resulting in little loss or no loss of the auxiliary dielectric layer 4.
Referring to
In this embodiment, for the auxiliary dielectric layer 4 with silicon carbide material, the auxiliary dielectric layer 4 is dry etched, and the employed etching gas includes a gas combination of SF6/O2. An etching rate of the gas combination to the auxiliary dielectric layer 4 is much higher than an etching rate of the gas combination to the first dielectric layer 3, resulting in little loss or no loss of the first dielectric layer 3. In this step, the photoresist layer 6′ is also partially removed in thickness, thus obtaining a photoresist layer 6″.
Referring to
In this embodiment, for the first dielectric layer 3 with silicon oxide material, the first dielectric layer 3 is dry etched, and the employed etching gas includes CF4/CHF3/Ar, CF4/CHF3/Ar/O2, C4F8/O2/Ar, C4F8/O2/CO/Ar, C4F6/O2/Ar, C4F6/O2/CO/Ar, C5F8/O2/Ar, C5F8/O2/CO/Ar or other suitable gas combinations. An etching rate of the gas combination to the first dielectric layer 3 is much higher than an etching rate of the gas combination to the etching stop layer 2, resulting in little loss or no loss of the etching stop layer 2.
Referring to
Specifically, as shown in
In this embodiment, for the etching stop layer 2 with silicon nitride material, the etching stop layer 2 is dry etched, and the employed etching gas includes CHF3/Ar/O2, CH2F2/Ar/O2, CH3F/Ar/O2 or other suitable gas combinations. An etching rate of the gas combination to the etching stop layer 2 is much higher than an etching rate of the gas combination to the first dielectric layer 3, therefore when the etching stop layer 2 at the bottom of the second trench 902 is completely removed, the bottom surface of the first trench 901 still remains in the first dielectric layer 3, and meanwhile the photoresist layer 6″ is also partially removed in thickness, thus obtaining a photoresist layer 6″.
Specifically, the etching stop layer 2 at the bottom of the second trench 902 is firstly removed, the photoresist layer 6″ is then removed, and a structure as shown in
Specifically, as shown in
Accordingly, a semiconductor device is obtained. The method for manufacturing the semiconductor device of this embodiment forms an asymmetric photoresist opening morphology by utilizing the phase difference inherent in photolithography machine, then etches a stepped opening with asymmetric left and right depths in the dielectric layer combined with subsequent preset etching steps, and forms a conductive layer in the stepped opening, thereby a dual damascene-like damascene structure is obtained. The method for manufacturing the semiconductor device of this embodiment achieves the manufacturing of the dual damascene-like damascene structure by only one coating development, which not only simplifies the process flow, but also reduces the production cost. The support of expensive lithography apparatus is not required, and the apparatus cost is lower. In addition, the method for manufacturing the semiconductor device of this embodiment has wide applicability and can be compatible with current CMOS/DMOS/BCD processes, and has a broader application prospect.
This embodiment provides a semiconductor device, referring to
Specifically, the second trench 902 is located at an edge of the first trench 901, i.e., one sidewall of the second trench 902 is connected to a sidewall of the first trench 901, and the other sidewall of the second trench 902 is spaced apart from the sidewall of the first trench 901.
As an example, a trench depth of the first trench 901 is greater than a trench depth of the second trench 902. The trench depth of the first trench 901 is a distance from a trench opening of the first trench 901 to a trench bottom of the first trench 901, and the trench depth of the second trench 902 is a distance from the trench bottom of the first trench 901 to a trench bottom of the second trench 902.
As an example, the conductive layer 10 can serve as a conductive interconnection layer of a semiconductor device. A material of the conductive layer 10 includes at least one of Cu, W, Al, Ag and Au. A critical dimension of a part of the conductive layer 10 located in the first trench 901 is larger than a critical dimension of a part the conductive layer 10 located in the second trench 902. The substrate 1 is exposed by the bottom of the second trench 902. The part of the conductive layer 10 located in the first trench 901 may serve as a conductive wire layer of the conductive interconnection layer, and the part of the conductive layer 10 located in the second trench 902 may serve as a via layer of the conductive interconnection layer.
In summary, the semiconductor device of the present disclosure and the manufacturing method therefor form an asymmetric photoresist opening morphology by utilizing the phase difference inherent in photolithography machine, then etch a stepped opening with asymmetric left and right depths in the dielectric layer combined with subsequent preset etching menu. Based on the depth difference between left and right, and through reasonable matching of the dielectric film layer, the present disclosure achieves a manufacturing of the dual damascene-like damascene structure by only one coating development, which not only simplifies the process flow, but also reduces the production cost. The support of expensive lithography apparatus is not required, and the apparatus cost is lower. The present disclosure has wide applicability and can be compatible with current CMOS/DMOS/BCD processes, and has a broader application prospect. Accordingly, the present disclosure effectively overcomes the drawbacks of the prior art and has high industrial utilization value.
The above embodiments are only exemplary illustrations of the principles and effects of the present disclosure, and are not intended to limit the present disclosure. Any person skilled in the art can modify or change the above embodiments without departing from the spirit and scope of the present disclosure. Therefore, all equivalent modifications or variations made by a person of ordinary skill in the art without departing from the spirit and technical ideas disclosed in the present disclosure shall still be covered by the claims of the present disclosure.
| Number | Date | Country | Kind |
|---|---|---|---|
| 202111057260.9 | Sep 2021 | CN | national |
| Filing Document | Filing Date | Country | Kind |
|---|---|---|---|
| PCT/CN2022/099406 | 6/17/2022 | WO |
