Claims
- 1. A method of manufacturing a semiconductor device having a first interconnection layer and a second interconnection layer provided over said first interconnection layer and connected through a connecting hole, comprising:forming a metal film to be said first interconnection layer on a semiconductor substrate; forming a conductive antireflection film on said first metal film; forming an oxide film on said antireflection film; forming a resist layer on said oxide film; selectively irradiating said resist layer which light using a halftone phase shift mask followed by development, thereby forming resist patterns for forming said connecting hole and an overlay mark; etching said oxide film using said resist patterns for said connecting hole and said overlay mark as masks, thereby forming said connecting hole in said oxide film as well as a pattern of an oxide film for an overlay mark; and forming a second interconnection layer to be electrically connected to said first interconnection layer through said connecting hole using said overlay mark as a reference for alignment by means of lithography technique.
- 2. The method of manufacturing a semiconductor device according to claim 1, wherein said metal layer is formed of a material mainly including aluminum, aluminum silicon, aluminum copper, copper or tungsten.
- 3. The method of manufacturing a semiconductor device according to claim 1, wherein said antireflection film includes titanium, titanium nitride, amorphous silicon or silicon nitride.
- 4. The method of manufacturing a semiconductor device according to claim 1, wherein the size of said connecting hole is not larger than 0.4 μm□.
Priority Claims (1)
Number |
Date |
Country |
Kind |
9-146394 |
Jun 1997 |
JP |
|
Parent Case Info
This application is a divisional of application Ser. No. 08/988,210 filed Dec. 10, 1997 now U.S. Pat. No. 6,005,295.
US Referenced Citations (9)