Patent Application
20050285206
The present application claims priority from Japanese Patent Application No. JP 2004-190589 filed on Jun. 29, 2004, the content of which is hereby incorporated by reference into this application.
The present invention relates to a semiconductor device and a manufacturing method thereof. More particularly, the present invention relates to a technology effectively applied to a semiconductor device in which a gate electrode of a MISFET is comprised of metal silicide and a manufacturing method thereof.
After forming a gate insulating film on a semiconductor substrate and forming a gate electrode on the gate insulating film, source and drain regions are formed by the ion implantation or the like. Through the process described above, a MISFET (Metal Insulator Semiconductor Field Effect Transistor, MIS field effect transistor, MIS transistor) is formed.
Also, in the CMISFET (Complementary Metal Insulator Semiconductor Field Effect Transistor), in order to realize the low threshold voltage in both of the n channel MISFET and the p channel MISFET, the so-called dual-gate structure in which materials having different work functions (Fermi level, in the case of polysilicon) are used to form the gate electrodes has been employed. More specifically, an n type impurity and a p type impurity are introduced into the respective polysilicon films of the n channel MISFET and the p channel MISFET so that the work function (Fermi level) of the gate electrode material of the n channel MISFET becomes close to the conduction band of silicon and the work function (Fermi level) of the gate electrode material of the p channel MISFET becomes close to the valence band of silicon. By doing so, the threshold voltage is reduced.
However, the thickness of a gate insulating film has been reduced more and more due to the scaling down of the CMISFET device in recent years, and the influence of the depletion in the gate electrode when a polysilicon film is used for the gate electrode has become a significant problem. For the solution of the problem, there is the technology of using a metal gate electrode as the gate electrode for preventing the depletion in the gate electrode.
U.S. Pat. No. 6,599,831 B1 describes the technology in which a polysilicon film doped with a dopant is reacted with a nickel layer formed thereon to form a gate electrode comprised of nickel silicide.
As a result of the examination by the inventors of the present invention, the following problems are found out.
In the case where a polysilicon film is used as a gate electrode of a MISFET, influence of the depletion in the gate electrode comprised of polysilicon occurs in many cases. However, when a metal material such as nickel silicide is used to form the gate electrode, the depletion in the gate electrode can be suppressed and the parasitic capacitance can be removed. Consequently, the scaling down of the MISFET device (thickness reduction of gate insulating film) can be achieved.
However, even in the case where a metal film such as nickel silicide is used as the gate electrode material, the reduction of the threshold voltage in both of the n channel MISFET and the p channel MISFET of the CMISFET is desired for the improvement of the performance of the semiconductor device. For its achievement, it is necessary to control the work function of the gate electrodes of the n channel MISFET and the p channel MISFET.
In the technology in which a polysilicon film doped with a dopant is reacted with a nickel layer formed thereon to form a gate electrode comprised of nickel silicide, the threshold voltage can be controlled by the dopant. However, in the thermal treatment, for example, the annealing for activating an impurity, boron (B) doped into a polysilicon film for forming a gate electrode of the p channel MISFET penetrates through the gate insulating film and diffuses into a channel region below the gate insulating film, and as a result, the characteristics and the reliability of the formed CMISFET may be influenced.
An object of the present invention is to provide a technology capable of improving the performance of a semiconductor device.
Another object of the present invention is to provide a technology capable of improving the reliability of a semiconductor device.
The above and other objects and novel characteristics of the present invention will be apparent from the description and the accompanying drawings of this specification.
The typical ones of the inventions disclosed in this application will be briefly described as follows.
The present invention is a semiconductor device, which comprises: an n channel first MISFET; and a p channel second MISFET, wherein a first gate electrode of the first MISFET is comprised of metal silicide containing Ni, first metal with a work function lower than that of Ni, and Si, and a second gate electrode of the second MISFET is comprised of metal silicide containing Ni, second metal with a work function higher than that of Ni, and Si.
A method of manufacturing a semiconductor device having an n channel first MISFET and a p channel second MISFET, which comprises steps of: (a) preparing a semiconductor substrate; (b) forming a first insulating film for a gate insulating film on the semiconductor substrate; (c) forming a silicon film on the first insulating film; (d) forming a first dummy electrode of the first MISFET and a second dummy electrode of the second MISFET by patterning the silicon film; (e) forming a first metal film containing Ni and first metal with a work function lower than that of Ni on the first dummy electrode; (f) reacting the silicon film constituting the first dummy electrode with the first metal film to form a first gate electrode of the first MISFET, which is comprised of metal silicide containing Ni, the first metal, and Si; (g) forming a second metal film containing Ni and second metal with a work function higher than that of Ni on the second dummy electrode; and (h) reacting the silicon film constituting the second dummy electrode with the second metal film to form a second gate electrode of the second MISFET, which is comprised of metal silicide containing Ni, the second metal, and Si.
A method of manufacturing a semiconductor device having an n channel first MISFET and a p channel second MISFET, which comprises steps of: (a) preparing a semiconductor substrate; (b) forming a first insulating film for a gate insulating film on the semiconductor substrate; (c) forming a silicon film on the first insulating film; (d) forming a first dummy electrode of the first MISFET and a second dummy electrode of the second MISFET by patterning the silicon film; (e) forming a metal film mainly comprised of nickel on the first dummy electrode and the second dummy electrode; (f) introducing first metal with a work function lower than that of Ni into the metal film on the first dummy electrode and introducing second metal with a work function higher than that of Ni into the metal film on the second dummy electrode by ion implantation, and (g) reacting the silicon film constituting the first dummy electrode with the metal film in which the first metal is introduced to form a first gate electrode of the first MISFET comprised of metal silicide containing Ni, the first metal, and Si, and reacting the silicon film constituting the second dummy electrode with the metal film in which the second metal is introduced to form a second gate electrode of the second MISFET comprised of metal silicide containing Ni, the second metal, and Si.
A method of manufacturing a semiconductor device having an n channel first MISFET and a p channel second MISFET, which comprises steps of: (a) preparing a semiconductor substrate; (b) forming a first insulating film for a gate insulating film on the semiconductor substrate; (c) forming a silicon film on the first insulating film; (d) forming a first dummy electrode of the first MISFET and a second dummy electrode of the second MISFET by patterning the silicon film; (e) forming a metal film mainly comprised of nickel on the first dummy electrode and the second dummy electrode; (f) reacting the silicon film constituting the first dummy electrode with the metal film to form a first gate electrode of the first MISFET comprised of nickel silicide, and reacting the silicon film constituting the second dummy electrode with the metal film to form a second gate electrode of the second MISFET comprised of nickel silicide; and (g) introducing first metal with a work function lower than that of Ni into the first gate electrode and introducing second metal with a work function higher than that of Ni into the second gate electrode by ion implantation.
The effect obtained by the representative one of the inventions disclosed in this application will be briefly described as follows.
That is, it is possible to improve the performance of a semiconductor device.
Also, it is possible to improve the reliability of a semiconductor device.
Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiment, and the repetitive description thereof will be omitted. Also, the description of the same and similar part is not repeated in principle unless particularly required in the following embodiments.
Also, in the drawings used in the embodiments, the hatching is omitted in some cases even in a cross-sectional view and the hatching is used in some cases even in a plan view so as to make the drawings easy to see.
A semiconductor device and a manufacturing method thereof according to this embodiment will be described with reference to the drawings. FIGS. 1 to 12 are cross-sectional views showing the principal part in the process of a manufacturing of a semiconductor device according to an embodiment of the present invention, for example, a CMISFET (Complementary Metal Insulator Semiconductor Field Effect Transistor).
As shown in
Next, a p type well 3 is formed in a region of the semiconductor substrate 1 in which the n channel MISFET is to be formed (n channel MISFET forming region 1A), and an n type well 4 is formed in a region of the semiconductor substrate 1 in which the p channel MISFET is to be formed (p channel MISFET forming region 1B). The p type well 3 is formed by the ion implantation of a p type impurity such as boron (B), and the n type well 4 is formed by the ion implantation of an n type impurity such as phosphorus (P) or arsenic (As).
Next, as shown in
Next, a silicon film 6 is formed on the gate insulating film 5. The silicon film 6 is, for example, a polycrystalline silicon film and can be formed by the CVD (Chemical Vapor Deposition) method. When the CVD method is used as the method of forming the silicon film 6, the silicon film 6 can be formed without damaging the gate insulating film 5 and the like. The thickness of the silicon film 6 can be, for example, about 20 to 30 nm. Also, an amorphous silicon film can be used as the silicon film 6. Also, the silicon film 6 is preferably a nondope (undope) silicon film in which no impurity is introduced (nondope polysilicon film or nondope amorphous silicon film). Note that, in this embodiment, the nondope means that any impurity is not introduced (added) intentionally, and the nondope includes the case where a minute amount of impurity is contained unintentionally.
Next, an insulating film (hard mask layer) 7 comprised of silicon oxide is formed on the silicon film 6. The thickness of the insulating film 7 can be, for example, about 50 to 100 nm.
Next, as shown in
Next, as shown in
Next, sidewalls (sidewall spacer, sidewall insulating film) 14 comprised of an insulator such as silicon nitride are formed on the sidewalls of the gate electrodes 11a and 11b. The sidewalls 14 are formed by depositing a silicon nitride film on the semiconductor substrate 1 and then performing the anisotropic etching of the silicon nitride film.
After forming the sidewalls 14, the ion implantation of an n type impurity such as phosphorus (P) or arsenic (As) into the regions on both sides of the gate electrode 11a and the sidewalls 14 of, for example, the p type well 3 is performed to form (a pair of) n+ type semiconductor regions 15 (source, drain) aligned with the sidewalls 14 of the gate electrode 11a of the p type well 3, and the ion implantation of a p type impurity such as boron (B) into the regions on both sides of the gate electrode 11b and the sidewalls 14 of, for example, the n type well 4 is performed to form (a pair of) p+ type semiconductor regions 16 (source, drain) aligned with the sidewalls 14 of the gate electrode 11b of the n type well 4. Since the insulating film 7 exists on the gate electrodes 11a and 11b and the insulating film 7 functions as a mask in the ion implantation process described above, the impurity ions are not introduced into the gate electrodes 11a and 11b.
After the ion implantation, the annealing process for activating the introduced impurity (activation annealing, thermal treatment) is performed. By the annealing process at, for example, about 950° C., the impurity introduced into the n− type semiconductor region 12, the p− type semiconductor region 13, the n+ type semiconductor region 15, and the p+ type semiconductor region 16 can be activated. In the case where the silicon film 6 is an amorphous silicon film when it is formed, the silicon film 6 composed of an amorphous silicon film become may be a polycrystalline silicon film by this annealing process.
Also, in the case where the silicon film 6 constituting the gate electrodes 11a and 11b is the silicon film doped with an impurity, more particularly, in the case where the silicon film 6 constituting the gate electrode 11b is the silicon film doped with boron (B) (for example, B doped polysilicon film), there is the possibility that the boron (B) penetrates through the gate insulating film 5 and diffuses into the channel region below the gate insulating film 5 in this annealing process. However, since the nondope silicon film not doped with any impurity is used as the silicon film 6 constituting the gate electrodes 11a and 11b in this embodiment as described above, it is possible to prevent an impurity such as boron (B) from penetrating through the gate insulating film 5 and diffusing into the channel region below the gate insulating film 5 in this annealing process.
By the annealing process (activation annealing) described above, the impurities introduced into the n+ type semiconductor region 12, the p− type semiconductor region 13, the n+ type semiconductor region 15, and the p+ type semiconductor region 16 are activated. As a result, n type semiconductor regions (impurity diffusion layer) functioning as the source or drain of the n channel MISFET are composed of the n+ type semiconductor region 15 and the n− type semiconductor region 12, and p type semiconductor regions (impurity diffusion layer) functioning as the source or drain of the p channel MISFET are composed of the p+ type semiconductor region 16 and the p− type semiconductor region 13. The impurity concentration of the n+ type semiconductor region 15 is higher than that of the n− type semiconductor region 12, and the impurity concentration of the p+ type semiconductor region 16 is higher than that of the p− type semiconductor region 13.
Next, as shown in
Next, an insulating film 22 is formed on the semiconductor substrate 1. More specifically, the insulating film 22 is formed on the semiconductor substrate 1 so as to cover the gate electrodes 11a and 11b. The insulating film 22 is composed of, for example, a silicon oxide film (for example, TEOS (Tetraethoxysilane oxide film)). When the process for forming the insulating film 22 is performed at a relatively high temperature, a cobalt silicide film is preferably used as the metal silicide film 21. However, when the process for forming the insulating film 22 is performed at a relatively low temperature, a nickel silicide film is also available as the metal silicide film 21.
Next, the upper surface of the insulating film 22 is planarized by the CMP (Chemical Mechanical Polishing) method to expose the surface of the insulating film 7. After the CMP method, the structure shown in
Next, as shown in
Next, as shown in
The metal film 25a is composed of an Ni (nickel) film in which metal with a work function lower than that of Ni (nickel) (for example, Ti (titanium), Hf (hafnium), Zr (zirconium), Ta (tantalum)) is solid-solved. More specifically, the metal film 25a is a metal film which contains metal with a work function lower than that of Ni (nickel) (for example, Ti (titanium), Hf (hafnium), Zr (zirconium), Ta (tantalum)) and Ni (nickel). For example, it is a film comprised of metal alloy of metal with a work function lower than that of Ni and Ni.
Next, as shown in
As described above, since the metal film 25a is composed of an Ni film in which the metal (metal element) with a work function lower than that of Ni is solid-solved, the metal silicide film 26a formed by the reaction between the metal film 25a and the silicon film 6 constituting the gate electrode 11a is composed of a metal silicide film containing (as constituent elements) Ni (nickel), metal with a work function lower than that of Ni (for example, Ti (titanium), Hf (hafnium), Zr (zirconium), or Ta (tantalum)), and Si (silicon). For example, it is comprised of alloy of metal with a work function lower than that of Ni, Ni, and Si. More specifically, the metal silicide film 26a is comprised of nickel silicide in which metal with a work function lower than that of Ni (for example, Ti (titanium), Hf (hafnium), Zr (zirconium), Ta (tantalum)) is solid-solved. It is considered that the metal (metal element) with a work function lower than that of Ni is solid-solved in the nickel site of the nickel silicide. Therefore, the metal silicide film 26a is composed of, for example, an Ni1-xMxSiy film (M indicates metal with a work function lower than that of Ni). This metal silicide film 26a is to be the gate electrode 31a of the n channel MISFET 30a. Since the gate electrode 31a of the n channel MISFET 30a is composed of the metal silicide film 26a (showing metallic conduction), the gate electrode 31a is a metal gate electrode.
Next, as shown in
Next, as shown in
The metal film 25b is composed of an Ni (nickel) film in which metal with a work function higher than that of Ni (nickel) (for example, Pt (platinum), Ir (iridium), or Ru (ruthenium)) is solid-solved. More specifically, the metal film 25b is composed of a metal film containing (as constituents) metal with a work function higher than that of Ni (nickel) (for example, Pt (platinum), Ir (iridium), or Ru (ruthenium)) and Ni (nickel) and is a metal alloy film of the metal with a work function higher than that of Ni and Ni.
After forming the metal film 25b, the metal film 25b and the gate electrode 11b (silicon film 6) are reacted by the thermal treatment to form a metal silicide film (conductive film) 26b as shown in
As described above, since the metal film 25b is composed of an Ni film in which the metal (metal element) with a work function higher than that of Ni is solid-solved, the metal silicide film 26b formed by the reaction between the metal film 25b and the silicon film 6 constituting the gate electrode 11b is composed of a metal silicide film containing (as constituents) Ni (nickel), metal with a work function higher than that of Ni (for example, Pt (platinum), Ir (iridium), or Ru (ruthenium)), and Si (silicon). For example, it is comprised of metal alloy of metal with a work function higher than that of Ni, Ni, and Si. More specifically, the metal silicide film 26b is comprised of nickel silicide in which metal with a work function higher than that of Ni (for example, Pt (platinum), Ir (iridium), or Ru (ruthenium)) is solid-solved. It is considered that the metal (metal element) with a work function higher than that of Ni is solid-solved in the nickel site of the nickel silicide. Therefore, the metal silicide film 26b is composed of, for example, an Ni1-xMxSiy film (M indicates metal with a work function higher than that of Ni). This metal silicide film 26b is to be the gate electrode 31b of the p channel MISFET 30b. Since the gate electrode 31b of the p channel MISFET 30b is composed of the metal silicide film 26b (showing metallic conduction), the gate electrode 31b is a metal gate electrode.
Note that, in this embodiment, the gate electrode 11a is first reacted with the metal film 25a to form the gate electrode 31a and then the gate electrode 11b is reacted with the metal film 25b to form the gate electrode 31b. However, as another embodiment, the gate electrodes 31a and 31b can be formed in the opposite order. That is, the gate electrode 11b is first reacted with the metal film 25b to form the gate electrode 31b and then the gate electrode 11a is reacted with the metal film 25a to form the gate electrode 31a.
Also, in still another embodiment, after forming the metal film 25a on the semiconductor substrate 1 including on the upper surface of the gate electrode 11a, the metal film 25a on the p channel MISFET forming region 1B is removed (the metal film 25a on the n channel MISFET forming region 1A is not removed), and then, the metal film 25b is formed on the semiconductor substrate 1 including on the upper surface of the gate electrode 11b. Thereafter, through the same thermal treatment process, the gate electrode 11a is reacted with the metal film 25a to form the gate electrode 31a and the gate electrode 11b is reacted with the metal film 25b to form the gate electrode 31b.
Next, as shown in
Next, the insulating films 22, 33, and 41 are dry-etched with using a photoresist pattern (not shown) formed on the insulating film 41 by the photolithography method as an etching mask. By doing so, contact holes (opening) 42 are formed on the n+ type semiconductor regions 15 (source, drain), the p+ type semiconductor regions 16 (source, drain), and the gate electrodes 31a and 31b. A part of the main surface of the semiconductor substrate 1, for example, a part of (the metal silicide film 21 on the surface of) the n+ type semiconductor region 15, a part of (the metal silicide film 21 on the surface of) the p+ type semiconductor region 16, or a part of the gate electrodes 31a and 31b is exposed at the bottom portions of the contact holes 42. Note that, in the cross-sectional view in
Next, a plug 43 comprised of tungsten (W) is formed in the contact hole 42. The plug 43 is formed in the following manner. For example, after forming a barrier film (for example, titanium nitride film) 43a on the insulating film 41 and in the contact holes 42, a tungsten film is formed on the barrier film 43a by the CVD method so as to fill the contact holes 42, and the unnecessary tungsten film and barrier film 43a on the insulating film 41 are removed by the CMP method or the etch-back method.
Next, a wiring (first wiring layer) 44 is formed on the insulating film 41 in which the plugs 43 are embedded. The wiring 44 is formed in the following manner. For example, after sequentially forming a titanium film 44a, titanium nitride film 44b, an aluminum film 44c, a titanium film 44d, and a titanium nitride film 44e by the sputtering method, the films are patterned by the photolithography method and the dry etching. The aluminum film 44c is a conductive film mainly comprised of aluminum such as single aluminum (Al) or aluminum alloy. The wiring 44 is electrically connected to the n+ type semiconductor regions 15 to be the source and the drain of the n channel MISFET 30a, the p+ type semiconductor regions 16 to be the source and the drain of the p channel MISFET 30b, the gate electrode 31a of the n channel MISFET 30a, or the gate electrode 31b of the p channel MISFET 30b via the plugs 43. The wiring 44 is not limited to the above-described aluminum wiring but can be changed to various types of other wirings. For example, a tungsten wiring and a copper wiring (for example, buried copper wiring formed by the damascene method) are also available. Thereafter, an interlayer insulating film and an upper wiring layer are further formed. However, the description thereof is omitted here. The embedded copper wirings formed by the damascene method can be used as the second and subsequent layer wirings.
The semiconductor device according to this embodiment manufactured through the process described above is provided with a CMISFET having the n channel MISFET 30a and the p channel MISFET 30b formed on the main surface of the semiconductor substrate 1, and the gate electrodes 31a and 31b of the MISFETs 30a and 30b are the metal gate electrodes composed of the metal silicide films 26a and 26b.
As described above, the gate electrode 31a (that is, metal silicide film 26a) of the n channel MISFET 30a is formed by the reaction between the metal film 25a which is an Ni film in which metal (metal element) with a work function lower than that of Ni is solid-solved (contained) and the silicon film 6 constituting the gate electrode 11a, and is comprised of metal silicide containing (as constituent elements) Ni (nickel), metal with a work function lower than that of Ni (for example, Ti (titanium), Hf (hafnium), Zr (zirconium), or Ta (tantalum)), and Si (silicon). For example, it is comprised of metal alloy of metal with a work function lower than that of Ni, Ni, and Si. More specifically, the gate electrode 31a of the n channel MISFET 30a is comprised of nickel silicide in which metal with a work function lower than that of Ni (for example, Ti (titanium), Hf (hafnium), Zr (zirconium), Ta (tantalum)) is solid-solved. Since it is considered that the metal (metal element) with a work function lower than that of Ni is solid-solved in the nickel site of the nickel silicide, the gate electrode 31a of the n channel MISFET 30a is composed of, for example, an Ni1-xMxSiy film (M indicates metal with a work function lower than that of Ni).
On the other hand, the gate electrode 31b (that is, metal silicide film 26b) of the p channel MISFET 30b is formed by the reaction between the metal film 25b which is an Ni film in which metal (metal element) with a work function higher than that of Ni is solid-solved (contained) and the silicon film 6 constituting the gate electrode 11b, and is composed of a metal silicide film containing (as constituent elements) Ni (nickel), metal with a work function higher than that of Ni (for example, Pt (platinum), Ir (iridium), Ru (ruthenium)), and Si (silicon). For example, it is comprised of metal alloy of metal with a work function higher than that of Ni, Ni, and Si. More specifically, the gate electrode 31b of the p channel MISFET 30b is comprised of nickel silicide in which metal with a work function higher than that of Ni (for example, Pt (platinum), Ir (iridium), Ru (ruthenium)) is solid-solved. Since it is considered that the metal (metal element) with a work function higher than that of Ni is solid-solved in the nickel site of the nickel silicide, the gate electrode 31b of the p channel MISFET 30b is composed of, for example, an Ni1-xMxSiy film (M indicates metal with a work function higher than that of Ni).
As described above, since metal (metal element) with a work function lower than that of Ni is contained (solid-solved) in the gate electrode 31a (metal silicide film 26a) of the n channel MISFET 30a, the work function of the gate electrode 31a (metal silicide film 26a) of the n channel MISFET 30a is lower than that of nickel silicide (NiSiy). On the other hand, since metal (metal element) with a work function higher than that of Ni is contained (solid-solved) in the gate electrode 31b (metal silicide film 26b) of the p channel MISFET 30b, the work function of the gate electrode 31b (metal silicide film 26b) of the p channel MISFET 30b is higher than that of nickel silicide (NiSiy). Consequently, the work function of the gate electrode 31a of the n channel MISFET 30a is lower than that of the gate electrode 31b of the p channel MISFET 30b.
The solid solubility S31a (corresponding to horizontal axis of
Similarly, the solid solubility S31b (corresponding to horizontal axis of
As shown in
Also, in the gate electrode 31a of the n channel MISFET 30a, the solid solubility S31a of metal with a work function lower than that of Ni (that is, the ratio of the number of atoms NM1 of the metal with a work function lower than that of Ni to the sum of the number of NNi atoms Ni and the number of atoms NM1 of metal with a work function lower than that of Ni in the gate electrode 31a) is preferably set in the range of 0.1 to 20% and is more preferably set in the range of 0.2 to 10%. By setting the solid solubility S31a of metal with a work function lower than that of Ni preferably to 0.1% or more and more preferably to 0.2% or more in the gate electrode 31a of the n channel MISFET 30a, the flat band voltage (work function) of the gate electrode 31a of the n channel MISFET 30a can be appropriately reduced, and thus, the absolute value of the threshold voltage of the n channel MISFET 30a can be appropriately reduced. In addition, if the Ni concentration (Ni content) of the metal film 25a is too low, when the silicon film 6 constituting the gate electrode 11a is reacted with the metal film 25a to form the gate electrode 31a, the silicidation reaction is suppressed, and as a result, the unreacted silicon may be left in the gate electrode 31a. For its prevention, the Ni concentration (Ni content) of the metal film 25a is controlled to a certain level or higher (preferably to 80 atom % or higher, more preferably 90 atom % or higher) so that the solid solubility S31a of metal with a work function lower than that of Ni in the gate electrode 31a of the n channel MISFET 30a can be controlled to 20% or lower, more preferably, to 10% or lower. By doing so, the silicidation reaction can be appropriately performed when the silicon film 6 constituting the gate electrode 11a is reacted with the metal film 25a to form the gate electrode 31a, and thus, it is possible to prevent the unreacted silicon from being left in the gate electrode 31a. In addition, since the silicon film 6 can be sufficiently reacted with the metal film 25a to form the gate electrode 31a at a relatively low temperature, the reaction between the gate insulating film 5 and the semiconductor substrate 1 and the reaction between the gate insulating film 5 and the silicon film 6 during the process can be prevented.
Also, in the gate electrode 31b of the p channel MISFET 30b, the solid solubility S31b of metal with a work function higher than that of Ni (that is, the ratio of the number of atoms NM2 of the metal with a work function higher than that of Ni to the sum of the number of NNi atoms Ni and the number of atoms NM2 of metal with a work function higher than that of Ni in the gate electrode 31b) is preferably set in the range of 0.1 to 20% and is more preferably set in the range of 0.2 to 10%. By setting the solid solubility S31b of metal with a work function higher than that of Ni preferably to 0.1% or more and more preferably to 0.2% or more in the gate electrode 31b of the p channel MISFET 30b, the flat band voltage (work function) of the gate electrode 31b of the p channel MISFET 30b can be appropriately increased, and thus, the absolute value of the threshold voltage of the p channel MISFET 30b can be appropriately reduced. In addition, if the Ni concentration (Ni content) of the metal film 25b is too low, when the silicon film 6 constituting the gate electrode 11b is reacted with the metal film 25b to form the gate electrode 31b, the silicidation reaction is suppressed, and as a result, the unreacted silicon may be left in the gate electrode 31b. For its prevention, the Ni concentration (Ni content) of the metal film 25b is controlled to a certain level or higher (preferably to 80 atom % or higher, more preferably 90 atom % or higher) so that the solid solubility S31b of metal with a work function higher than that of Ni in the gate electrode 31b of the p channel MISFET 30b can be controlled to 20% or lower, more preferably, to 10% or lower. By doing so, the silicidation reaction can be appropriately performed when the silicon film 6 constituting the gate electrode 11b is reacted with the metal film 25b to form the gate electrode 31b, and thus, it is possible to prevent the unreacted silicon from being left in the gate electrode 31b. In addition, since the silicon film 6 can be sufficiently reacted with the metal film 25b to form the gate electrode 31b at a relatively low temperature, the reaction between the gate insulating film 5 and the semiconductor substrate 1 and the reaction between the gate insulating film 5 and the silicon film 6 during the process can be prevented.
According to this embodiment described above, in the n channel MISFET 30a, metal with a work function lower than that of Ni is contained (solid-solved) in the gate electrode 31a mainly comprised of nickel silicide to adjust the work function (flat band voltage) of the gate electrode 31a (to be lower than that of nickel silicide), thereby controlling the threshold voltage of the n channel MISFET 30a (reducing the threshold voltage). Also, in the p channel MISFET 30b, metal with a work function higher than that of Ni is contained (solid-solved) in the gate electrode 31b mainly comprised of nickel silicide to adjust the work function (flat band voltage) of the gate electrode 31b (to be higher than that of nickel silicide), thereby controlling the threshold voltage of the p channel MISFET 30b (reducing the threshold voltage). As a result, the threshold voltage of the n channel MISFET 30a and the p channel MISFET 30b of the CMISFET can be reduced. Consequently, the performance of a semiconductor device having the CMISFET can be improved. In addition, it is possible to acquire a semiconductor device having the CMISFET with large On-current and low threshold voltage. Furthermore, the gate electrodes 31a and 31b with good symmetry can be located around midgap, and thus, the CMISFET with good characteristics can be acquired.
Also, in the case where the silicon film 6 constituting the gate electrode 11b of the p channel MISFET is a silicon film introduced (doped) with a p type impurity, in particular, B (boron) (for example, B doped polysilicon film) unlike this embodiment, there is the possibility that the p type impurity (boron) in the silicon film constituting the gate electrode 11b of the p channel MISFET penetrates through the gate insulating film 5 and diffuses in the channel region below the gate insulating film 5 in the annealing process for activating the impurity introduced in the silicon film 6, the n31 type semiconductor region 12, the p− type semiconductor region 13, the n+ type semiconductor region 15, and the p+ type semiconductor region 16. This probably deteriorates the performance and reliability of the semiconductor device.
Meanwhile, according to this embodiment, since the silicon film 6 is reacted with the metal film 25a which is an Ni film in which metal with a work function lower than that of Ni is contained (solid-solved) to form the gate electrode 31a of the n channel MISFET 30a, the metal with a work function lower than that of Ni is contained (solid-solved) in the gate electrode 31a. By doing so, the work function (flat band voltage) of the gate electrode 31a is adjusted (to be lower than that of nickel silicide) to control the threshold voltage of the n channel MISFET 30a (reduce the threshold voltage). Also, since the silicon film 6 is reacted with the metal film 25b which is an Ni film in which metal with a work function higher than that of Ni is contained (solid-solved) to form the gate electrode 31b of the p channel MISFET 30b, the metal with a work function higher than that of Ni is contained (solid-solved) in the gate electrode 31b. By doing so, the work function (flat band voltage) of the gate electrode 31b is adjusted (to be lower than that of nickel silicide) to control the threshold voltage of the p channel MISFET 30b (reduce the threshold voltage). Therefore, a nondope silicon film doped with no impurity (for example, nondope polysilicon film or nondope amorphous silicon film) can be used as the silicon film 6. By using the nondope silicon film in which no impurity is introduced as the silicon film 6, it is possible to prevent the p type impurity (boron or the like) from penetrating through the gate insulating film 5 and diffusing in the channel region below the gate insulating film 5 in the annealing process for activating the impurity introduced in the n− type semiconductor region 12, the p− type semiconductor region 13, the n+ type semiconductor region 15, and the p+ type semiconductor region 16. Therefore, it is possible to improve the performance and reliability of the semiconductor device.
Furthermore, according to this embodiment, the solid solubility S31a of metal with a work function lower than that of Ni in the gate electrode 31a can be controlled by adjusting the content (concentration) of metal with a work function lower than that of Ni in the metal film 25a, and the solid solubility S31b of metal with a work function higher than that of Ni in the gate electrode 31b can be controlled by adjusting the content (concentration) of metal with a work function higher than that of Ni in the metal film 25b. Therefore, it is possible to easily control the threshold voltage of the n channel MISFET 30a and the p channel MISFET 30b.
Also, when a metal film is directly formed on the gate insulating film 5 by the sputtering method unlike this embodiment, there is the possibility that the gate insulating film 5 is damaged. However, in this embodiment, the silicon film 6 is formed on the gate insulating film 5 by the CVD method, and the silicon film 6 is reacted with the metal films 25a and 25b formed thereon to form the gate electrodes 31a and 31b composed of the metal silicide films 26a and 26b. Therefore, it is possible to prevent the gate insulating film 5 from being damaged.
Also, since an Ni containing film (Ni alloy) mainly comprised of Ni (nickel) is used for the metal films 25a and 25b in this embodiment, the full silicidation reaction can be comprised by the thermal treatment at a relatively low temperature. More specifically, the temperature of the thermal treatment in which the silicon film 6 (gate electrodes 11a and 11b) is reacted with the metal films 25a and 25b to form the metal silicide films 26a and 26b (gate electrodes 31a and 31b) can be comprised relatively low. In addition, all of the silicon film 6 constituting the gate electrodes 11a and 11b can be reacted with the metal films 25a and 25b to form the metal silicide films 26a and 26b (gate electrodes 31a and 31b), and therefore, it is possible to prevent the unreacted silicon film 6 from being left on the gate insulating film 5. Furthermore, it is possible to suppress or prevent the reaction between the gate insulating film 5 and the semiconductor substrate 1 and between the gate insulating film 5 and the silicon film 6 in the thermal treatment process. As a result, the performance and reliability of the semiconductor device can be further improved.
Also, when the source and drain regions are formed after forming the metal gate electrodes unlike this embodiment, there is the possibility that the electrical characteristics of the MISFET are deteriorated because the metal constituting the gate electrode is reacted with the gate insulating film, the gate electrode is peeled from the gate insulating film, or the metal atoms of the gate electrode are diffused in the gate insulating film and the silicon substrate in the high-temperature annealing for activating the impurity introduced into the source and drain regions by the ion implantation method (activation annealing). In this embodiment, after the annealing process for activating the impurity introduced (ion-implanted) into the source and drain regions (n− type semiconductor region 12, p− type semiconductor region 13, n+ type semiconductor region 15, and p+ type semiconductor region 16) of the MISFET, the silicon film 6a (gate electrodes 11a and 11b) is reacted with the metal films 25a and 25b formed thereon to form the gate electrodes 31a and 31b composed of the metal silicide films 26a and 26b. Therefore, it is possible to prevent the reaction between the gate electrode and the gate insulating film, the peeling of the gate electrode from the gate insulating film, and the diffusion of metal atoms of the gate electrode into the gate insulating film and the silicon substrate in the annealing process for activating the impurity. As a result, the deterioration of the electrical characteristics of the MISFET can be prevented.
Also, in this embodiment, after forming the gate electrodes 11a and 11b composed of the silicon film 6a, they are reacted with the metal films 25a and 25b to form the gate electrodes 31a and 31b composed of the metal silicide films 26a and 26b. Therefore, the manufacturing line and the manufacturing apparatus for a semiconductor device with a conventional polysilicon gate electrode structure can be used without modification, and the semiconductor device with a metal gate electrode structure can be easily manufactured at low cost.
FIGS. 15 to 20 are cross-sectional views showing the principal part in the process of a manufacturing of a semiconductor device according to another embodiment of the present invention. Since the process of a manufacturing until
After forming the structure shown in
Next, as shown in
Next, as shown in
Next, as shown in
Note that, in this embodiment, the ion implantation 52 into the metal film 25c in the n channel MISFET forming region 1A is first performed and then the ion implantation 54 into the metal film 25c in the p channel MISFET forming region 1B is performed. However, as another embodiment, the ion implantations 52 and 54 can be performed in the opposite order. That is, the ion implantation 54 into the metal film 25c in the p channel MISFET forming region 1B is first performed and then the ion implantation 52 into the metal film 25c in the n channel MISFET forming region 1A is performed.
Next, as shown in
As described above, metal (metal element) with a work function lower than that of Ni (nickel) is introduced by the ion implantation 52 into the metal film 25c in the n channel MISFET forming region 1A, and the metal film (Ni film) 25c in which metal with a work function lower than that of Ni (nickel) is introduced is reacted with the silicon film 6 constituting the gate electrode 11a to form the metal silicide film 26c. Therefore, the metal silicide film 26c is comprised of metal silicide which contains (as constituent elements) Ni (nickel), metal with a work function lower than that of Ni (for example, Ti (titanium), Hf (hafnium), Zr (zirconium), Ta (tantalum)), and Si (silicon), and is comprised of, for example, the metal alloy of these constituent elements. More specifically, the metal silicide film 26c is comprised of nickel silicide in which metal with a work function lower than that of Ni (for example, Ti (titanium), Hf (hafnium), Zr (zirconium), Ta (tantalum)) is solid-solved. It is considered that the metal (metal element) with a work function lower than that of Ni is solid-solved in the nickel site of the nickel silicide. Therefore, the metal silicide film 26c is composed of, for example, an Ni1-xMxSiy film (M indicates metal with a work function lower than that of Ni). This metal silicide film 26c is to be the gate electrode 31a of the n channel MISFET 30a. Therefore, since the gate electrode 31a of the n channel MISFET 30a is composed of the metal silicide film 26c (showing metallic conduction), the gate electrode 31a is a metal gate electrode.
Also, as described above, metal (metal element) with a work function higher than that of Ni (nickel) is introduced by the ion implantation 54 into the metal film 25c in the p channel MISFET forming region 1B, and the metal film (Ni film) 25c in which metal with a work function higher than that of Ni (nickel) is introduced is reacted with the silicon film 6 constituting the gate electrode 11b to form the metal silicide film 26d. Therefore, the metal silicide film 26d is comprised of metal silicide which contains (as constituent elements) Ni (nickel), metal with a work function higher than that of Ni (for example, Pt (platinum), Ir (iridium), or Ru (ruthenium)), and Si (silicon), and is comprised of, for example, the metal alloy of these constituent elements. More specifically, the metal silicide film 26d is comprised of nickel silicide in which metal with a work function higher than that of Ni (for example, Pt (platinum), Ir (iridium), or Ru (ruthenium)) is solid-solved. It is considered that the metal (metal element) with a work function higher than that of Ni is solid-solved in the nickel site of the nickel silicide. Therefore, the metal silicide film 26d is composed of, for example, an Ni1-xMxSiy film (M indicates metal with a work function higher than that of Ni). This metal silicide film 26d is to be the gate electrode 31b of the p channel MISFET 30b. Therefore, since the gate electrode 31b of the p channel MISFET 30b is composed of the metal silicide film 26d (showing metallic conduction), the gate electrode 31b is a metal gate electrode.
Also, in this embodiment, after the ion implantations 52 and 54 are performed to the metal film 25c composed of an Ni film, the silicon film 6 is reacted with the metal film 25c to form the gate electrodes 31a and 31b. Therefore, it is possible to form the gate electrode 31a containing metal with a work function lower than that of Ni and the gate electrode 31b containing metal with a work function higher than that of Ni in a relatively simple manufacturing process.
The subsequent manufacturing process is almost identical to that described in the first embodiment. That is, as shown in
Also in this embodiment, the effects almost similar to those in the first embodiment can be obtained. For example, in the n channel MISFET 30a, metal with a work function lower than that of Ni is contained in the gate electrode 31a mainly comprised of nickel silicide to adjust the work function (flat band voltage) of the gate electrode 31a (to be lower than that of nickel silicide), thereby controlling the threshold voltage of the n channel MISFET 30a (reducing the threshold voltage). Also, in the p channel MISFET 30b, metal with a work function higher than that of Ni is contained in the gate electrode 31b mainly comprised of nickel silicide to adjust the work function (flat band voltage) of the gate electrode 31b (to be higher than that of nickel silicide), thereby controlling the threshold voltage of the p channel MISFET 30b (reducing the threshold voltage). As a result, the threshold voltage of the n channel MISFET 30a and the p channel MISFET 30b of the CMISFET can be reduced. Consequently, the performance of a semiconductor device having the CMISFET can be improved. In addition, it is possible to acquire a semiconductor device having the CMISFET with large On-current and low threshold voltage. Furthermore, the gate electrodes 31a and 31b with good symmetry can be located around midgap, and thus, the CMISFET with good characteristics can be acquired. In addition, since a nondope silicon film doped with no impurity can be used as the silicon film 6, it is possible to prevent the p type impurity (boron or the like) from penetrating through the gate insulating film 5 and diffusing in the channel region below the gate insulating film 5 in the annealing process for activating the impurity introduced in the n− type semiconductor region 12, the p− type semiconductor region 13, the n+ type semiconductor region 15, and the p+ type semiconductor region 16. Therefore, it is possible to improve the performance and reliability of the semiconductor device.
FIGS. 21 to 26 are cross-sectional views showing the principal part in the manufacturing process of a semiconductor device according to another embodiment of the present invention. Since the manufacturing process until
After forming the structure shown in
Next, as shown in
Next, as shown in
Next, as shown in
Next, as shown in
As described above, metal (metal element) with a work function lower than that of Ni (nickel) is introduced by the ion implantation 62 into the metal silicide film 26e in the n channel MISFET forming region 1A. Therefore, the metal silicide film 26e is comprised of metal silicide which contains (as constituent elements) Ni (nickel), metal with a work function lower than that of Ni (for example, Ti (titanium), Hf (hafnium), Zr (zirconium), Ta (tantalum)), and Si (silicon). More specifically, the metal silicide film 26e is comprised of nickel silicide in which metal with a work function lower than that of Ni (for example, Ti (titanium), Hf (hafnium), Zr (zirconium), Ta (tantalum)) is introduced (solid-solved, contained). This metal silicide film 26e is to be the gate electrode 31a of the n channel MISFET 30a. Therefore, since the gate electrode 31a of the n channel MISFET is composed of the metal silicide film 26e (showing metallic conduction), the gate electrode 31a is a metal gate electrode.
Also, as described above, metal (metal element) with a work function higher than that of Ni (nickel) is introduced by the ion implantation 64 into the metal silicide film 26f in the p channel MISFET forming region 1B. Therefore, the metal silicide film 26f is comprised of metal silicide which contains (as constituent elements) Ni (nickel), metal with a work function higher than that of Ni (for example, Pt (platinum), Ir (iridium), Ru (ruthenium)), and Si (silicon). More specifically, the metal silicide film 26f is comprised of nickel silicide in which metal with a work function higher than that of Ni (for example, Pt (platinum), Ir (iridium), Ru (ruthenium)) is introduced (solid-solved, contained). This metal silicide film 26f is to be the gate electrode 31b of the p channel MISFET 30b. Therefore, since the gate electrode 31b of the p channel MISFET is composed of the metal silicide film 26f (showing metallic conduction), the gate electrode 31b is a metal gate electrode.
Note that, in this embodiment, the ion implantation 62 into the metal silicide film 26e in the n channel MISFET forming region 1A is first performed and then the ion implantation 64 into the metal silicide film 26f in the p channel MISFET forming region 1B is performed. However, as another embodiment, the ion implantations 62 and 64 can be performed in the opposite order. That is, the ion implantation 64 into the metal silicide film 26f in the p channel MISFET forming region 1B is first performed and then the ion implantation 62 into the metal silicide film 26e in the n channel MISFET forming region 1A is performed.
In this embodiment, after the silicon film 6 is reacted with the metal film 25e composed of an Ni film to form the gate electrodes 31a and 31b, the ion implantation 62 into the gate electrode 31a is performed and then the ion implantation 64 is performed to the gate electrode 31b. Therefore, it is possible to form the gate electrode 31a containing metal with a work function lower than that of Ni and the gate electrode 31b containing metal with a work function higher than that of Ni in a relatively simple manufacturing process.
The subsequent manufacturing process is almost identical to that described in the first embodiment. That is, as shown in
Also in this embodiment, the effects almost similar to those in the first embodiment can be obtained. For example, in the n channel MISFET 30a, metal with a work function lower than that of Ni is contained in the gate electrode 31a mainly comprised of nickel silicide to adjust the work function (flat band voltage) of the gate electrode 31a (to be lower than that of nickel silicide), thereby controlling the threshold voltage of the n channel MISFET 30a (reducing the threshold voltage). Also, in the p channel MISFET 30b, metal with a work function higher than that of Ni is contained in the gate electrode 31b mainly comprised of nickel silicide to adjust the work function (flat band voltage) of the gate electrode 31b (to be higher than that of nickel silicide), thereby controlling the threshold voltage of the p channel MISFET 30b (reducing the threshold voltage). As a result, the threshold voltage of the n channel MISFET 30a and the p channel MISFET 30b of the CMISFET can be reduced. Consequently, the performance of a semiconductor device having the CMISFET can be improved. In addition, it is possible to acquire a semiconductor device having the CMISFET with large On-current and low threshold voltage. Furthermore, the gate electrodes 31a and 31b with good symmetry can be located around midgap, and thus, the CMISFET with good characteristics can be acquired. In addition, since a nondope silicon film doped with no impurity can be used as the silicon film 6, it is possible to prevent the p type impurity (boron or the like) from penetrating through the gate insulating film 5 and diffusing in the channel region below the gate insulating film 5 in the annealing process for activating the impurity introduced in the n− type semiconductor region 12, the p− type semiconductor region 13, the n+ type semiconductor region 15, and the p+ type semiconductor region 16. Therefore, it is possible to improve the performance and reliability of the semiconductor device.
In the foregoing, the invention comprised by the inventors of the present invention has been concretely described based on the embodiments. However, it is needless to say that the present invention is not limited to the foregoing embodiments and various modifications and alterations can be comprised within the scope of the present invention.
The present invention is effectively applied to a semiconductor device in which the gate electrodes of the MISFETs are comprised of metal silicide and a manufacturing method thereof.
| Number | Date | Country | Kind |
|---|---|---|---|
| 2004-190589 | Jun 2004 | JP | national |
