Patent Application
20150228787
The embodiments of the present invention relate to a semiconductor device and manufacturing method thereof.
In recent years, a TFET (Tunnel Field-Effect Transistor) that employs a quantum-mechanical effect of electrons has been developed. In the TFET, by applying a voltage to a gate electrode, BTBT (Band To Band Tunneling) is caused between a source and a channel. As a result, the TFET becomes an on-state.
To increase an on-state current of a TFET, it is effective to introduce strain in a substrate. By introducing strain in a substrate, a bandgap of the substrate becomes narrow and effective mass of conductive carrier is reduced. Tunneling efficiency is thus improved, which increases the on-state current.
In a TFET, the on-state current is determined by tunneling efficiency on the side of a source. Meanwhile, an off-state current is determined by tunneling efficiency on the side of a drain. Therefore, if uniform strain is applied to the side of a source and the side of a drain, there is a problem that not only the on-state current but also the off-state current is increased.
Embodiments will now be explained with reference to the accompanying drawings. The present invention is not limited to the embodiments. In the embodiments, “an upper direction” or “a lower direction” refers to a relative direction when a direction of a surface of a semiconductor layer on which semiconductor elements are provided is assumed as “an upper direction”. Therefore, the term “upper direction” or “lower direction” occasionally differs from an upper direction or a lower direction based on a gravitational acceleration direction.
A semiconductor device according to an embodiment includes a semiconductor layer. A first conductivity-type source layer is provided in the semiconductor layer. A second conductivity-type drain layer is provided in the semiconductor layer. A gate dielectric film is provided on the semiconductor layer between the source layer and the drain layer. A gate electrode includes a first gate part partially provided on the gate dielectric film on a side of the source layer and a second gate part partially provided on the gate dielectric film on a side of the drain layer. A length of crystal grains of the first gate part in a channel length direction is longer than that of crystal grains of the second gate part in the channel length direction.
The TFET 100 includes a semiconductor layer 10, a source layer S, a drain layer D, a gate dielectric film 20, a gate electrode G, a sidewall film 40, and an interlayer dielectric film 60.
The semiconductor layer 10 can be a semiconductor substrate such as a silicon substrate or can be an SOI (Silicon On Insulator) layer on a BOX layer.
The p-type (first conductivity-type) source layer S is formed on a surface region of the semiconductor layer 10. The n-type (second conductivity-type) drain layer D is formed on another surface region of the semiconductor layer 10. The source layer S is formed by implanting a p-type impurity (for example, boron) in the semiconductor layer 10. The drain layer D is formed by implanting an n-type impurity (for example, arsenic or phosphorus) in the semiconductor layer 10. The source layer S is formed on a surface region of the semiconductor layer 10 on the opposite side of the drain layer D across the gate electrode G.
Shallow trench isolation regions STI are provided in the semiconductor layer 10 in order to electrically isolate the TFET 100 from other elements. For example, the shallow trench isolation regions STI are formed of an insulation film such as a silicon oxide film.
The gate dielectric film 20 is provided on the semiconductor layer 10 between the drain layer D and the source layer S. For example, the gate dielectric film 20 is formed of a silicon oxide film, a silicon oxynitride film, or a dielectric film having a higher dielectric constant than that of the silicon oxide film (for example, HfO2).
The gate electrode G is provided on the gate dielectric film 20. The gate electrode G includes a first gate part Gs on the side of the source layer S and a second gate part Gd on the side of the drain layer D. The first gate part Gs is partially provided on the gate dielectric film 20 on the side of the source layer S. The second gate part Gd is partially provided on the gate dielectric film 20 on the side of the drain layer D.
The first and second gate parts Gs and Gd are both formed of a conductive material such as doped polysilicon or a metal. More specifically, in the first embodiment, the first and second gate parts Gs and Gd are both formed of doped polysilicon. The length of crystal grains of the first gate part Gs in a channel length direction Dch is longer than that of crystal grains of the second gate part Gd in the channel length direction Dch. That is, crystal grains of polysilicon that forms the first gate part Gs are horizontally (laterally) longer than those of polysilicon that forms the second gate part Gd. The height of the first gate part Gs is lower than that of the second gate part Gd. This is because the crystal grains of the first gate part Gs extend in the channel length direction Dch.
Because the crystal grains of the first gate part Gs extend in the channel length direction Dch, the first gate part Gs has a stress to extend in the channel length direction Dch. On the other hand, unlike the first gate part Gs, the second gate part Gd does not have the stress to extend in the channel length direction Dch. Alternatively, the stress of the second gate part Gd is relatively small.
The sidewall film 40 is provided on both side surfaces of the gate electrode G. The sidewall film 40 covers a side surface of the first gate part Gs on the side of the source layer S and a side surface of the second gate part Gd on the side of the drain layer D. For example, the sidewall film 40 is formed of an insulation film such as a silicon oxide film.
The interlayer dielectric film 60 is provided on the gate electrode G and the semiconductor layer 10. For example, the interlayer dielectric film 60 is an insulation film such as a silicon oxide film using TEOS (Tetraethylorthosilicate).
In the first embodiment, as compared to the second gate part Gd, the first gate part Gs has the stress to extend in the channel length direction Dch. Therefore, the first gate part Gs applies a stress to a channel part CH on the side of the source layer S. The second gate part Gd applies a smaller stress to the channel part CH on the side of the drain layer D. As a result, a stress applied to a junction (a source edge) ES between the source layer S and the channel part CH is larger than a stress applied to a junction (a drain edge) ED between the drain layer D and the channel part CH. Arrows A in
By setting the stress applied to the source layer S and the source edge ES larger than the stress applied to the drain layer D and the drain edge ED as explained above, tunneling efficiency on the side of the source layer S that determines an on-state current can be improved without increasing tunneling efficiency on the side of the drain layer D that determines an off-state current. Consequently, the TFET 100 can increase the on-state current while suppressing an increase in the off-state current.
According to the first embodiment, the first gate part Gs itself can have a stress and apply the stress to the source edge ES. That is, according to the first embodiment, a stress memorization technique (SMT) is employed to apply a relatively large stress to the source layer S and the source edge ES. In the first embodiment, a stress application film does not need to remain on the gate electrode G for stress application.
Next, a material for the second gate part Gd is deposited on the material for the gate dielectric film 20 by a CVD (Chemical Vapor Deposition) method. For example, the material for the second gate part Gd is polysilicon. Polysilicon is obtained by film formation of silicon in an atmosphere at a relatively high temperature of about 1000° C. by the CVD method. Next, for example, an n-type impurity (for example, phosphorus) is implanted in the material for the second gate part Gd by an ion implantation method. As a result, the material for the second gate part Gd becomes conductive doped polysilicon. Next, a hard mask HM is deposited on the material for the second gate part Gd by the CVD method. For example, a material for the hard mask HM is an insulation film such as a silicon oxide film. As a result, a configuration shown in
Next, the materials for the hard mask HM and the second gate part Gd are processed by a lithographic technique and an etching technique. At this time, the hard mask HM and the second gate part Gd on a region where the source layer S is formed (hereinafter, “source-layer-S formation region”) and a region where the first gate part Gs is formed (hereinafter, “first-gate-part-Gs formation region”) are removed. As a result, a configuration shown in
Next, as shown in
Next, the material for the first gate part Gs is anisotropically etched by an RIE (Reactive Ion Etching) method. As a result, as shown in
Next, the materials for the hard mask HM and the second gate part Gd are processed by the lithographic technique and the RIE method. As a result, as shown in
Next, parts of the hard mask HM and the gate dielectric film 20 are removed by wet etching using a DHF (Dilute Hydrofluoric Acid) or the like. As a result, as shown in
Next, a material for the sidewall film 40 is deposited on top and side surfaces of the gate electrode G and on the semiconductor layer 10 by the CVD method. For example, the material for the sidewall film 40 is an insulation film such as a silicon oxide film. For example, the film thickness of the material of the sidewall film 40 is about 30 nanometers. Next, the material for the sidewall film 40 is anisotropically etched by the RIE method. As a result, as shown in
Next, as shown in
After the resist film 42 is removed, the source-layer-S formation region is covered by a resist film 44 by the lithographic technique as shown in
After the resist film 44 is removed, a stress inducing layer 50 is deposited on the gate electrode G and the semiconductor layer 10 by the CVD method as shown in
Next, a thermal process is performed to cause the first gate part Gs to memorize a stress due to the stress inducing layer 50. For example, the semiconductor layer 10 and the gate electrode G are thermally processed at a temperature of about 1050° C. by a spike annealing method. At this time, amorphous silicon of the first gate part Gs is altered into polysilicon. When amorphous silicon is altered into polysilicon, crystal grains of silicon grow while extending horizontally (in a channel length direction) because the top of the first gate part Gs is blocked by the stress inducing layer 50. As a result, the crystal grains of the first gate part Gs become polysilicon that extends horizontally (in the channel length direction) compared to crystal grains of the second gate part Gd. Because left and right sides of the first gate part Gs are also blocked by the sidewall film 40 and the second gate part Gd, respectively, strain due to the extension is applied to a bottom of the first gate part Gs.
Because the first gate part Gs is altered into polysilicon having a horizontally-extending grain diameter, the first gate part Gs become lower as shown in
The thermal process for stress memorization also has a function of activating the impurities in the source layer S and the drain layer D. As a result, the source layer S is formed in the semiconductor layer 10 on the side of the first gate part Gs of the gate electrode G. The drain layer D is formed in the semiconductor layer 10 on the side of the second gate part Gd of the gate electrode G.
Next, the stress inducing layer 50 is removed. The first gate part Gs has been altered into polysilicon having the grain diameter that horizontally extends during the thermal process. For this reason, even when the stress inducing layer 50 is removed, the crystal grains of the first gate part Gs keep to extend horizontally (in the channel length direction). That is, the first gate part Gs memorizes a stress and continuously applies the stress to the source edge ES and the periphery thereof.
Thereafter, the interlayer dielectric film 60, contact plugs, and wires are formed, so that the TFET 100 is completed. According to the first embodiment, it is possible to cause the first gate part Gs to memorize a stress by using the stress inducing layer 50 and the thermal process. That is, with the stress memorization technique, the first gate part Gs itself can have a stress and apply the stress to the source edge ES.
The stress applied to the source layer S and the source edge ES can thus be set larger than that applied to the drain layer D and the drain edge ED. As a result, the TFET 100 can improve tunneling efficiency on the side of the source layer S that determines an on-state current without increasing tunneling efficiency on the side of the drain layer D that determines an off-state current.
The TFET 100 according to the first embodiment includes the gate electrode G made of polysilicon. However, the gate electrode G can be formed of a metal material. In this case, materials for the first and second gate parts Gs and Gd are selected to set the thermal expansion coefficient of the first gate part Gs larger than that of the second gate part Gd. Alternatively, the materials for the first and second gate parts Gs and Gd are selected to set the Young's modulus of the first gate part Gs smaller than that of the second gate part Gd. For example, combinations of the materials for the first gate part Gs and the second gate part Gd are as follows. That is, the material for the first gate part Gs is titanium nitride (TiN) and the material for the second gate part Gd is tungsten carbide (WC). Alternatively, the material for the first gate part Gs is tantalum carbide (TaC) and the material for the second gate part Gd is tungsten carbide (WC). These combinations satisfy the conditions of the thermal expansion coefficient or the Young's modulus mentioned above. Accordingly, even when the gate electrode G is formed of these metal materials, the stress applied to the source layer S and the source edge ES can be larger than that applied to the drain layer D and the drain edge ED, and effects of the first embodiment are not lost.
When the gate electrode G is formed of a metal material, it suffices that the metal material for the second gate part Gd is deposited in
Next, materials for the first gate part Gs and the second gate part Gd are deposited on a material for the gate dielectric film 20 by the CVD method. At first, the materials for the first gate part Gs and the second gate part Gd are, for example, polysilicon. Polysilicon is obtained by film formation of silicon in an atmosphere at a relatively high temperature of about 1000° C. by the CVD method. Next, an n-type impurity (for example, phosphorus) is implanted in the materials for the first and second gate parts Gs and Gd by, for example, the ion implantation method. As a result, the materials for the first and second gate parts Gs and Gd become conductive doped polysilicon. Consequently, a configuration shown in
Next, as shown in
Next, polysilicon and amorphous silicon are processed by the lithographic technique and the etching technique. As a result, as shown in
Processes explained with reference to
According to the manufacturing method of the second embodiment, polysilicon and amorphous silicon do not need to be deposited separately. As a result, according to the second embodiment, the first gate part Gs that has memorized a stress can be formed relatively easily. Furthermore, the second embodiment can also achieve effects identical to those of the first embodiment.
Other configurations of the third embodiment can be identical to those of the second embodiment. Stress characteristics of the first gate part Gs and other electrical characteristics of the TFET 300 can be identical to those of the second embodiment. Therefore, the third embodiment can also achieve effects identical to those of the second embodiment.
Next, as shown in
Next, as explained with reference to
Next, as shown in
Next, an inert element having a larger atomic weight than that of silicon is introduced in the first-gate-part-Gs formation region and the source-layer-S formation region by using the resist film 48 as a mask. For example, ions of germanium (Ge) are implanted in the first-gate-part-Gs formation region. As a result, polysilicon in a region of the first gate part Gs is amorphized. At the same time, ions of germanium (Ge) are implanted also in the source-layer-S formation region. As a result, the semiconductor layer 10 in the source-layer-S formation region is amorphized. Because not only the first gate part Gs but also the source-layer-S formation region is amorphized, a stress from the stress inducing layer 50 is easily introduced also in the source layer S as well as the first gate part Gs.
Processes explained with reference to
According to the manufacturing method of the third embodiment, not only the first gate part Gs but also the source layer S is amorphized. Because the Young's modulus of amorphous silicon is smaller than that of crystalline silicon, the effect of applying strain by the stress memorization technique is enhanced. Therefore, according to the third embodiment, it is possible to easily introduce a stress in not only the first gate part Gs but also the source layer S and cause the first gate part Gs and the source layer S to memorize the stress. Tunneling efficiency on the side of the source layer S can thus be further improved. In addition, by introducing germanium in the source layer S, a p-type impurity is hardly diffused and a concentration gradient of the source layer S becomes sharp. Furthermore, the third embodiment can also achieve effects identical to those of the second embodiment.
In the above embodiments, the N-TFETs 100 to 300 have been explained. However, it is needless to mention that the above embodiments can be applied to a P-TFET. In this case, the source layer S is an n-type diffusion layer and the drain layer D is a p-type diffusion layer.
While certain embodiments have been described, these embodiments have been presented by way of example only, and are not intended to limit the scope of the inventions. Indeed, the novel methods and systems described herein may be embodied in a variety of other forms; furthermore, various omissions, substitutions and changes in the form of the methods and systems described herein may be made without departing from the spirit of the inventions. The accompanying claims and their equivalents are intended to cover such forms or modifications as would fall within the scope and spirit of the inventions.
This application is based upon and claims the benefit of priority from the prior U.S. Provisional Patent Application No. 61/939,106, filed on Feb. 12, 2014, the entire contents of which are incorporated herein by reference.
| Number | Date | Country | |
|---|---|---|---|
| 61939106 | Feb 2014 | US |
