Preferred embodiments of the present invention will be described in detail below with reference to the accompanying drawings.
A first embodiment will be first described.
A MOS transistor 10 shown in
By forming such an extremely shallow high-concentration LDD region 15b under the sidewall 14, even if hot carriers are generated and accumulated in the sidewall 14 (in
This construction is applied, for example, to the case of forming a high-voltage transistor and a low-voltage transistor in the same chip, specifically, to a construction on a high-voltage transistor side. In this case, even when both sidewalls of the high-voltage transistor and the low-voltage transistor are formed using a SiO2 film simultaneously formed at a low temperature, depletion in the surface part of the LDD region of the high-voltage transistor can be effectively suppressed.
Further, when forming the above-described extremely shallow high-concentration LDD region on the high-voltage transistor side by ion implantation of predetermined impurities, the ion implantation is performed simultaneously with that in forming a source/drain/extension region (simply referred to as an “extension region”) on the low-voltage transistor side. As a result, formation of the high-voltage transistor and the low-voltage transistor can be effectively performed at low cost.
Here, a method of forming the high-voltage transistor and the low-voltage transistor in the same chip will be described in detail.
By taking as an example a case of forming transistors corresponding to two kinds of voltages such as a high-voltage transistor operating at 3.3 V and a low-voltage transistor operating at 1.2 V in the same chip, description will be made here by taking the respective n-channel portions into consideration.
First, an element isolation region (not shown) is formed in a silicon (Si) substrate 20 using an STI (Shallow Trench Isolation) method. Then, a SiO2 film having a predetermined thickness is formed in a predetermined region of the surface using a thermal oxidation method, and polysilicon is deposited over the film. Then, the polysilicon and the SiO2 film are processed to have predetermined shapes. Thus, gate oxide films 31 and 41 and gate electrodes 32 and 42 are formed in a formation region of an n-channel type MOS transistor corresponding to a 3.3 V power supply (referred to as a “3.3 V NMOS transistor”) and in a formation region of an n-channel type MOS transistor corresponding to a 1.2 V power supply (referred to as a “1.2 V NMOS transistor”) of the same Si substrate 20, respectively, as shown in
Thereafter, a resist is formed over the formation region of the 1.2 V NMOS transistor (not shown). Then, into the formation region of the 3.3 V NMOS transistor, phosphorus (P) as n-type impurities is ion-implanted using the gate electrode 32 as a mask, and the annealing at about 900 to 1050° C. is performed. Thus, an n-type low-concentration LDD region 33 is formed as an impurity region.
The ion implantation of P for forming the low-concentration LDD region 33 is performed, for example, under the conditions that an acceleration voltage is 15 to 40 keV, a dose is 1×1013 to 5×1013 cm−2 and a tilt angle is 0 degree. Alternatively, the ion implantation of P is performed four times under the conditions that an acceleration voltage is 15 to 40 keV, a dose is 2.5×1012 to 12×1012 cm−2 and a tilt angle is 28 degree.
After such ion implantation of P, the resist over the formation region of the 1.2 V NMOS transistor is removed, and the annealing at the above-described predetermined temperature is performed.
Subsequently, a resist is formed over the formation region of the 3.3 V NMOS transistor (not shown). Then, into the formation region of the 1.2 V NMOS transistor, boron (B) as a p-type impurity is ion-implanted using the gate electrode 42 as a mask to form a p-type pocket region 43 as an impurity region. Further, arsenic (As) as an n-type impurity is ion-implanted to form an n-type extension region 44 as an impurity region.
The ion implantation of boron (B) for forming the pocket region 43 is performed four times, for example, under the conditions that an acceleration voltage is 5 to 10 keV, a dose is 1×1012 to 15×1012 cm−2 and a tilt angle is 28 degree.
The ion implantation of arsenic (As) for forming the extension region 44 is performed, for example, under the conditions that an acceleration voltage is 3 keV, a dose is 1×1014 to 20×1014 cm−2 and a tilt angle is 0 degree.
After the ion implantation of B and As, the resist over the formation region of the 3.3 V NMOS transistor is removed.
The above-described annealing performed during the formation of the low-concentration LDD region 33 may be performed after the ion implantation for forming the pocket region 43 and the extension region 44 (after removal of the resist) without being performed at that time.
Subsequently, using a low-temperature CVD (Chemical Vapor Deposition) method at about 500 to 600° C., a SiO2 film is deposited over the entire surface and dry-etched. Thus, thin sidewalls 34 and 45 having a thickness of, for example, about 5 to 20 nm are formed over the side walls of the gate electrodes 32 and 42, respectively, as shown in
Thereafter, As is ion-implanted using as masks the gate electrodes 32 and 42 and the sidewalls 34 and 45 formed over the side walls of the electrodes 32 and 42. The ion implantation conditions are, for example, set such that an acceleration voltage is 1 to 7 keV, a dose is 5×1014 to 20×1014 cm−2 and a tilt angle is 0 degree. By this ion implantation of As, an extremely shallow n-type high-concentration LDD region 35 as an impurity region is formed in the formation region of the 3.3 V NMOS transistor. Further, an additional n-type extension region 46 as an impurity region is formed outside the previously formed extension region 44 in the formation region of the 1.2 V NMOS transistor.
Thus, in the first embodiment, the ion implantation for forming the extension region 46 in the formation region of the 1.2 V NMOS transistor is simultaneously performed by the same process as that of the ion implantation for forming the high-concentration LDD region 35 in the formation region of the 3.3 V NMOS transistor.
Subsequently, using a low-temperature CVD method at about 500 to 600° C., a SiO2 film is deposited over the entire surface and dry-etched. Thus, thick sidewalls 36 and 47 having, for example, a thickness of about 50 to 90 nm are formed outside the previously formed sidewalls 34 and 45, respectively, as shown in
Thereafter, using as masks the gate electrode 32 and the sidewalls 34 and 36 as well as the gate electrode 42 and the sidewalls 45 and 47, n-type impurities are ion-implanted to form n-type source/drain regions 37 and 48, respectively.
Thereafter, activation annealing at about 1000 to 1200° C. is performed to form silicide layers (not shown) over the surfaces of the gate electrodes 32 and 42 and the source/drain regions 37 and 48 by a silicide process. Thus, fundamental structures of the 3.3 V NMOS transistor and the 1.2 V NMOS transistor are completed. Hereafter, a chip having formed thereon the 3.3 V NMOS transistor and the 1.2 V NMOS transistor may be completed through the formations of interlayer insulating films, contact electrodes and wiring layers.
First, when forming no extremely shallow high-concentration LDD region 35 in the formation region of the 3.3 V NMOS transistor (the dose: 0 cm−2), the current Ids deteriorates by about 4% in terms of the specification.
In contrast, when forming the high-concentration LDD region 35 in the formation region of the 3.3 V NMOS transistor, the deterioration rate of the current Ids decreases in any case where the acceleration voltages in the ion implantation of As are 1 keV and 5 keV. Further, a reducing effect of the deterioration rate in the current Ids tends to increase with the increase in the dose of As in this measuring range. For example, the deterioration rate of the current Ids can be suppressed to about 0.15% under the conditions where the acceleration voltage is 5 keV and the dose is 1×1015 cm−2.
Thus, by forming the extremely shallow high-concentration LDD region 35 in the formation region of the 3.3 V NMOS transistor, even if hot carriers are generated and accumulated in the sidewall 36, depletion of the surface part of the LDD region due to hot carriers is suppressed, so that the deterioration of the current Ids can be effectively suppressed.
The ion implantation of AS for forming the extremely shallow high-concentration LDD region 35 is performed using as masks the gate electrode 32 and the thin sidewall 34 formed over the side wall of the electrode 32. Accordingly, As is ion-implanted apart from a region under the gate electrode 32 by a thickness of this sidewall 34. Therefore, the high-concentration LDD region 35 can be formed apart from a region under the gate electrode 32. As a result, a transverse electric field in channel is sufficiently relaxed, so that the generation of hot carriers and the threshold shift due to the hot carries can be effectively suppressed.
Further, the ion implantation of As for forming the extremely shallow high-concentration LDD region 35 can be performed by the same process as that in the ion implantation for forming the extension region 46 of the 1.2 V NMOS transistor. Therefore, a chip having formed thereon these MOS transistors can be efficiently formed at low cost. In this case, an impurity profile in the high-concentration LDD region 35 of the 3.3 V NMOS transistor and that in the extension region 46 of the 1.2 V NMOS transistor are the same.
The conditions for the ion implantation of As for forming the high-concentration LDD region 35 of the 3.3 V NMOS transistor may be set in consideration of the conditions for the simultaneously performed ion implantation for forming the extension region 46 of the 1.2 V NMOS transistor, the results as shown in
In the first embodiment, an n-channel portion of the MOS transistor is described. A p-channel portion thereof may be formed in parallel with the formation of the n-channel portion in accordance with the conventional method.
Next, a second embodiment will be described.
In this second embodiment, description will be made on the case of applying the principles of the first embodiment to a chip having formed thereon MOS transistors each corresponding to three kinds of voltages.
By taking as an example a case of forming MOS transistors corresponding to three kinds of voltages such as a high-voltage MOS transistor operating at 3.3 V, a high-voltage MOS transistor operating at 1.8 V and a low-voltage MOS transistor operating at 1.2 V in the same chip, description will be made here by taking the respective n-channel portions into consideration.
First, an element isolation region (not shown) is formed in a silicon (Si) substrate 20. Then, a SiO2 film having a predetermined thickness is formed in a predetermined region of the surface using a thermal oxidation method, and polysilicon is accumulated over the film. Then, the polysilicon and the SiO2 film are processed to have predetermined shapes. Thus, gate oxide films 31, 51 and 41 and gate electrodes 32, 52 and 42 are formed in a formation region of an 3.3 V NMOS transistor corresponding to a 3.3 V power supply, in a formation region of an n-channel type MOS transistor corresponding to a 1.8 V power supply (referred to as a “1.8 V NMOS transistor”) and in a formation region of a 1.2 V NMOS transistor corresponding to a 1.2 V power supply of the same substrate 20, respectively, as shown in
Thereafter, a resist is formed over the formation region of the 1.8 V NMOS transistor and the 1.2 V NMOS transistor (not shown). Then, into a formation region of the 3.3 V NMOS transistor, phosphorus (P) is ion-implanted using the gate electrode 32 as a mask under predetermined conditions as described in the first embodiment, and the annealing at a predetermined temperature is performed. Thus, an n-type low-concentration LDD region 33 is formed as an impurity region. After such ion implantation of P, the resists over the formation regions of the 1.8 V NMOS transistor and the 1.2 V NMOS transistor are removed.
Subsequently, resists are formed over the formation regions of the 3.3 V NMOS transistor and the 1.8 V NMOS transistor (not shown). Then, into the formation region of the 1.2 V NMOS transistor, boron (B) is ion-implanted using the gate electrode 42 as a mask to form a p-type pocket region 43 as an impurity region. Further, arsenic (As) is ion-implanted to form an n-type extension region 44 as an impurity region. The ion implantation of B and the ion implantation of As are respectively performed under the predetermined conditions as described in the first embodiment.
After the ion implantation of B and As, the resists over the formation regions of the 3.3 V NMOS transistor and the 1.8 V NMOS transistor are removed.
The above-described annealing performed during the formation of the low-concentration LDD region 33 may be performed after the ion implantation for forming the pocket region 43 and the extension region 44 (after removal of the resist) without being performed at that time.
Subsequently, using a low-temperature CVD method at about 500 to 600° C., a SiO2 film is deposited over the entire surface and dry-etched. Thus, sidewalls 34, 53 and 45 having a thickness of, for example, about 5 to 20 nm are formed over the side walls of the gate electrodes 32, 52 and 42, respectively, as shown in
Thereafter, As is ion-implanted using as masks the gate electrodes 32, 52 and 42 and the sidewalls 34, 53 and 45 formed over the side walls of the electrodes 32, 52 and 42 under the above-described predetermined conditions as described in the first embodiment. By this ion implantation of As, an extremely shallow n-type high-concentration LDD region 35 as an impurity region is formed in the formation region of the 3.3 V NMOS transistor. Further, an n-type LDD region 54 as an impurity region is formed in the formation region of the 1.8 V NMOS transistor. Further, an n-type extension region 46 as an impurity region is formed in the formation region of the 1.2 V NMOS transistor.
Subsequently, using a low-temperature CVD method at about 500 to 600° C., a SiO2 film is deposited over the entire surface and dry-etched. Thus, sidewalls 36, 55 and 47 having a thickness of, for example, about 50 to 90 nm are formed outside the sidewalls 34, 53 and 45, respectively, as shown in
Thereafter, using as masks the gate electrode 32 and the sidewalls 34, 36, the gate electrode 52 and the sidewalls 53, 55 as well as the gate electrode 42 and the sidewalls 45, 47, n-type impurities are ion-implanted to form n-type source/drain regions 37, 56 and 48.
Thereafter, the activation annealing at about 1000 to 1200° C. is performed to form silicide layers (not shown) over the surfaces of the gate electrodes 32, 52 and 42 and the source/drain regions 37, 56 and 48. Thus, fundamental structures of the 3.3 V NMOS transistor, the 1.8 V NMOS transistor and the 1.2 V NMOS transistor are completed. Hereafter, a chip having formed thereon the 3.3 V NMOS transistor, the 1.8 V NMOS transistor and the 1.2 V NMOS transistor may be completed through the formations of interlayer insulating films, contact electrodes and wiring layers.
Thus, in the second embodiment, the ion implantation for forming the high-concentration LDD region 35 in the formation region of the 3.3 V NMOS transistor, the ion implantation for forming the LDD region 54 in the formation region of the 1.8 V NMOS transistor, and the ion implantation for forming the extension region 46 in the formation region of the 1.2 V NMOS transistor are simultaneously performed by the same process as shown in
In the second embodiment, an n-channel portion of the MOS transistor is described. A p-channel portion thereof may be formed in parallel with the formation of the n-channel portion in accordance with the conventional method.
Next, a third embodiment will be described.
A MOS transistor 60 shown in
By forming such an extremely shallow counter region 66 in a surface part of the LDD region 65 under the sidewall 64, the surface part of the region 65 becomes a previously depleted state. Accordingly, even if hot carriers are generated and accumulated in the sidewall 64, the surface part of the LDD region 65 is prevented from being depleted (or scarcely depleted), so that characteristic deterioration of the MOS transistor 60 due to hot carriers can be suppressed. When the whole LDD region 65 is depleted, characteristics of the MOS transistor 60 are dramatically deteriorated. Therefore, the counter region 66 is formed only in the extremely shallow surface part of the LDD region 65.
Note, however, that in this case, a path of hot carriers on the drain side is formed apart from an interface between the semiconductor substrate 61 and the sidewall 64 (in
By a low-temperature process technology and an oxide thin film technology, a recent high-voltage transistor can obtain a large current as compared with a previous one. In forming the high-voltage transistor using such technologies, a method of decreasing the impurity concentration in the LDD region and intentionally increasing the resistance of the region to suppress the current is often performed to match its performance with that of a previous transistor, depending on the use thereof.
Accordingly, for example, as long as a level canceling a current increase portion obtained in using such technologies, when forming the counter region 66 with resistance increase, the MOS transistor 60 having a constant characteristic and suppressed in characteristic deterioration due to hot carriers can be obtained.
The construction as shown in
Further, when forming the above-described extremely shallow counter region on the high-voltage transistor side by ion implantation of predetermined impurities, the ion implantation is performed simultaneously with that in forming an extension region on the low-voltage transistor side. As a result, formation of the high-voltage transistor and the low-voltage transistor can be efficiently performed at low cost.
Here, the above-described principles will be described in detail by taking as an example a case of applying the principles to a chip having formed thereon the high-voltage transistor and the low-voltage transistor.
Description will be made here by taking as an example a case of forming transistors corresponding to two kinds of voltages such as a high-voltage transistor operating at 3.3 V and a low-voltage transistor operating at 1.2 V in the same chip.
First, an element isolation region (not shown) is formed in a silicon (Si) substrate 70 using an STI method. Then, a SiO2 film having a predetermined thickness is formed in a predetermined region of the surface using a thermal oxidation method, and polysilicon is deposited over the film. Then, the polysilicon and the SiO2 film are processed to have predetermined shapes. Thus, gate oxide films 81 and 91 and gate electrodes 82 and 92 are formed in a formation region of a 3.3 V NMOS transistor corresponding to a 3.3 V power supply and in a formation region of a p-channel type MOS transistor (1.2 V PMOS transistor) corresponding to a 1.2 V power supply of the same Si substrate 70, respectively, as shown in
Thereafter, a resist is formed over the formation region of the 1.2 V PMOS transistor (not shown). Then, into the formation region of the 3.3 V NMOS transistor, phosphorus (P) is ion-implanted using the gate electrode 82 as a mask, and the annealing is performed. Thus, an n-type LDD region 83 is formed as an impurity region.
The ion implantation of P at this time is performed, for example, under the conditions that an acceleration voltage is 15 to 40 keV, a dose is 1×1013 to 5×1013 cm−2 and a tilt angle is 0 degree. Alternatively, the ion implantation of P is performed four times under the conditions that an acceleration voltage is 15 to 40 keV, a dose is 2.5×1012 to 12×1012 cm−2 and a tilt angle is 28 degree. After such ion implantation of P, the resist over the formation region of the 1.2 V PMOS transistor is removed and the annealing is performed at about 900 to 1050° C.
Subsequently, a resist is formed over the formation region of the 3.3 V NMOS transistor (not shown). Then, into the formation region of the 1.2 V PMOS transistor, P or As is ion-implanted using the gate electrode 92 as a mask to form an n-type pocket region 93 as an impurity region. Further, B is ion-implanted to form a p-type extension region 94 as an impurity region.
The ion-implantation of P for forming the pocket region 93 is performed four times, for example, under the conditions that an acceleration voltage is 20 to 40 keV, a dose is 2×1012 to 10×1012 cm−2 and a tilt angle is 28 degree. Further, the ion-implantation of As for forming the pocket region 93 is performed four times, for example, under the conditions that an acceleration voltage is 30 to 60 keV, a dose is 2×1012 to 10×1012 cm−2 and a tilt angle is 28 degree.
Further, the ion implantation of B for forming the extension region 94 is performed under the conditions that, for example, an acceleration voltage is 0.6 keV or less, a dose is 1×1015 cm−2 or less and a tilt angle is 0 degree.
After such ion implantation, the resist over the formation region of the 3.3 V NMOS transistor is removed.
The above-described annealing performed during the formation of the low-concentration LDD region 83 may be performed after the ion implantation for forming the pocket region 93 and the extension region 94 (after removal of the resist) without being performed at that time.
Subsequently, using a low-temperature CVD (Chemical Vapor Deposition) method at about 500 to 600° C., a SiO2 film is deposited over the entire surface and dry-etched. Thus, the sidewalls 84 and 95 having a thickness of, for example, about 5 to 20 nm are formed over the side walls of the gate electrodes 82 and 92, respectively, as shown in
Thereafter, B is ion-implanted using as masks the gate electrodes 82 and 92 and the sidewalls 84 and 95. The ion implantation conditions are set such that, for example, an acceleration voltage is 0.3 to 1 keV, a dose is 5×1014 to 20×1014 cm−2 and a tilt angle is 0 degree. By this ion implantation of B, an extremely shallow p-type counter region 85 as an impurity region is formed in the formation region of the 3.3 V NMOS transistor. Further, a p-type extension region 96 as an impurity region is formed in the formation region of the 1.2 V PMOS transistor.
Subsequently, using a low-temperature CVD method at about 500 to 600° C., a SiO2 film is deposited over the entire surface and dry-etched. Thus, sidewalls 86 and 97 having a thickness of, for example, about 50 to 90 nm are formed outside the sidewalls 84 and 95, respectively, as shown in
Thereafter, n-type impurity ion implantation using as masks the gate electrode 82 and the sidewalls 84 and 86, and p-type impurity ion implantation using as masks the gate electrode 92 and the sidewalls 95 and 97 are respectively performed to form an n-type source/drain region 87 and a p-type source/drain region 98, respectively.
Thereafter, the activation annealing at about 1000 to 1200° C. is performed to form silicide layers (not shown) over the surfaces of the gate electrodes 82 and 92 and the source/drain regions 87 and 98. Thus, fundamental structures of the 3.3 V NMOS transistor and the 1.2 V PMOS transistor are completed. Hereafter, a chip having formed thereon the 3.3 V NMOS transistor and the 1.2 V PMOS transistor may be completed through the formations of interlayer insulating films, contact electrodes and wiring layers.
Thus, in the third embodiment, the counter region 85 is formed under the sidewall 86 of the 3.3 V NMOS transistor. As a result, there can be effectively suppressed characteristic deterioration due to hot carriers, which easily occurs particularly in the n-channel type MOS transistor operating at a high voltage.
Further, in the third embodiment, the ion implantation for forming the extension region 96 in the formation region of the 1.2 V PMOS transistor is performed by the same process as that in the ion implantation for forming the counter region 85 in the formation region of the 3.3 V NMOS transistor, as shown in
In the third embodiment, portions of the 3.3 V NMOS transistor and the 1.2 V PMOS transistor are described. A p-channel portion and n-channel portion of each transistor may be formed in parallel with each other in accordance with the conventional method.
Next, a fourth embodiment will be described.
A MOS transistor 100 shown in
In such a MOS transistor 100, the inner sidewall 104 over the gate electrode 103 and the semiconductor substrate 101 is composed of a SiO2 film formed using the thermal oxidation method or the high-temperature CVD method. Further, the sidewall 105 formed over the sidewall 104 is composed of a SiO2 film formed using the low-temperature CVD method.
When using the thermal oxidation method or the high-temperature CVD method, a dense SiO2 film can be formed. Therefore, when such a SiO2 film is used for a sidewall, hot carriers are hardly accumulated in the sidewall. Accordingly, when forming the sidewall 104 between the LDD region 106 and the low-temperature formed sidewall 105 using the thermal oxidation method or the high-temperature CVD method, even if hot carriers are generated, accumulation of the hot carriers in the sidewall 104 is suppressed. As a result, depletion of the surface part of the LDD region 106 can be suppressed.
Here, the above-described principles will be described in detail by taking as an example a case of applying the principles to a chip having formed thereon the high-voltage transistor and the low-voltage transistor.
Description will be made here by taking as an example a case of forming transistors corresponding to two kinds of voltages such as a high-voltage transistor operating at 3.3 V and a low-voltage transistor operating at 1.2 V in the same chip.
First, an element isolation region (not shown) is formed in a silicon (Si) substrate 110 using an STI method. Then, a SiO2 film having a predetermined thickness is formed in a predetermined region of the surface using the thermal oxidation method, and polysilicon is deposited over the film. Then, the polysilicon and the SiO2 film are processed to have predetermined shapes. Thus, gate oxide films 121 and 131 and gate electrodes 122 and 132 are formed in a formation region of a 3.3 V NMOS transistor corresponding to a 3.3 V power supply and in a formation region of a 1.2 V NMOS transistor corresponding to a 1.2 V power supply of the same Si substrate 110, respectively, as shown in
Thereafter, a SiO2 film 111 having a thickness of about 3 nm is formed over the entire surface using the thermal oxidation method or the high-temperature CVD method (600° C. or more).
Subsequently, as shown in
After removing the resist 112, the following regions are formed as impurity regions. Into the formation region of the 3.3 V NMOS transistor, n-type impurities are ion-implanted and the annealing is performed. Thus, an n-type LDD region 123 is formed as an impurity region as shown in
Subsequently, a SiO2 film 113 is formed over the entire surface using the low-temperature CVD method (about 500° C.) as shown in
Subsequently, a resist (not shown) is formed over the formation region of the 3.3 V NMOS transistor, and the SiO2 film 113 over the formation region of the 1.2 V NMOS transistor is removed by the dry etching to form a sidewall composed of the SiO2 film 113, as shown in
The reason why the formation region of the 3.3 V NMOS transistor is covered with the resist is as follows. That is, when the formation region of the 3.3 V NMOS transistor is etched to expose the Si substrate 110, the low-temperature formed sidewall is disadvantageously brought into contact with the Si substrate 110 in the sidewall formation step performed later again.
Subsequently, using the low-temperature CVD method (about 500° C.), a SiO2 film 114 is formed over the entire surface and dry-etched, as shown in
Thereafter, using as masks these sidewalls and the gate electrodes 122 and 132, n-type impurities are ion-implanted to form n-type source/drain regions 124 and 136, respectively. Thereafter, the activation annealing at about 1000 to 1200° C. is performed to form silicide layers (not shown) over the surfaces of the gate electrodes 122 and 132 and the source/drain regions 124 and 136. Thus, fundamental structures of the 3.3 V NMOS transistor and the 1.2 V NMOS transistor are completed. Hereafter, a chip having formed thereon the 3.3 V NMOS transistor and the 1.2 V NMOS transistor may be completed through the formations of interlayer insulating films, contact electrodes and wiring layers.
Thus, in the fourth embodiment, the SiO2 film 111 is formed using the thermal oxidation method or the high-temperature CVD method to construct the sidewall between the LDD region 123 of the 3.3 V NMOS transistor and the low-temperature formed SiO2 film 113. Therefore, even if hot carriers are generated, accumulation of the hot carriers in the SiO2 film 111 is suppressed. As a result, depletion of the surface part of the LDD region 123 can be effectively suppressed.
In the fourth embodiment, an n-channel portion of the MOS transistor is described. A p-channel portion thereof may be formed in parallel with the formation of the n-channel portion in accordance with the conventional method.
The first to fourth embodiments are described above; however, a combination of the MOS transistors different in operating voltage is not limited to the above-described examples. Specifically, in addition to a combination of the 3.3 V NMOS transistor and the 1.2 V NMOS transistor, and a combination of the 3.3 V NMOS transistor, the 1.8 V NMOS transistor and the 1.2 V NMOS transistor, the present invention can be similarly applied, for example, to a combination of the 1.8 V NMOS transistor and the 1.2 V NMOS transistor, and a combination of the 3.3 V NMOS transistor and the 1.8 V NMOS transistor. Further, the operating voltages cited here are mere examples, and the above-described principles and formation method can be similarly applied to a combination of the high-voltage transistor and the low-voltage transistor, or a combination of the high-voltage transistor, the medium voltage transistor and the low-voltage transistor.
In the present invention, a first impurity region and a second impurity region which is shallower than the first impurity region and apart from a region under the gate electrode are formed under the sidewall. As a result, depletion of the surface part of the impurity region due to hot carriers accumulated in the sidewall can be suppressed, so that the semiconductor device suppressed in characteristic deterioration can be realized.
Particularly, in the case where the first and second impurity regions have the same conductivity type, when the second impurity region is formed apart from a region under the gate electrode, a transverse electric field in channel can be sufficiently relaxed. Further, in the case where the first and second impurity regions have different conductivity types, the surface part of the first impurity region becomes a previously depleted state due to the second impurity region. As a result, depletion due to hot carriers can be suppressed, so that characteristic deterioration can be suppressed.
Further, in the present invention, the high-voltage transistor and the low-voltage transistor are formed over the same semiconductor substrate and the above-described second impurity region is formed on the high-voltage transistor side by ion implantation. At this time, the ion implantation is performed simultaneously with that for forming the impurity region on the low-voltage transistor side. As a result, a semiconductor device having formed thereon the high-voltage transistor and the low-voltage transistor can be efficiently manufactured at low cost.
Further, in the present invention, a first sidewall is formed over the side wall of the gate electrode and over the impurity region within the semiconductor substrate using a high-temperature formed insulating film, and a second sidewall is formed over the first sidewall using a low-temperature formed insulating film. As a result, accumulation of hot carriers in the first sidewall can be suppressed and depletion of the surface part of the impurity region under the first sidewall can be effectively suppressed, so that a semiconductor device suppressed in characteristic deterioration can be realized.
The foregoing is considered as illustrative only of the principles of the present invention. Further, since numerous modifications and changes will readily occur to those skilled in the art, it is not desired to limit the invention to the exact construction and applications shown and described, and accordingly, all suitable modifications and equivalents may be regarded as falling within the scope of the invention in the appended claims and their equivalents.
Number | Date | Country | Kind |
---|---|---|---|
2006-240973 | Sep 2006 | JP | national |