SEMICONDUCTOR DEVICE AND MANUFACTURING METHODS THEREOF

Abstract

Some implementations described herein provide techniques and apparatuses for forming insulator layers in or on a semiconductor substrate prior to forming epitaxial layers within source/drain regions of a fin field-effect transistor. The epitaxial layers may be formed over the insulator layers to reduce electron tunneling between the source/drain regions of the fin field-effect transistor. In this way, a likelihood of leakage into the semiconductor substrate and/or between the source/drain regions of the fin field-effect transistor is reduced.

Description

Claims

1. A semiconductor device, comprising: a fin structure above a semiconductor substrate;a first epitaxial layer extending into the fin structure;a second epitaxial layer extending into the fin structure adjacent to the first epitaxial layer;a gate structure between the first epitaxial layer and the second epitaxial layer;a first oxide layer between a first bottom surface of the first epitaxial layer and the fin structure; anda second oxide layer between a second bottom surface of the second epitaxial layer and the fin structure.

2. The semiconductor device of claim 1, wherein the semiconductor device corresponds to a static random access memory (SRAM) type of semiconductor device; and wherein at least one of the first oxide layer or the second oxide layer comprises: a thickness in a range from approximately 1 nanometers to approximately 3 nanometers; anda width in a range from approximately 10 nanometer to approximately 30 nanometers.

3. The semiconductor device of claim 1, wherein the semiconductor device corresponds to ring oscillator (RO) type of semiconductor device; and wherein at least one of the first oxide layer or the second oxide layer comprises: a thickness in a range from approximately 1 nanometer to approximately 5 nanometers; anda width in a range from approximately 10 nanometers to approximately 60 nanometers.

4. The semiconductor device of claim 1, wherein the semiconductor device corresponds to an input/output (IO) type of semiconductor device; and wherein at least one of the first oxide layer or the second oxide layer comprises: a thickness in a range from approximately 1 nanometer to approximately 7 nanometers; anda width that is in a range of approximately 20 nanometers to approximately 60 nanometers.

5. A method, comprising: forming a dielectric layer in or on a semiconductor substrate;forming a fin structure in the semiconductor substrate, wherein the fin structure includes a portion of the dielectric layer;forming a recess in the fin structure to the portion of the dielectric layer; andforming an epitaxial region over the portion of the dielectric layer in the recess.

6. The method of claim 5, wherein forming the dielectric layer in or on the semiconductor substrate comprises: forming the dielectric layer to a thickness that is in a range from approximately 5 nanometers to approximately 50 nanometers.

7. The method of claim 5, wherein forming the dielectric layer in or on the semiconductor substrate comprises: forming a layer of silicon dioxide (SiO2) material.

8. The method of claim 5, wherein forming the dielectric layer in or on the semiconductor substrate comprises: forming the dielectric layer below a surface of the semiconductor substrate using an ion-implantation processing operation.

9. The method of claim 5, wherein forming the recess in the fin structure comprises: forming the recess into a portion of the dielectric layer.

10. The method of claim 5, wherein forming the dielectric layer in or on the semiconductor substrate comprises: forming the dielectric layer on a surface of the semiconductor substrate using a thermal-oxidation processing operation.

11. The method of claim 5, further comprising: forming an epitaxial layer on a top surface of the dielectric layer using an epitaxial-growth processing operation prior to forming the fin structure.

12. The method of claim 11, wherein forming the fin structure comprises: forming the fin structure such that the fin structure includes a portion of the epitaxial layer.

13. The method of claim 5, wherein forming the epitaxial region comprises: forming a first epitaxial layer on the dielectric layer and between fin sidewall spacers;forming a second epitaxial layer on the first epitaxial layer and above the fin sidewall spacers; andforming a third epitaxial layer on the second epitaxial layer.

14. The method of claim 13, wherein forming the second epitaxial layer comprises: forming a merged-epitaxial sub-region that joins the epitaxial region and another epitaxial region on another fin structure.

15. The method of claim 13, further comprising: forming a contact layer over the third epitaxial layer.

16. A semiconductor device, comprising: a first fin structure above a semiconductor substrate;a second fin structure above the semiconductor substrate and adjacent to the first fin structure;a first epitaxial layer extending into the first fin structure;a second epitaxial layer extending into the second fin structure;a first insulator layer between the first fin structure and a bottom portion of the first epitaxial layer; anda second insulator layer between the second fin structure and a bottom portion of the second epitaxial layer.

17. The semiconductor device of claim 16, wherein at least one of the first insulator layer or the second insulator layer comprises: a top surface at a depth that is in a range from approximately 5 nanometers to approximately 30 nanometers below a top surface of a shallow trench isolation region between the first fin structure and the second fin structure.

18. The semiconductor device of claim 16, wherein the first insulator layer comprises: a first material; andwherein the second insulator layer comprises: a second material that is different than the first material.

19. The semiconductor device of claim 16, wherein the first insulator layer comprises: a first thickness; andwherein the second insulator layer comprises: a second thickness that is different than the first thickness.

20. The semiconductor device of claim 16, wherein at least one of the first epitaxial layer or the second epitaxial layer comprises: a silicon material comprising an arsenic dopant (SiAs); ora silicon-germanium material comprising a boron dopant (SiGeB).