Semiconductor device and method for fabricating the same

Abstract

A high dielectric constant gate insulating film is formed on an active region of a substrate, and a gate electrode is formed on the high dielectric constant gate insulating film. A high dielectric constant insulating sidewall is formed on a side face of the gate electrode.

Description

BRIEF DESCRIPTION of THE DRAWINGS

FIG. 1 is a cross-sectional view for showing the structure of a semiconductor device according to Embodiment 1 of the invention;

FIGS. 2A and 2B are cross-sectional views for showing the structures of an insulating sidewall used in the semiconductor device of Embodiment 1;

FIG. 3 is a cross-sectional view for showing the structure of a semiconductor device according to Modification 1 of Embodiment 1 of the invention;

FIG. 4 is a cross-sectional view for showing the structure of a semiconductor device according to Modification 2 of Embodiment 1 of the invention;

FIG. 5 is a cross-sectional view for showing the structure of a semiconductor device according to Modification 3 of Embodiment 1 of the invention;

FIG. 6 is a cross-sectional view for showing the structure of a semiconductor device according to Embodiment 2 of the invention;

FIGS. 7A and 7B are cross-sectional views for showing the structures of an insulating sidewall used in the semiconductor device of Embodiment 2 of the invention;

FIG. 8 is a cross-sectional view for showing the structure of a semiconductor device according to Modification 1 of Embodiment 2 of the invention;

FIG. 9 is a cross-sectional view for showing the structure of a semiconductor device according to Modification 2 of Embodiment 2 of the invention;

FIG. 10 is a cross-sectional view for showing the structure of a semiconductor device according to Modification 3 of Embodiment 2 of the invention;

FIG. 11 is a cross-sectional view for showing the structure of a semiconductor device according to Embodiment 3 of the invention;

FIG. 12 is a cross-sectional view for showing the structure of a semiconductor device according to a modification of Embodiment 3 of the invention;

FIG. 13 is a cross-sectional view for showing the structure of a semiconductor device according to another modification of Embodiment 3 of the invention;

FIG. 14 is a cross-sectional view for showing the structure of a semiconductor device according to another modification of Embodiment 3 of the invention;

FIG. 15 is a cross-sectional view for showing the structure of a semiconductor device according to another modification of Embodiment 3 of the invention;

FIG. 16 is a cross-sectional view for showing the structure of a semiconductor device according to Embodiment 4 of the invention;

FIG. 17 is a cross-sectional view for showing the structure of a semiconductor device according to a modification of Embodiment 4 of the invention;

FIG. 18 is a cross-sectional view for showing the structure of a semiconductor device according to another modification of Embodiment 4 of the invention;

FIG. 19 is a cross-sectional view for showing the structure of a semiconductor device according to another modification of Embodiment 4 of the invention;

FIGS. 20A, 20B, 20C, 20D, 20E and 20F are cross-sectional views for showing procedures in a method for fabricating a semiconductor device according to Embodiment 5 of the invention;

FIGS. 21A, 21B, 21C, 21D, 21E, 21F and 21G are cross-sectional views for showing procedures in a method for fabricating a semiconductor device according to Embodiment 6 of the invention;

FIGS. 22A, 22B, 22C, 22D, 22E, 22F and 22G are cross-sectional views for showing procedures in a method for fabricating a semiconductor device according to Embodiment 7 of the invention;

FIGS. 23A, 23B, 23C, 23D, 23E, 23F and 23G are cross-sectional views for showing procedures in a method for fabricating a semiconductor device according to Embodiment 8 of the invention;

FIGS. 24A, 24B, 24C and 24D are cross-sectional views for showing other procedures in the method for fabricating a semiconductor device according to Embodiment 8 of the invention;

FIG. 25 is a cross-sectional view for showing a notch provided in the semiconductor device of Modification 2 of Embodiment 1 shown in FIG. 3;

FIG. 26 is a cross-sectional view for showing a notch provided in the semiconductor device of Modification 2 of Embodiment 2 shown in FIG. 9;

FIG. 27 is a cross-sectional view for showing a notch provided in the semiconductor device of the modification of Embodiment 3 shown in FIG. 14;

FIG. 28 is a cross-sectional view for showing a notch provided in the semiconductor device of Modification 2 of Embodiment 1 shown in FIG. 3;

FIG. 29 is a cross-sectional view for showing a notch provided in the semiconductor device of Modification 2 of Embodiment 2 shown in FIG. 9;

FIG. 30 is a cross-sectional view for showing a notch provided in the semiconductor device of the modification of Embodiment 3 shown in FIG. 14; and

FIGS. 31A and 31B are cross-sectional views for showing the structures of conventional MISFETs.

Claims

1. A semiconductor device comprising: a high dielectric constant gate insulating film formed on an active region of a substrate;a gate electrode formed on said high dielectric constant gate insulating film; anda high dielectric constant insulating sidewall formed on a side face of said gate electrode.

2. The semiconductor device of claim 1, wherein said high dielectric constant gate insulating film continuously extends from under said gate electrode to under said high dielectric constant insulating sidewall.

3. The semiconductor device of claim 2, wherein said high dielectric constant gate insulating film has a smaller thickness below said high dielectric constant insulating sidewall than below said gate electrode.

4. The semiconductor device of claim 1, wherein said high dielectric constant insulating sidewall has a lower dielectric constant than said high dielectric constant gate insulating film.

5. The semiconductor device of claim 4, wherein said high dielectric constant insulating sidewall is formed to have the lower dielectric constant than said high dielectric constant gate insulating film by using the same material as that used for said high dielectric constant gate insulating film with its composition ratios changed.

6. A semiconductor device comprising: a high dielectric constant gate insulating film formed on an active region of a substrate;a gate electrode formed on said high dielectric constant gate insulating film;a first insulating sidewall formed on a side face of said gate electrode and having a high dielectric constant; anda second insulating sidewall formed above the side face of said gate electrode with said first insulating sidewall sandwiched therebetween.

7. The semiconductor device of claim 6, wherein said high dielectric constant gate insulating film continuously extends from under said gate electrode to under said first insulating sidewall.

8. The semiconductor device of claim 7, wherein said high dielectric constant gate insulating film has a smaller thickness below said first insulating sidewall than below said gate electrode.

9. The semiconductor device of claim 6, wherein said high dielectric constant gate insulating film continuously extends from under said gate electrode to under said second insulating sidewall.

10. The semiconductor device of claim 9, wherein said high dielectric constant gate insulating film has an equivalent thickness below said first insulating sidewall and below said gate electrode, andsaid high dielectric constant gate insulating film has a smaller thickness below said second insulating sidewall than below said gate electrode.

11. The semiconductor device of claim 9, wherein said high dielectric constant gate insulating film has a smaller thickness below said first insulating sidewall than below said gate electrode, andsaid high dielectric constant gate insulating film has an equivalent thickness below said second insulating sidewall and below said first insulating sidewall.

12. The semiconductor device of claim 9, wherein said high dielectric constant gate insulating film has a smaller thickness below said first insulating sidewall than below said gate electrode, andsaid high dielectric constant gate insulating film has a smaller thickness below said second insulating sidewall than below said first insulating sidewall.

13. The semiconductor device of claim 6, wherein said first insulating sidewall has a lower dielectric constant than said high dielectric constant gate insulating film.

14. The semiconductor device of claim 13, wherein said first insulating sidewall is formed to have the lower dielectric constant than said high dielectric constant gate insulating film by using the same material as that used for said high dielectric constant gate insulating film with its composition ratios changed.

15. The semiconductor device of claim 1, wherein a notch is provided in a side end portion of said high dielectric constant gate insulating film.

16. The semiconductor device of claim 1, wherein a buffer insulating film is provided between said substrate and said high dielectric constant gate insulating film.

17. The semiconductor device of claim 16, wherein said buffer insulating film is made of a silicon oxide film or a silicon oxide nitride film.

18. The semiconductor device of claim 1, wherein said gate electrode is a full silicide gate electrode or a metal gate electrode.

19. A method for fabricating a semiconductor device comprising the steps of: (a) forming a high dielectric constant gate insulating film on an active region of a substrate;(b) forming a gate electrode on said high dielectric constant gate insulating film; and(c) forming a high dielectric constant insulating sidewall on a side face of said gate electrode.

20. The method for fabricating a semiconductor device of claim 19, further comprising, between the step (b) and the step (c), a step of thinning a portion of said high dielectric constant gate insulating film disposed outside said gate electrode.

21. The method for fabricating a semiconductor device of claim 19, further comprising, after the step (c), a step of removing a portion of said high dielectric constant gate insulating film disposed away from said gate electrode beyond said high dielectric constant insulating sidewall.

22. The method for fabricating a semiconductor device of claim 19, wherein said high dielectric constant insulating sidewall has a lower dielectric constant than said high dielectric constant gate insulating film.

23. The method for fabricating a semiconductor device of claim 22, wherein the step (c) includes a sub-step of forming said high dielectric constant insulating sidewall to have the lower dielectric constant than said high dielectric constant gate insulating film by using the same material as that used for said high dielectric constant gate insulating film with its composition ratios changed.

24. A method for fabricating a semiconductor device comprising the steps of: (a) forming a high dielectric constant gate insulating film on an active region of a substrate;(b) forming a gate electrode on said high dielectric constant gate insulating film;(c) forming a first insulating sidewall having a high dielectric constant on a side face of said gate electrode; and(d) forming a second insulating sidewall above the side face of said gate electrode with said first insulating sidewall sandwiched therebetween.

25. The method for fabricating a semiconductor device of claim 24, further comprising, between the step (b) and the step (c), a step of thinning a portion of said high dielectric constant gate insulating film disposed outside said gate electrode.

26. The method for fabricating a semiconductor device of claim 24, further comprising, between the step (c) and the step (d), a step of removing a portion of said high dielectric constant gate insulating film disposed away from said gate electrode beyond said first insulating sidewall.

27. The method for fabricating a semiconductor device of claim 24, further comprising steps of: thinning a portion of said high dielectric constant gate insulating film disposed away from said gate electrode beyond said first insulating sidewall between the step (c) and the step (d); andremoving a portion of said high dielectric constant gate insulating film disposed away from said gate electrode beyond said second insulating sidewall after the step (d).

28. The method for fabricating a semiconductor device of claim 24, wherein the step (b) includes a sub-step of forming a protection film for covering a top face of said gate electrode, andthe method further comprises, after the step (d), a step of siliciding a surface portion of said active region disposed away from said gate electrode beyond said second insulating sidewall, removing said protection film and full siliciding said gate electrode.

29. The method for fabricating a semiconductor device of claim 24, wherein said first insulating sidewall has a lower dielectric constant than said high dielectric constant gate insulating film.

30. The method for fabricating a semiconductor device of claim 29, wherein the step (c) includes a sub-step of forming said first insulating sidewall to have the lower dielectric constant than said high dielectric constant gate insulating film by using the same material as that used for said high dielectric constant gate insulating film with its composition ratios changed.

31. The method for fabricating a semiconductor device of claim 21, wherein said high dielectric constant gate insulating film is selectively removed by wet etching.

32. The method for fabricating a semiconductor device of claim 19, further comprising, before the step (a), a step of forming a buffer insulating film on said active region, wherein said high dielectric constant gate insulating film is formed above said active region with said buffer insulating film sandwiched therebetween in the step (a).