TECHNICAL FIELD
The present application generally relates to semiconductor devices, and more particularly, to a semiconductor device and a method for making the same.
BACKGROUND OF THE INVENTION
The semiconductor industry is constantly faced with complex integration challenges as consumers want their electronic devices to be smaller, faster and have higher performances. In cutting edge 5G devices such as portable multimedia devices, it is common to integrate both a processing system and antenna(s) into one package. In such configuration, multiple electronic components may be integrated in a smaller package, meeting the consumers' needs to encompass more functional modules in a smaller device. However, such high-level integration requires higher interface pin-counts and less thickness, and thus generates more heat and has a less effective heat dissipation. In such cases, the heat accumulated within the package may cause package warpage issue and harm the function of the system.
Therefore, a need exists for a semiconductor package with improved heat management.
SUMMARY OF THE INVENTION
An objective of the present application is to provide an apparatus for heat management of a semiconductor device.
According to an aspect of embodiments of the present application, a semiconductor device is provided. The semiconductor device comprises: a substrate; at least one electronic component mounted on the substrate; an encapsulant formed on the substrate and at least partially encapsulating the at least one electronic component; a shielding layer formed on the encapsulant; a thermal interface layer formed on the shielding layer; and a metal lid formed on the thermal interface layer.
According to an aspect of embodiments of the present application, a semiconductor device is provided. The semiconductor device comprises: a substrate; at least one electronic component mounted on the substrate; an encapsulant formed on the substrate and at least partially encapsulating the at least one electronic component; a thermal interface layer formed on the encapsulant; a metal lid formed on the thermal interface layer; and a shielding layer formed on the substrate and covering the metal lid, the thermal interface layer and the encapsulant.
According to another aspect of embodiments of the present application, methods for making the semiconductor devices according to the above aspects are provided.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only, and are not restrictive of the invention. Further, the accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description, serve to explain principles of the invention.
BRIEF DESCRIPTION OF THE DRAWINGS
The drawings referenced herein form a part of the specification. Features shown in the drawing illustrate only some embodiments of the application, and not of all embodiments of the application, unless the detailed description explicitly indicates otherwise, and readers of the specification should not make implications to the contrary.
FIG. 1A is a cross-sectional view illustrating a semiconductor device according to an embodiment of the present application.
FIGS. 1B and 1C are enlarged views illustrating a portion of the semiconductor device of FIG. 1A according to some embodiments of the present application.
FIG. 1D is a cross-sectional view illustrating a semiconductor device with discrete antenna packages according to an embodiment of the present application.
FIG. 2A is a cross-sectional view illustrating a semiconductor device with top surfaces of two electronic components being exposed to a shielding layer according to another embodiment of the present application.
FIGS. 2B and 2C are enlarged views illustrating a portion of the semiconductor device of FIG. 2A according to some embodiments of the present application.
FIGS. 3A, 3B and 4 are cross-sectional views illustrating a semiconductor device with encapsulated semiconductor package mounted on a substrate according to some embodiments of the present application.
FIG. 5A is a cross-sectional view illustrating a semiconductor device according to another embodiment of the present application.
FIGS. 5B and 5C are enlarged views illustrating a portion of the semiconductor device of FIG. 5A according to some embodiments of the present application.
FIG. 6A is a cross-sectional view illustrating a semiconductor device according to another embodiment of the present application.
FIGS. 6B and 6C are enlarged views illustrating a portion of the semiconductor device of FIG. 6A according to some embodiments of the present application.
FIGS. 7 and 8 are cross-sectional views illustrating a semiconductor device with encapsulated semiconductor package mounted on a substrate according to some embodiments of the present application.
FIG. 9A is a flowchart illustrating a method 900 for making a semiconductor device according to an embodiment of the present application.
FIGS. 9B-9F are cross-sectional views illustrating various steps of the method for making a semiconductor device shown in FIG. 9A.
FIG. 10A is a flowchart illustrating a method 1000 for making a semiconductor device according to another embodiment of the present application.
FIGS. 10B-10F are cross-sectional views illustrating various steps of the method for making a semiconductor device shown in FIG. 10A.
The same reference numbers will be used throughout the drawings to refer to the same or like parts.
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
The following detailed description of exemplary embodiments of the application refers to the accompanying drawings that form a part of the description. The drawings illustrate specific exemplary embodiments in which the application may be practiced. The detailed description, including the drawings, describes these embodiments in sufficient detail to enable those skilled in the art to practice the application. Those skilled in the art may further utilize other embodiments of the application, and make logical, mechanical, and other changes without departing from the spirit or scope of the application. Readers of the following detailed description should, therefore, not interpret the description in a limiting sense, and only the appended claims define the scope of the embodiment of the application.
In this application, the use of the singular includes the plural unless specifically stated otherwise. In this application, the use of “or” means “and/or” unless stated otherwise. Furthermore, the use of the term “including” as well as other forms such as “includes” and “included” is not limiting. In addition, terms such as “element” or “component” encompass both elements and components including one unit, and elements and components that include more than one subunit, unless specifically stated otherwise. Additionally, the section headings used herein are for organizational purposes only, and are not to be construed as limiting the subject matter described.
As used herein, spatially relative terms, such as “beneath”, “below”, “above”, “over”, “on”, “upper”, “lower”, “left”, “right”, “vertical”, “horizontal”, “side” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly. It should be understood that when an element is referred to as being “connected to” or “coupled to” another element, it may be directly connected to or coupled to the other element, or intervening elements may be present.
FIG. 1A shows a semiconductor device 100 with multiple electronic components mounted on a substrate 110 of the semiconductor device 100, according to an embodiment of the present application. As shown in FIG. 1A, some of the electronic components are encapsulated, and further covered by a shielding layer, a thermal interface layer and a metal lid which together provide heat management for the semiconductor device 100, especially the electronic components encapsulated therein.
Specifically, a plurality of electronic components 120, 130, 140 and 150 are mounted on both sides of the substrate 110, and the electronic components are electrically connected to the conductive structures (not shown) within the substrate 110. In one embodiment, the substrate 110 includes one or more embedded antenna members (not shown). The electronic components mounted on the substrate 110 may be semiconductor dice 120, discrete devices 130 and 140, and dielectric members 150. The dielectric members 150 may improve transmission and reception of corresponding embedded antenna members, respectively. In some embodiments, the discrete device 140 is a board-to-board connector, which may be electrically connected to an electronic component or the substrate 110 of the semiconductor device 100, and may be configured to electrically connect to other devices. Preferably, the board-to-board connector electrically connects the embedded antenna members to other devices. Some of the electronic components such as the semiconductor dice 120 and the discrete device 130 may require encapsulation and EMI shielding, while some other electronic components such as the discrete devices 140 and the dielectric members 150 may not require the same protections. The present application achieves an improved heat management by further stacking a multi-layer structure with the encapsulation and the shielding layer, which is further elaborated below.
Further referring to the semiconductor device 100 shown in FIG. 1A, in a preferred embodiment, the semiconductor dice 120, the discrete devices 130, 140 may be mounted on one side of the substrate 110, and the dielectric members 150 may be mounted on the other side of the substrate 110. As aforementioned, due to different practical needs in production and usage, the semiconductor dice 120 and discrete device 130, and the discrete devices 140 and dielectric members 150 may not require the same encapsulation and EMI shielding. An encapsulant 160 is therefore disposed on a part of the electronic components mounted on the substrate 110, i.e., the encapsulant 160 covers the semiconductor dice 120 and the discrete device 130. In contrast, the other electronic components, i.e., the discrete devices 140 and the dielectric members 150, remain not encapsulated and not shielded. The encapsulant 160 covering the part of the electronic components may form an encapsulant cuboid on the substrate 110. A shielding layer 170 is formed to cover at least part of the outer surface of the encapsulant cuboid. Preferably, the shielding layer 170 covers all the outer surface of the encapsulant cuboid. As such, the shielding layer 170 includes a top section covering a top surface of the encapsulant cuboid, and a lateral section covering lateral surfaces of the encapsulant cuboid, thereby the shielding layer 170 has a shape that conforms to the shape of the encapsulant 160.
A thermal interface layer 180 is further formed on the shielding layer 170. Preferably, the thermal interface layer 180 may fully cover the top section of the shielding layer 170, but may not cover the lateral section of the shielding layer 170. That is, the thermal interface layer 180 conforms to the top section of the shielding layer 170. A metal lid 190 is further disposed on the thermal interface layer 180. Preferably, the metal lid 190 may fully cover a top surface of the thermal interface layer 180. That is, the metal lid 190 conforms to the top surface of the thermal interface layer 180.
As illustrated above, in the semiconductor device 100 shown in FIG. 1A, the electronic components 120 and 130 are covered by a stack-up structure of the encapsulant 160, the shielding layer 170, the thermal interface layer 180 and the metal lid 190 in bottom-to-top order. Of note, heights of layers of the stack-up structure depicted in FIG. 1A are only illustrative, not representing the actual proportion of heights of layers in the stack-up structure. The shielding layer 170 may be formed by depositing a shielding material such as metals, conducting plastics and conducting polymers. The thermal interface layer 180 may be formed on the shielding layer 170 by dispensing a thermal interface material onto the shielding layer 170. The thermal interface layer 180 is used for enhancing thermal coupling between a heat-producing device and a heat dissipating device. Specifically speaking, at each contact interface, a thermal boundary resistance exists to impede heat dissipation, and electronic performance and device lifetime can degrade dramatically under continuous overheating and large thermal stress at the contact interfaces. The thermal interface layer 180 may reduce the thermal boundary resistance between layers, enhance thermal management performance, as well as tackle application requirements such as low thermal stress between materials of different thermal expansion coefficients, low elastic modulus or viscosity, flexibility, and reusability. The thermal interface layer 180 transfers heat away from the electronic components under the thermal interface layer 180 through the encapsulant 160 and the shielding layer 170 to the heat-spreading metal lid 190. In some embodiments, the thermal interface material can be thermally conductive, dispensable materials, preferably thermal greases, thermal adhesives, thermal gap fillers, liquid metal, and solder paste. In an embodiment, the thermal interface material is an epoxy compound, which may be used for easy bonding to metals, ceramics, most plastics and a wide variety of other materials. In another embodiment, the thermal interface material includes solder paste which has improved thermal conductivity over typical thermal interface material. Preferably, the solder paste is Ag—In solder alloy. Specifically, the thermal interface material may be a solder preform, that is, a solid, flat, manufactured-shape of solder, and a flux may be applied to coat the solder preform. The metal lid 190 is usually made of high thermal conductive metallic materials for efficient heat dissipation from devices in a semiconductor package. In the present application, the metal lid 190 may function in combination with the thermal interface layer 180 to provide better heat dissipation for electronic components inside the corresponding encapsulant. The metal lid 190 is preferably made of copper, aluminum, and copper-tungsten alloy. It can be appreciated that other suitable materials can be used to form the metal lid 190. With the thermal interface layer 180 and the metal lid 190 conducting heat away from the electronic components, power consumption may be reduced by maintaining the electronic components at a lower operating temperature.
The shielding layer 170 in FIG. 1A may further include sublayers, which are exemplarily illustrated by enlarging a portion 101 of the semiconductor device 100 in FIG. 1B and FIG. 1C. Portions 101b, 101c shown in FIGS. 1B and 1C are cross-sectional views of stack-up structures on encapsulants 160b, 160c covering electronic components, respectively. Of note, heights of layers of the stack-up structures depicted in FIG. 1B and FIG. 1C are only illustrative, not representing the actual proportion of heights of layers in the stack-up structures.
Referring to FIG. 1B, the enlarged portion 101b shows that a shielding layer 170b may include three sublayers according to a preferred embodiment. Specifically speaking, the shielding layer 170b may include a wetting sublayer 171b, a shielding sublayer 172b, and a protection sublayer 173b from bottom to top. That is, the wetting sublayer 171b is formed on the encapsulant 160b. The shielding sublayer 172b on the wetting sublayer 171b may be formed by sputtering, plasma deposition or spraying, so as to prevent exterior interference such as electromagnetic interference. Preferably, the shielding sublayer 172b is formed by sputtering. The protection sublayer 173b may be formed on the shielding sublayer 172b, which preferably includes stainless steel, organic solderability preservative or nickel, so as to provide better resistance such as oxidation resistance, thermal shock resistance, moisture resistance, and corrosion resistance. Then a thermal interface layer 180b is disposed on the protection sublayer 173b, and a metal lid 190b is further disposed on the thermal interface layer 180b. In some embodiments, a thickness of the wetting sublayer 171b is less than or equal to 1 μm. In some embodiments, a thickness of the shielding sublayer 172b ranges from 2 μm to 10 μm, for example, 2 μm, 3 μm, 4 μm, 5 μm, 6 μm, 7 μm, 8 μm, 9 μm, 10 μm. In some embodiments, a thickness of the protection sublayer 173b is less than or equal to 1 μm. However, the respective thicknesses of the above-mentioned sublayers 171b, 172b and 173b are not to be limited to these examples. In accordance with the scope of the present application, the thicknesses of the sublayers 171b, 172b and 173b may include any thickness, which can effectively perform wetting, shielding and protecting, respectively.
In another embodiment, i.e., the portion 101c shown in FIG. 1C, the shielding layer 170c may include only two sublayers, which are a wetting sublayer 171c on the encapsulant 160c, and a shielding sublayer 172c on the wetting sublayer 171c, respectively. A thermal interface layer 180c is disposed on the shielding sublayer 172c, and a metal lid 190c is further disposed on the thermal interface layer 180c. The wetting sublayers 171b, 171c are generally used for providing better wettability for layers that are in contact with themselves. Specifically speaking, the wetting sublayer 171b, 171c may enable the shielding sublayers 172b, 172c to adhere more completely and uniformly to the encapsulants 160b, 160c, respectively. The wetting sublayers 171b, 171c are preferably made of a material including at least one of gold, silver, indium, and tin. Preferably, the wetting sublayers 171b, 171c includes titanium or stainless steel. The shielding sublayer is used for blocking exterior interference such as electromagnetic interference from environment or other electronic devices. Preferably, the shielding sublayers 172b, 172c includes copper. Aspects of the present application are not limited thereto, it can be appreciated that other electronic components may be mounted on a substrate, and encapsulant and shielding may be needed on electronic components on both sides of a substrate. Furthermore, a selective shielding and/or selective forming a thermal interface layer and/or configuring a selective metal lid can be appreciated.
FIG. 1D is a cross-sectional view illustrating a semiconductor device with discrete antenna packages according to an embodiment of the present application. As shown in FIG. 1D, in a semiconductor device 100d, electronic components mounted on a side of a substrate 110d opposite to an encapsulant and aforementioned heat management layers may be discrete antenna packages 150d. The discrete antenna packages 150d may be formed within another encapsulant layer 151d. The discrete antenna packages 150d may include therein respective antenna conductive patterns which are electrically connected to certain conductive patterns (not shown) in the substrate 110d, so as to further connected to the other electronic components on the topside of the substrate 110d.
In some embodiments, an encapsulant covering a plurality of electronic components may be constructed to expose a top surface of at least one electronic component of the plurality of electronic components, thereby, a shielding layer on the encapsulant may be in contact with the top surface of the at least one electronic component. FIG. 2A shows a semiconductor device 200 with a thinned encapsulant, according to an embodiment of the present application.
As shown in FIG. 2A, multiple electronic components including two semiconductor dice 220, discrete devices 230, 240, and dielectric members 250 may be mounted on both sides of a substrate 210. It can also be appreciated that the dielectric members 250 may be replaced by discrete antenna packages configuration shown in FIG. 1D. Similar to the embodiment of FIG. 1A, the two semiconductor dice 220 and the discrete device 230 need to be encapsulated, while other electronic components require no encapsulation. However, different from the embodiment of FIG. 1A, an encapsulant 260 constructed for covering the two semiconductor dice 220 and the discrete device 230 may expose top surfaces of the two semiconductor dice 220. At the same time, some electronic components inside the encapsulant 260 may remain unexposed such as the discrete device 230. A shielding layer 270 is formed on the encapsulant 260. Since the top surfaces of the semiconductor dice 220 are exposed, the shielding layer 270 is in contact with the top surfaces of the two semiconductor dice 220. In some preferred embodiments, the shielding layer 270 may cover an outer surface of an encapsulant cuboid formed by the encapsulant 260. A thermal interface layer 280 is disposed on the shielding layer 270 and conforms to a top surface of the shielding layer 270. A metal lid 290 is disposed on the thermal interface layer 280 and conforms to a top surface of the thermal interface layer 280. The materials of the encapsulant 260, the above-mentioned layers and the metal lid 290 are similar to those described with reference to the embodiment illustrated in FIG. 1A. It can be appreciated that some electronic components may be exposed from an encapsulant while others may not, which may be configured differently.
Further referring to FIG. 2A, the shielding layer 270 may further include sublayers, which are exemplarily illustrated by enlarging a portion 201 of the semiconductor device 200 in FIG. 2B and FIG. 2C. Portions 201b, 201c shown in FIGS. 2B and 2C are cross-sectional views of stack-up structures on an encapsulant covering electronic components, respectively. Particularly, a portion where a right semiconductor die 220 in FIG. 2A is in contact with the shielding layer 270 is enlarged.
Referring to FIG. 2B, the enlarged portion 201b shows that a shielding layer 270b may include three sublayers according to a preferred embodiment. Of note, the enlarged portion 210b depicts a portion where a top surface of a semiconductor die 220b is exposed from the encapsulant 260 in FIG. 2A, thereby the semiconductor die 220b is in contact with the shielding layer 270b. Specifically speaking, in the preferred embodiment of FIG. 2B, the shielding layer 270b may include a wetting sublayer 271b, a shielding sublayer 272b, and a protection sublayer 273b from bottom to top. Then a thermal interface layer 280b is disposed on the protection sublayer 273b, and a metal lid 290b is disposed on the thermal interface layer 280b.
In another embodiment, i.e., the portion 201c shown in FIG. 2C, a shielding layer 270c may only include two sublayers, which are a wetting sublayer 271c in contact with a semiconductor die 220c, and a shielding sublayer 272c on the wetting sublayer 271c, respectively. A thermal interface layer 280c is disposed on the shielding sublayer 272c, and a metal lid 290c is disposed on the thermal interface layer 280c. The material configurations of the above-mentioned layers and the metal lid may refer back to the illustrations of FIGS. 1B and 1C.
In some other embodiments, an electronic component mounted on a substrate may be a semiconductor package, which may include one or more semiconductor dice and/or one or more discrete devices. Such embodiments can refer to FIGS. 3A, 3B and 4, which depict the situation that encapsulation, shielding and layers for heat management are constructed on a semiconductor package of multiple electronic components mounted on a substrate.
FIG. 3A shows a semiconductor device 300 according to an embodiment of the present application. Referring to FIG. 3A, in the semiconductor device 300, multiple electronic components may be mounted on a substrate 310. That is, a semiconductor package 320, discrete devices 340, and dielectric members 350 may be mounted on the substrate 310 and electrically connected together via conductive structures in the substrate 310. It can also be appreciated that the dielectric members 350 may be replaced by a discrete antenna packages configuration as shown in FIG. 1D. The semiconductor package 320 may include multiple components such as a substrate 321, two semiconductor dice 322 and discrete devices 323 mounted on one side of the substrate 321, and one semiconductor die 324 on the other side of the substrate 321. Electronic components mounted on the substrate 321 are electrically connected together via the conductive structures in the substrate 321. Of note, part of the semiconductor package 320 may be previously encapsulated in some embodiments. The substrate 321 of the semiconductor package 320 may be electrically connected to the substrate 310 via such as solder balls 325. In this embodiment, the semiconductor package 320 is encapsulated with an encapsulant 360, forming an encapsulant cuboid similar to the embodiment of FIG. 1A. In some embodiments, the semiconductor die 324 disposed between the substrate 321 and the substrate 310 may expose a surface facing the substrate 310 from the encapsulant 360 as illustrated in FIG. 3A. A shielding layer 370 is formed on the encapsulant 360 to cover at least part of the outer surface of the encapsulant 360. Preferably, the shielding layer 370 covers all the outer surface of the encapsulant cuboid. The shielding layer 370 includes a top section covering a top surface of the encapsulant cuboid, and a lateral section covering lateral surfaces of the encapsulant cuboid. A thermal interface layer 380 is further formed on the shielding layer 370. Preferably, the thermal interface layer 380 may fully cover the top section of the shielding layer 370, and may not cover the lateral section of the shielding layer 370. That is, the thermal interface layer 380 conforms to the top section of the shielding layer. A metal lid 390 is further disposed on the thermal interface layer 380. Preferably, the metal lid 390 may fully cover a top surface of the thermal interface layer 380. That is, the metal lid 390 conforms to the top surface of the thermal interface layer 380. It can be appreciated that the shielding layer 370 of the semiconductor device 300 may be the shielding layer 101b or 101c, which includes three or two sublayers, respectively.
Referring to FIG. 3B, a semiconductor device 300b may be configured similarly to FIG. 3A. That is, a semiconductor package 320 may be mounted via solder balls 325 to a substrate 310 of the semiconductor device 300b. In this embodiment, the semiconductor package 320 also includes a substrate 321, two semiconductor dice, and discrete devices 323a, 323b. Different from FIG. 3A, the discrete device 323b of the semiconductor package 320 requires no encapsulation, therefore, an encapsulant 360 is not formed on the discrete device 323b. That is to say, the encapsulant 360 is formed on part of the semiconductor package 320.
FIG. 4 shows a semiconductor device 400 according to an embodiment of the present application. Referring to FIG. 4, the semiconductor device 400 with mounted semiconductor package 420 is shown. Similar to FIG. 2A, the semiconductor package 420 is mounted on a substrate and requires thermal interface layer and metal lid, and an encapsulant 460 may also be constructed to expose a top surface of at least one electronic component of the semiconductor package 420. It can be appreciated that such configuration may be adapted for a semiconductor package configuration as shown in FIG. 3B. In a preferred embodiment, top surfaces of two semiconductor dice 422 are exposed from the encapsulant 460. In this case, a shielding layer 470 formed on the encapsulant 460 is in contact with the top surfaces of the two semiconductor dice 422. Yet other electronic components inside the encapsulant 460 may remain unexposed and not in contact with the shielding layer 470. A thermal interface layer 480 is disposed on the shielding layer 470. A metal lid 490 is disposed on the thermal interface layer 480.
The above embodiments show that the thermal interface layer and the metal lid are disposed on top of the shielding layer. In yet another aspect, a thermal interface layer and a metal lid may be configured underneath a shielding layer, as illustrated in the embodiments shown in FIGS. 5A-8.
FIG. 5A shows a semiconductor device 500 according to an embodiment of the present application. As shown in FIG. 5A, a thermal interface layer 580 is disposed on a top surface of an encapsulant cuboid formed by an encapsulant 560 and electronic components covered by the encapsulant 560. The thermal interface layer 580 conforms to a top surface of the encapsulant cuboid. A metal lid 590 is disposed on the thermal interface 580, which conforms to a top surface of the thermal interface 580. In a preferred embodiment, a shielding layer 570 is disposed on the metal lid 590 to cover a top surface of the metal lid 590, lateral surfaces of the encapsulant cuboid, lateral surfaces of the thermal interface layer 580 and lateral surfaces of the metal lid 590.
The shielding layer 570 in the semiconductor device 500 shown in FIG. 5A may further include sublayers according to two other embodiments, which are illustrated by enlarging a portion 501 of the semiconductor device 500 in FIG. 5B and FIG. 5C. Portions 501b, 501c are cross-sectional views of stack-up structures on encapsulants 560b, 560c covering electronic components.
General laminate structures shown in FIG. 5B and FIG. 5C are both the encapsulants 560b, 560c, thermal interface layers 580b, 580c, metal lids 590b, 590c and shielding layers 570b, 570c from bottom to top, respectively. The difference of the two general laminate structures shown in FIG. 5B and FIG. 5C lies in sublayers of the shielding layers 570b, 570c. Referring to FIG. 5B, an enlarged portion 501b shows that the shielding layer 570b may include three sublayers according to a preferred embodiment. Specifically speaking, the shielding layer 570b may include a wetting sublayer 571b, a shielding sublayer 572b, and a protection sublayer 573b from bottom to top. In another embodiment 501c shown in FIG. 5C, the shielding layer 570c may only include two sublayers, which are a shielding sublayer 572c on the metal lid 590c, and a protection sublayer 573c on the shielding sublayer 572c.
FIG. 6 shows a semiconductor device 600 according to an embodiment of the present application. Similar to the embodiment shown in FIG. 5A, a thermal interface layer 680 and a metal lid 690 are also beneath a shielding layer 670, yet here an encapsulant 660 is configured to expose a top surface of at least one electronic component inside the encapsulant 660, which is similar to the embodiment shown in FIG. 2A. In FIG. 6A, the encapsulant 660 covering a plurality of electronic components may be constructed to expose top surfaces of two semiconductor dice 620, thereby the thermal interface layer 680 is in contact with the two semiconductor dice 620. The metal lid 690 is disposed on the thermal interface layer 680, both of which have a same area as a top surface of an encapsulant cuboid formed by the encapsulant 660. The shielding layer 670 is formed on the metal lid 690. It can be appreciated that similar to FIG. 5A, the shielding layer 670 may cover a top surface of the metal lid 690, lateral surfaces of the metal lid 690, lateral surfaces of the thermal interface layer 680, and the lateral surfaces of the encapsulant cuboid.
Similar to the semiconductor device 500 shown in FIG. 5A, the shielding layer 670 in the semiconductor device 600 may further include sublayers according to two other embodiments, which are illustrated by enlarging a portion 601 of the semiconductor device 600 in FIG. 6B and FIG. 6C. Portions 601b, 601c are cross-sectional views of stack-up structures on an encapsulant 660 covering electronic components. Particularly, a portion where a right semiconductor die 620 in FIG. 6A is in contact with the shielding layer 670, is enlarged.
General laminate structures of the embodiments shown in FIG. 6B and FIG. 6C are both semiconductor dice 620b, 620c, thermal interface layers 680b, 680c, metal lids 690b, 690c, and shielding layers 670b, 670c from bottom to top, respectively. The difference of the two general laminate structures shown in FIG. 6B and FIG. 6C lies in sublayers of the shielding layers 670b, 670c. Referring to FIG. 6B, the enlarged portion 601b shows that the shielding layer 670b may include three sublayers, i.e., a wetting sublayer 671b, a shielding sublayer 672b, and a protection sublayer 673b from bottom to top. The three sublayers of the shielding layer 670b are formed on the metal lid 690b. In another embodiment 601c shown in FIG. 6C, the shielding layer 670c may only include two sublayers, which are a shielding sublayer 672c and a protection sublayer 673c on the shielding sublayer 672c, respectively.
Similar to the embodiments shown in FIGS. 3 and 4, an electronic component mounted on a substrate may be a semiconductor package, which may include one or more semiconductor dice and/or one or more discrete devices. In this situation, a thermal interface layer and a metal lid may also be configured beneath a shielding layer, which can refer to FIGS. 7 and 8.
FIG. 7 shows a semiconductor device 700 according to an embodiment of the present application. Referring to FIG. 7, in the semiconductor device 700, multiple electronic components are mounted on a substrate 710. That is, a semiconductor package 720, discrete devices 740, dielectric members 750 are mounted on the substrate 710 and electrically connected with each other via the substrate 710. It can also be appreciated that the dielectric members 750 may be replaced by a discrete antenna packages configuration as shown in FIG. 1D. The semiconductor package 720 may include multiple components as shown in FIG. 7. In this embodiment, the semiconductor package 720 is encapsulated with an encapsulant 760, forming an encapsulant cuboid. On the periphery of the encapsulant 760, there are a thermal interface layer 780 and a metal lid 790, both of which have a same area as a top surface of the encapsulant cuboid. A shielding layer 770 further covers a top surface of the metal lid 790, lateral surfaces of the metal lid 790, lateral surfaces of the thermal interface layer 780, and lateral surfaces of the encapsulant cuboid. It can be appreciated that the shielding layer 770 may be the same as or similar to the shielding layer 501b or 501c shown in FIGS. 5B and 5C. It can be appreciated that such configuration may be adapted for a semiconductor package configuration as shown in FIG. 3B.
FIG. 8 shows a semiconductor device 800 according to an embodiment of the present application. Referring to FIG. 8, an encapsulant 860 exposing a top surface of at least one electronic component in a semiconductor package 820 mounted on a substrate is shown. Similar to the semiconductor device 600 shown in FIG. 6A, a thermal interface layer 880 is in contact with top surfaces of two semiconductor dice 822, which are exposed from the encapsulant 860. Other electronic components of the semiconductor package 820 remain covered by the encapsulant 860. A metal lid 890 is disposed on the thermal interface layer 880, both of which have a same area as a top surface of an encapsulant cuboid formed by the encapsulant 860. A shielding layer 870 further covers a top surface of the metal lid 890, lateral surfaces of the metal lid 890, lateral surfaces of the thermal interface layer 880, and the lateral surfaces of the encapsulant cuboid. It can be appreciated that the shielding layer 870 of the semiconductor device 800 may be the same as or similar to the shielding layer 601b or 601c shown in FIGS. 6B and 6C. It can be appreciated that such configuration may be adapted for a semiconductor package configuration as shown in FIG. 3B.
In FIGS. 9A-10F, steps for making an aforementioned semiconductor device are illustrated. Note that the sequential order illustrated below represents only some of the embodiments and could be adapted to specific scenarios.
FIG. 9A is a flowchart illustrating a method 900 for making a semiconductor device according to an embodiment of the present application. Herein, a substrate is firstly provided in block 901, then at least one electronic component is mounted thereon in block 902. After that, an encapsulant is formed on the substrate in block 903, at least partially encapsulating the at least one electronic component. A shielding layer is formed in block 904, a thermal interface layer is formed in block 905 and a metal lid is formed in block 906. Of note, as illustrated in the above embodiments, the forming of the shielding layer may be before the forming of the thermal interface layer in block 904 and the forming of the metal lid in block 905, or after these two blocks. Of note, for a case that a semiconductor package including multiple electronic components is mounted on a substrate, part or all of the semiconductor package may be previously encapsulated.
FIGS. 9B to 9E illustrates various steps for making a semiconductor device according to the method shown in FIG. 9A on the provided substrate 910. As shown in FIG. 9B, a substrate 910 is provided, where a plurality of electronic components, such as two semiconductor dice 920, discrete devices 930, 940 and dielectric members 950 are firstly mounted by for example solder paste printing and reflowing. Then in FIG. 9C, an encapsulant 960 is formed, which encapsulates some of the above-mentioned electronic components such as the two semiconductor dice 920 and the discrete device 930 by molding. Next, in FIG. 9D, a shielding layer 970, preferably fully covering the encapsulant 960 and the encapsulated electronic components, is deposited by for example sputtering. Then in FIG. 9E, a thermal interface layer 980 is disposed on the shielding layer 970 by dispensing. Next in FIG. 9F, a metal lid 990 is attached on the thermal interface layer 980.
In method 1000, forming of a shielding layer 1004 may be after forming of a thermal interface layer 1005 and forming of a metal lid 1006 as mentioned before. Of note, for a case that a semiconductor package including multiple electronic components is mounted on a substrate, part of the semiconductor package may be previously encapsulated.
FIGS. 10B to 10F illustrates various steps for making a semiconductor device according to the method shown in FIG. 10A. As shown in FIG. 10B, a substrate 1010 is provided, where a plurality of electronic components, such as two semiconductor dice 1020, discrete devices 1030, 1040 and dielectric members 1050 are firstly mounted by for example solder paste printing and reflowing. Then in FIG. 10C, an encapsulant 1060 is formed, which encapsulates some of the above-mentioned electronic components such as the two semiconductor dice 1020 and the discrete device 1030 by molding. The two aforementioned steps are similar to the case in the method 900. Next, in FIG. 10D, a thermal interface layer 1080, preferably covering a top surface of the encapsulant 1060 and the encapsulated electronic components, is disposed by for example dispensing. Next in FIG. 10E, a metal lid 1090 is attached on the thermal interface layer 1080. Finally, a shielding layer 1070 in FIG. preferably fully covering the thermal interface layer 1080, the metal lid 1090, the encapsulant 1060 and the encapsulated electronic components, is deposited by for example sputtering.
It can be appreciated that the aforementioned steps in FIGS. 9B-9F, FIGS. 10B-10F may be adapted for any one of the aforementioned semiconductor device in FIGS. 1A-8.
It can be seen from the above embodiments that the present application involves a stack-up structure of shielding, thermal interface layer and metal lid. This structure introduces heat management to a semiconductor device without affecting the general structure of a normal semiconductor device. Therefore, the present application provides a semiconductor device with heat management and is widely applicable.
The discussion herein included numerous illustrative figures that showed various portions of a semiconductor device and method of manufacturing thereof. For illustrative clarity, such figures did not show all aspects of each example assembly. Any of the example assemblies and/or methods provided herein may share any or all characteristics with any or all other assemblies and/or methods provided herein.
Various embodiments have been described herein with reference to the accompanying drawings. It will, however, be evident that various modifications and changes may be made thereto, and additional embodiments may be implemented, without departing from the broader scope of the invention as set forth in the claims that follow. Further, other embodiments will be apparent to those skilled in the art from consideration of the specification and practice of one or more embodiments of the invention disclosed herein. It is intended, therefore, that this application and the examples herein be considered as exemplary only, with a true scope and spirit of the invention being indicated by the following listing of exemplary claims.
Patent Application
20230402399
