Patent Application
20090184373
This description refers to embodiments of semiconductor devices and particularly to power semiconductor devices having an integrated gate runner structure with an adjusted gate resistance. Further embodiments refer to a method for manufacturing a semiconductor device.
Power semiconductor devices such as compensation devices, also known as CoolMOS, exhibit a low specific on-state resistance (Ron*A) and can be formed at reduced size with respect to conventional MOSFETs while maintaining the low on-state resistance. The reduced size also results in smaller capacities which allow fast switching with steeper switching slopes.
When using such high speed power semiconductor devices care must be taken to match the semiconductor device with parasitics in the application. For example, in non-optimised applications having relatively large parasitic inductances or capacitances a fast switching device can induce steep changes of the current and voltage which could result in high-frequent oscillations which may adversely affect the EMI-behaviour of the device or might bring the device outside of operational standards.
Many applications try to tailor the gate-drain capacitance, also known as Miller capacitance, to compensate the oscillations. This, however, may cause significant changes to the layout of the device.
According to an embodiment, a semiconductor device is provided which includes a semiconductor substrate and an active cell area having at least one active cell formed in the semiconductor substrate. An edge termination region surrounds at least sections of the active cell area. An integrated gate runner structure is arranged at least partially in the edge termination region and has at least one low electrical resistance portion and at least one high electrical resistance portion. The high electrical resistance portion is electrically connected in series to the low electrical resistance portion.
By providing high and low electrical resistance portions the resistance of the gate runner structure can be adjusted. This changes the effective gate resistance and, therefore, influences the switching behaviour of the semiconductor device. Steep oscillations can be avoided. Furthermore, the effective gate resistance can be varied according to specific needs so that tailored devices can be provided.
A full and enabling disclosure of the present invention, including the best mode thereof, to one of ordinary skill in the art, is set forth more particularly in the remainder of the specification, including reference to the accompanying figures. Therein:
Reference will now be made in detail to various embodiments, one or more examples of which are illustrated in the figures. Each example is provided by way of explanation, and is not meant as a limitation of the invention. For example, features illustrated or described as part of one embodiment can be used on or in conjunction with other embodiments to yield yet a further embodiment. It is intended that the present invention includes such modifications and variations. The examples are described using specific language which should not be construed as limiting the scope of the appending claims. The drawings are not scaled and are for illustrative purposes only.
The term “lateral” as used in this specification intends to describe an orientation parallel to the main surface of a semiconductor wafer or die.
The term “vertical” as used in this specification intends to describe an orientation which is arranged perpendicular to the main surface of the semiconductor wafer or die.
The term “above” as used in this specification describes a location of a structural feature which is arranged closer to the first surface in relation to another structural feature.
Consequently, the term “below” as used in this specification describes a location of a structural feature which is arranged closer to the second surface in relation to another structural feature.
Specific embodiments described in this specification pertain to, without being limited thereto, semiconductor devices such as CMOS devices, power semiconductor devices and particularly to devices which are controlled by field-effect such as field-effect transistors (FETs) and insulated gate bipolar transistors (IGBTs).
With reference to
In certain embodiments, the gate runner structure 2 includes at least two spaced-apart low electrical resistance portions 6 and at least one high electrical resistance portion 8 which electrically connects the two spaced-apart low electrical resistance portions 6 with each other. The resistance portions 6, 8 are therefore connected with each other in series.
The resistor structure integrated in the gate runner structure 2 can be scaled with the device and does not assume further space in comparison to resistors arranged separate to the gate runner structure 2. Furthermore, integrating a resistor structure into the gate runner structure 2 avoids additional parasitic effects such as parasitic capacitances and inductances of a bond pad and the corresponding bond wire or of additional electrical connections required. The resistor structure is formed by the at least one high electrical resistance portion, the length of which can be varied to obtain different resistance values.
The gate runner structure 2, hereinafter referred to as gate runner 2, can have a ring-like shape with a rectangular or hexagonal layout or any other layout depending on the actual layout of the semiconductor device. The gate runner 2 can be formed like a closed ring or a ring having an open side or can have a U-shaped layout. Furthermore, a stripe layout is also possible.
In this description, the gate runner 2 and the gate electrodes of the active cells form together with the gate pad structure and the electrical connections between the gate electrodes and the runner 2 a gate structure, which may also include optional gate fingers. The gate structure has an effective gate resistance which is determined by all components and, particularly, by the gate runner 2. The effective gate resistance influences the switching behaviour of the active cells.
Gate runners are used particularly for large area semiconductor devices having a plurality of active cells to connect electrically the gate electrodes of all cells with a common gate pad structure. In some embodiments, it is desired that the electrical connection to each cell has the same resistance so that the cells can be uniformly activated. Otherwise, for example, when the effective gate resistance of cells close to the gate pad were smaller than for cells remote to the gate pad, the cells close to the gate pad would switch faster and would therefore bear the total current. This non-uniform behaviour is sometimes referred to as current splitting or formation of current filaments. Formation of current filaments stresses the active cells and can render the device inoperable.
The gate runner 2, as described herein, can be used to provide a uniform electrical connection to all gate electrodes so that each gate electrode “sees” substantially the same effective gate resistance. The cells are therefore uniformly switched and the risk of having a current splitting is reduced.
As shown in
By combining high and low electrical resistance portions 6, 8 to form a gate runner 2 the electrical resistance of the gate runner 2 can be adjusted according to specific needs. Particularly, the resistance of the gate runner 2 can be selected to reduce oscillations of fast switching devices by increasing the effective gate resistance. Increasing the effective gate resistance reduces the switching speed of the device since the gates of the respective cells can only be charged or discharged at reduced speed. Increasing the effective gate resistance might increase switching losses which are, however, tolerable to a certain degree if, on the other hand, the risk, that the device is subjected to adverse oscillations, can be reduced. As it becomes more apparent from the description below, the effective gate resistance can be selected in a wide range which allows adjustment of the device behaviour to specific applications.
The effective gate resistance can be determined by an impedance measurement between source and drain of the semiconductor device. Alternatively, the effective gate resistance can be determined from a comparison between the switching behaviour of a reference device having a gate runner made of a low resistance material only and the switching behaviour of a device having a gate runner of low and high electrical resistance portions as described herein. An external resistor is connected to the gate runner of the reference device and varied until the switching behaviour of both devices is substantially identical. The effective gate resistance then corresponds to the value of the external resistor.
In the embodiment shown in
A first insulating layer 23, for example an oxide layer, is arranged on the first surface 21 of the semiconductor substrate 1. Thereon, high electrical resistance portions 8 are formed in a first level. The high electrical resistance portions 8 are covered by a second insulating layer 24, for example an oxide layer, on which the low electrical resistance portions 6 are arranged in a second level. First and second levels are spaced from each other in a vertical direction. With reference to the semiconductor substrate 1, the high electrical resistance portions 8 are arranged below the low electrical resistance portions 6 or between the substrate 1 and the low electrical resistance portions 6. It would also be possible to interchange the vertical arrangement of the low and high electrical resistance portions 6, 8.
The low electrical resistance portions 6 can be arranged in a staggered manner with respect to the high electrical resistance portions 8 as shown in
As further shown in
For example, the low electrical resistance portions 6 can be made of a metal-containing material such as a metal or a metal-alloy. In many applications, aluminium or an aluminium-alloy can be used which have a sufficiently low electrical resistance. On the other hand, the high electrical resistance portions 8 can be made of an appropriately doped polysilicon. The vias 28 typically are also made of a metal such as aluminium.
A skilled person will appreciate that the resistance of the low and high electrical resistance portions 6, 8 is determined by the specific electrical resistance and the cross-sectional area of the respective material used. Due to size limitations the width of the respective electrical resistance portions can not be significantly increased in many applications. Under certain circumstances, it might be possible to increase their thickness which, however, would increase topological differences between for example the edge termination region 12 and the active cell area 11. By selecting the doping concentration of polysilicon, a certain variation of the resistance is also possible.
To illustrate an application, a semiconductor device with a total area of about 30 mm2 is assumed. In this case, the gate runner 2 having a ring-like structure as shown in
Depending on the device size, the effective gate resistance can be maintained by varying the relative contribution of the respective resistance portions to the gate runner 2. For example, to maintain the effective resistance at a designated value when manufacturing a large device, the total length of the low electrical resistance portions 6 can be increased with respect to the total length of the high electrical resistance portions 8 to take account of the increased size of the gate runner 2. On the other hand, for small devices the high electrical resistance portions 8 may dominate the gate runner 2 to keep the resistance at the designated value.
It would also be possible to form a single continuous high electrical resistance portion 8 and to add selectively low electrical resistance portions 6 to reduce the total resistance of the high electrical resistance portion 8. In this case, the high electrical resistance portion is not structured but formed as a single continuous opened or closed ring. Such an embodiment is illustrated in
In some embodiments, a further ring structure (not shown) can surround the gate runner 2 and functions as a source runner, i.e. provides an electrical connection for the source regions of the active cells.
A further embodiment of a gate runner 2 is shown in
When considering the electrical path between the gate pad structure 10 and each active cell, the electrical path to the most remote active cell 31a is longer than for an active cell such as cell 31 arranged closer to the gate pad structure 10. This means that the effective gate resistance of the most remote active cell 31a would be larger than that for cell 31. In order to at least partially compensate the different electrical path and hence the increased resistance thereof, low electrical resistance portions 6c with increasing length are arranged in the electrical path towards the most remote cell 31a to lessen the increase of the resistance. Alternatively or additionally, the length of the high electrical resistance portions 8 can be reduced.
A further embodiment is illustrated in
Different thereto, the embodiment shown in
The conductive region 48 can be doped polysilicon, which is insulated from the semiconductor substrate 1 by a groove insulating layer 34.
Trench 46 and groove 44 can be concomitantly or separately formed. Furthermore, the groove insulating layer 34 and the gate dielectric layer 36 can also be formed together or in separate steps. Typically, the gate electrode 38 and the conductive region arranged in groove 44 are formed together. In this embodiment, groove 44 and trench 46 have different depths but can also be formed to have substantially the same depth.
In the embodiment shown in
A plan view on a further embodiment is shown in
As shown in the embodiments, the arrangement of the gate runner 2 is typically, but not necessarily, symmetrical with respect to the gate pad structure 10, i.e. to a notional line running through the gate pad structure 10. A symmetrical arrangement improves a uniform switching of all cells.
From a manufacturing point, integrating the gate runner 2 with its internal resistor structure into the edge termination region 12 is possible by changing only three lithographical mask which are used for structuring polysilicon, metal layer and vias (contact openings). In some embodiments, only the lithographical masks for structuring the metal layer and for arranging the contact openings needs to be changed. Furthermore, it would be possible to change the specific electrical resistance or the sheet resistance of the high resistance electrical portions 8 by varying its doping concentration or thickness. These options facilitate custom-specific adaptation of the resistance of the gate runner 2.
With reference to
Typically, a semiconductor substrate 1 having a first and second surface 21, 22 is provided. The semiconductor substrate 1 typically includes at least one epitaxial layer 1a formed on a single crystalline wafer 1b. The free surface of the epitaxial layer 1a forms the first surface 21 while the free surface of the wafer 1b forms the second surface 22 of the semiconductor substrate 1. Furthermore, active cells are formed in the epitaxial layer 1a, and each cell is substantially completed, i.e. includes source and body regions and gate electrodes. These elements are not shown in
After completing the active cells, a first insulating layer 23 is formed on the first surface 21 of the semiconductor substrate 1. Thereon, a gate runner is formed.
As shown in
In a further step, shown in
The openings 28a are then filled with a low resistance material such as aluminium to form vias 28 as shown in
Together with the formation of the low electrical resistance portions 6 a gate pad structure 10 shown in
The semiconductor device as described herein is not restricted to power applications but can be used for any application for which an adaptation of the effective gate resistance is desired.
The gate runner as described herein may include low and high electrical resistance portions which can be alternatingly connected in series to tailor the resistance of the gate runner and therefore the effective gate resistance of the device's gate structure. The resistance of the gate runner can be varied by changing at least one of the length, cross-section, and number of the respective resistance portions or by a suitable combination thereof. The gate runner can be used for devices with and without gate fingers.
The gate runner is integral to the semiconductor device, i.e. is not externally provided. This at least partially or completely prevents the addition of unwanted parasitic capacitances and inductances, i.e. additional bond pads and bond wires. Furthermore, the integrated gate runner does not require additional space since the low and high electrical resistance portions are arranged in two levels above each other. From the manufacturing point of view, the resistance of the gate runner can be varied by changing at least one of the layout, length, width, height, and a combination thereof.
The written description above uses specific embodiments to disclose the invention, including the best mode, and also to enable any person skilled in the art to make and use the invention. While the invention has been described in terms of various specific embodiments, those skilled in the art will recognize that the invention can be practiced with modifications within the spirit and scope of the claims. Especially, mutually non-exclusive features of the embodiments described above may be combined with each other. The patentable scope is defined by the claims, and may include other examples that occur to those skilled in the art. Such other examples are intended to be within the scope of the claims if they have structural elements that do not differ from the literal language of the claims, or if they include equivalent structural elements with insubstantial differences from the literal languages of the claims.
