Patent Application
20250069981
The present disclosure relates to a semiconductor device and a method for manufacturing the same.
In a semiconductor power module, a solder joint material is used when an insulating substrate is joined onto a heat sink. In order to improve the thermal fatigue resistance of a solder joint material, it has been proposed to provide a groove in a heat sink along the outer peripheral portion of an insulating substrate (for example, see PTL 1).
Filling the groove with the solder joint material can increase the thickness of the solder joint material on the outer peripheral portion of the insulating substrate. This can prevent crack occurrence in the solder joint material due to: heat stress generated in operation of the semiconductor device; and stress on the insulating substrate and semiconductor chip. However, there has been a problem of solder voids occurring in the grooves and reducing the reliability of the semiconductor device.
The present disclosure has been made to solve the above-mentioned problems, and an object thereof is to obtain a semiconductor device and a method for manufacturing the same, capable of improving reliability.
A semiconductor device according to the present disclosure includes: an insulating substrate including an insulating layer, a first metal pattern provided on a lower surface of the insulating layer, and a second metal pattern provided on an upper surface of the insulating layer; a semiconductor chip joined to the second metal pattern; a heat sink provided below the insulating substrate and having an upper surface on which a groove is provided along an outer periphery of the insulating substrate; a first solder joint material filled in the groove; and a second solder joint material provided on the upper surface of the heat sink and the first solder joint material and joining the upper surface of the heat sink and the first metal pattern, wherein the first solder joint material and the second solder joint material are of different types, and a melting point of the first solder joint material is lower than a melting point of the second solder joint material.
In the present disclosure, the first solder joint material and the second solder joint material are of different types, and the melting point of the first solder joint material, with which the groove is filled, is made lower than the melting point of the second solder joint material. Therefore, since the first solder joint material first melts in reflow, the air bubbles in the first solder joint material move upward from the groove due to pressure from above. As a result, solder voids inside the groove are reduced, so that reliability can be improved.
A groove 6 is provided on the upper surface of the heat sink 5 along the outer periphery of each insulating substrate 1. The insulating substrate 1 is square in plan view, and the groove 6 is square frame-shaped. The inner periphery of the groove 6 is inside the outer periphery of the insulating substrate 1 in plan view, and the outer periphery of the groove 6 is coincident with the outer periphery of the insulating substrate 1 or outside it.
The groove 6 is filled with a first solder joint material 7. A second solder joint material 8 is provided on the upper surface of the heat sink 5 and the first solder joint material 7, and joins the upper surface of the heat sink 5 and the first metal pattern 1b.
Filling the groove 6 with the first solder joint material 7 can increase the thickness of the solder joint material on the outer peripheral portion of the insulating substrate 1. This can prevent crack occurrence in the solder joint material due to: heat stress generated in operation of the semiconductor device; and stress on the insulating substrate 1 and the semiconductor chip 3.
L>2H is satisfied, where: H is the distance between the upper surface of the heat sink 5 and the first metal pattern 1b; and L is the distance between the bottom surface of the groove 6 and the first metal pattern 1b. This makes the thickness of the solder joint material on the outer periphery of the insulating substrate 1 twice that of the conventional one, thus making it possible to lighten stress and prevent crack occurrence. Furthermore, the thickness of the solder joint material underneath the semiconductor chip 3 is the same as that of the conventional one, so that the heat dissipation performance does not reduce.
Next, a method for manufacturing a semiconductor device according to an embodiment will be described.
In the present embodiment, the first solder joint material 7 and the second solder joint material 8 are of different types, and the melting point of the first solder joint material 7, with which the groove 6 is filled, is made lower than the melting point of the second solder joint material 8. Therefore, since the first solder joint material 7 first melts in reflow, the air bubbles in the first solder joint material 7 move upward from the groove 6 due to pressure from above. As a result, solder voids inside the groove 6 are reduced, so that reliability can be improved. Note that the voids in the second solder joint material 8 on the heat sink 5 can be confirmed on the surface even after reflow, and therefore can be corrected by rework from outside.
The semiconductor chip 3 is not limited to a semiconductor chip formed of silicon, but instead may be formed of a wide-bandgap semiconductor having a bandgap wider than that of silicon. The wide-bandgap semiconductor is, for example, a silicon carbide, a gallium-nitride-based material, or diamond. A semiconductor chip formed of such a wide-bandgap semiconductor has a high voltage resistance and a high allowable current density, and thus can be miniaturized. The use of such a miniaturized semiconductor chip enables the miniaturization and high integration of the semiconductor device in which the semiconductor chip is incorporated. Further, since the semiconductor chip has a high heat resistance, a radiation fin of a heatsink can be miniaturized and a water-cooled part can be air-cooled, which leads to further miniaturization of the semiconductor device. Further, since the semiconductor chip has a low power loss and a high efficiency, a highly efficient semiconductor device can be achieved.
| Filing Document | Filing Date | Country | Kind |
|---|---|---|---|
| PCT/JP2022/019508 | 5/2/2022 | WO |
