Claims
- 1. A semiconductor memory device comprising:
a semiconductor substrate; an insulator film formed on said substrate; a ferroelectric capacitor having a bottom electrode, a ferroelectric film and a top electrode, which are sequentially stacked on said insulator film, said ferroelectric film being patterned on said bottom electrode having a predetermined pattern so as to have an area smaller than an area of said bottom electrode; an interlayer insulation layer covering the ferroelectric capacitor; and a hydrogen barrier film deposited on the interlayer insulation layer so that at least a top and side of said ferroelectric capacitor are enveloped via said interlayer insulation layer, wherein an extending portion of said hydrogen barrier film is at a level lower than said insulator film by a predetermined amount.
- 2. A semiconductor memory device comprising:
a semiconductor substrate; a first insulator film formed on said substrate; a ferroelectric capacitor having a bottom electrode, a ferroelectric film and a top electrode, which are sequentially stacked on said first insulator film, said ferroelectric film being patterned on said bottom electrode having a predetermined pattern so as to have an area smaller than an area of said bottom electrode; a first interlayer insulation layer covering the ferroelectric capacitor; a first hydrogen barrier film deposited on the first interlayer insulation layer so that at least a top and side of said ferroelectric capacitor are enveloped via said first interlayer insulation layer; a second interlayer insulation layer covering said first hydrogen barrier film; and a second hydrogen barrier film deposited on said second interlayer insulation layer, wherein said first and second hydrogen barrier films are disposed in a parallel plane.
- 3. A semiconductor memory device comprising:
a semiconductor substrate; an insulator film formed on said substrate; a ferroelectric capacitor having a bottom electrode, a ferroelectric film and a top electrode, which are sequentially stacked on said insulator film, said ferroelectric film being patterned on said bottom electrode having a predetermined pattern so as to have an area smaller than an area of said bottom electrode; an interlayer insulation layer covering the ferroelectric capacitor; a hydrogen barrier film deposited on the interlayer insulation layer so that at least a top and side of said ferroelectric capacitor are enveloped via said interlayer insulation layer; and a protective film formed on said hydrogen barrier film for protecting against at least one of hydrogen gas and a halogen gas such that a surface of said top electrode and sides of said ferroelectric film and said bottom electrode are covered.
- 4. A semiconductor memory device comprising:
a semiconductor substrate; a first insulator film formed on said substrate; a ferroelectric capacitor having a bottom electrode, a ferroelectric film and a top electrode, which are sequentially stacked on said first insulator film, said ferroelectric film being patterned on said bottom electrode having a predetermined pattern so as to have an area smaller than an area of said bottom electrode; a first interlayer insulation layer covering the ferroelectric capacitor; and a first hydrogen barrier film deposited on the first interlayer insulation layer so that at least a top and side of said ferroelectric capacitor are enveloped via said first interlayer insulation layer, wherein said ferroelectric capacitor further comprises a second insulator film formed on said top electrode, and a third insulator film formed to cover said second insulator film and sides of said ferroelectric film.
- 5. The semiconductor memory device as set forth in claim 4, wherein a first residual of the top electrode material remains on a side of said top electrode and a second residual of the ferroelectric film material remains on a side of the ferroelectric film.
- 6. The semiconductor memory device as set forth in claim 4, wherein a surface of said top electrode and sides of said ferroelectric film and said bottom electrode are covered with a protective film for protecting against at least one of hydrogen gas and a halogen gas.
- 7. The semiconductor memory device as set forth in claim 4, further comprising:
a second interlayer insulation layer covering said first hydrogen barrier film; and a second hydrogen barrier film deposited on said second interlayer insulation layer.
- 8. The semiconductor memory device as set forth in claim 4, wherein an extending portion of said first hydrogen barrier film is at substantially the same level as said first insulator film.
- 9. The semiconductor memory device as set forth in claim 4, wherein an extending portion of said first hydrogen barrier film is at a lower level than said first insulator film.
- 10. The semiconductor memory device as set forth in claim 4, further comprising:
a second interlayer insulation layer covering said first hydrogen barrier film; and a second hydrogen barrier film deposited on said second interlayer insulation layer, wherein said first and second hydrogen barrier films are disposed in a parallel plane.
- 11. The semiconductor memory device as set forth in claim 4, wherein an end portion of said first hydrogen barrier film extends to adjacent element regions.
- 12. The semiconductor memory device as set forth in claim 4, wherein said second and third insulator films are silicon oxide films.
- 13. The semiconductor memory device as set forth in claim 4, wherein said ferroelectric film is made of a plurality of stacked layers of perovskite compound including at least one of lead or bismuth.
- 14. The semiconductor memory device as set forth in claim 13, wherein said stacked layers have two layers of perovskite compound, a lower layer having a lower concentration of elements contained in the top electrode than an upper layer.
- 15. The semiconductor memory device as set forth in claim 13, wherein said stacked layers have two layers of perovskite compound, an upper layer having a lower concentration of elements contained in the bottom electrode than a lower layer.
- 16. The semiconductor memory device as set forth in claim 13, wherein said stacked layers have three layers of perovskite compound, and an intermediate layer has a lower concentration of elements contained in the top and bottom electrodes than a lower layer and an upper layer.
- 17. The semiconductor memory device as set forth in claim 4, wherein a surface of said top electrode and sides of said ferroelectric film and said bottom electrode are covered with a protective film for protecting against at least one of hydrogen gas and a halogen gas.
- 18. A semiconductor device comprising:
a semiconductor substrate; an insulator film formed on said substrate; a ferroelectric capacitor having a bottom electrode, a ferroelectric film and a top electrode, which are sequentially stacked on said insulator film, said ferroelectric film being patterned on said bottom electrode having a predetermined pattern so as to have an area smaller than an area of said bottom electrode; and an interlayer insulation layer covering the ferroelectric capacitor, said interlayer insulation layer containing metal oxide material exhibiting hydrogen barrier characteristics.
- 19. A semiconductor memory device comprising:
a semiconductor substrate; an insulator film formed on said substrate; a ferroelectric capacitor having a bottom electrode, a ferroelectric film and a top electrode, which are sequentially stacked on said first insulator film, said ferroelectric film being patterned on said bottom electrode having a predetermined pattern so as to have an area smaller than an area of said bottom electrode; an interlayer insulation layer covering the ferroelectric capacitor; and a hydrogen barrier film deposited on the interlayer insulation layer so that at least a top and side of said ferroelectric capacitor are enveloped via said interlayer insulation layer, wherein said ferroelectric film is made of a plurality of stacked layers of perovskite compound including at least one of lead or bismuth.
- 20. The semiconductor memory device as set forth in claim 19, wherein said stacked layers have two layers of perovskite compound, a lower layer having a lower concentration of elements contained in the top electrode than an upper layer.
- 21. The semiconductor memory device as set forth in claim 19, wherein said stacked layers have two layers of perovskite compound, an upper layer having a lower concentration of elements contained in the bottom electrode than a lower layer.
- 22. The semiconductor memory device as set forth in claim 19, wherein said stacked layers have three layers of perovskite compound, an intermediate layer having a lower concentration of elements contained in the top and bottom electrodes than a lower layer and a top layer.
Priority Claims (3)
Number |
Date |
Country |
Kind |
208999/1998 |
Jul 1998 |
JP |
|
324254/1998 |
Nov 1998 |
JP |
|
345368/1998 |
Apr 1998 |
JP |
|
CROSS-REFERENCE TO RELATED APPLICATION
[0001] This application is a divisional of U.S. patent application Ser. No. 09/359,324 filed Jul. 23, 1999, which is based upon and claims the benefit of priority from the prior Japanese Patent Application Nos. 208999/1998, filed Jul. 24, 1998; 324254/1998, filed Nov. 13, 1998; and 345368/1998, filed Apr. 12, 1998, the entire contents of which are incorporated herein by reference.
Divisions (1)
|
Number |
Date |
Country |
Parent |
09359324 |
Jul 1999 |
US |
Child |
10443107 |
May 2003 |
US |