A method of manufacturing a semiconductor device includes forming an insulating layer over the semiconductor substrate and the gate electrode. An insulating layer may have a via hole connected to the semiconductor substrate or the gate electrode and a trench connected to the via hole. A first barrier layer and a second barrier layer may be formed. The first barrier layer and the second barrier layer may be annealed to form a silicide and combine the first barrier layer and the second barrier layer to form a metal compound.
Description
BRIEF DESCRIPTION OF THE DRAWINGS
Example FIGS. 1 to 7 are sectional views illustrating processes of manufacturing a semiconductor device, according to embodiments.
Claims
1. A method comprising:
forming an insulating layer over a semiconductor substrate;etching at least one structure in the insulating layer;forming a first barrier layer over said at least one structure; andforming a second barrier layer over the first barrier layer, wherein the material of the first barrier layer is different from the material of the second barrier layer.
2. The method of claim 1, wherein the material of the first barrier layer comprises titanium.
3. The method of claim 1, wherein the material of the second barrier layer comprises tungsten.
4. The method of claim 1, wherein said at least one structure comprises at least one of:
at least one via hole; andat least one trench.
5. The method of claim 4, wherein:
each of said at least one hole exposes at least a portion of one of the semiconductor substrate and a gate electrode; andsaid at least one trench is contiguous with said at least one via hole.
6. The method of claim 1, comprising annealing the first barrier layer and the second barrier layer.
7. The method of claim 6, wherein said annealing forms silicide.
8. The method of claim 7, wherein the silicide is titanium silicide
9. The method of claim 7, wherein said silicide is formed in at least one of:
the semiconductor substrate; anda gate electrode.
10. The method of claim 7, wherein said annealing forms a metal compound from the combination of the first barrier layer and the second metal layer.
11. The method of claim 10, wherein said metal compound is titanium tungsten.
12. The method of claim 6, wherein annealing the first barrier layer and the second barrier layer forms silicide and forms a metal compound from the combination of the first barrier layer and the second metal layer at substantially the same time.
13. The method of claim 1, comprising forming a metal wiring layer to fill said at least one structure.
14. The method of claim 13, wherein the metal wiring layer comprises copper.
15. A semiconductor device comprising:
an insulating layer formed over a semiconductor substrate;at least one via hole etched in the insulating layer;at least one trench etched in the insulating layer;a first barrier layer formed over said at least one structure; anda second barrier layer formed over the first barrier layer, wherein the material of the first barrier layer is different from the material of the second barrier layer.
16. The semiconductor device of claim 15, wherein at least one of:
the material of the first barrier layer comprises titanium; andthe material of the second barrier layer comprises tungsten.
17. The semiconductor device of claim 15, comprising a gate electrode formed over the semiconductor substrate, wherein:
the insulating layer is formed over the semiconductor substrate and the gate electrode;each of said at least one hole exposes at least a portion of one of the semiconductor substrate and the gate electrode; andsaid at least one trench is contiguous with said at least one via hole.
18. The semiconductor device of claim 15, wherein the first barrier layer and the second barrier layer are annealed to form at substantially the same time:
silicide; anda metal compound from the combination of the first barrier layer and the second metal layer.
19. The semiconductor device of claim 15, comprising a metal wiring layer in at least one of said at least one via hole and said at least one trench.
20. The semiconductor device of claim 19, wherein the metal wiring layer comprises copper.
Patent Application
20070145492
