Patent Application
20240250167
The present invention relates to a semiconductor device, and particularly relates to a semiconductor device that suppresses an increase in contact resistance and a method of manufacturing the same.
In a MOS field effect transistor (MOSFET) that uses silicon (Si), double diffusion is used to form, in a p-type well region, an n+ source region to which a high concentration of impurities has been added. However, the diffusion coefficient of impurity atoms in a silicon carbide (SiC) substrate is extremely low, and it is not possible to use double diffusion. To address this, in a MOSFET that uses SiC, double ion implantation is used to form the p-type well region, and the n+ source region in the well region. In this method, high concentration ion implantation induces a large number of crystal defects. This may cause an increase in contact resistance or ON resistance. To solve such a problem, it has been proposed that a p-type well region be deposited and then a high concentration source region be selectively formed via ion implantation (see Patent Document 1).
In recent years, in MOSFETs that use SIC, a p+ base contact layer and an n+ source region have been formed adjacent to each other on a p-type base region. Ordinarily, the n-type source region is selectively formed via ion implantation first, and next the p-type base contact region is selectively formed via ion implantation so as to contact the source region. The impurity densities for the source region and the base contact region are both around several 1020 cm−3 (1020 level). In this case, there are cases where the base contact region overlaps the source region due to mask alignment deviations of the selective ion implantation for the base contact region. The impurity densities implanted into the source region and base contact region are around the same, and thus the overlapping portion will have higher resistance due to carrier compensation. Due to this, contact resistance increases, and this is a cause of an increase in ON resistance, an increase in forward voltage of the body diode, etc.
Patent Document 1: Japanese Patent Application Laid-Open Publication No. 2011-23757
In view of the aforementioned problems, the present invention aims at providing a semiconductor device and a method of manufacturing the same that can prevent mask alignment deviations and can suppress an increase in ON resistance and forward voltage of a body diode.
Additional or separate features and advantages of the invention will be set forth in the descriptions that follow and in part will be apparent from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and claims thereof as well as the appended drawings.
To achieve these and other advantages and in accordance with the purpose of the present invention, as embodied and broadly described, in one aspect, the present disclosure provides a semiconductor device, including: (a) a drift layer of a first conductivity type; (b) a current spreading region of the first conductivity type provided on the drift layer and having a higher impurity density than the drift layer; (c) a base region of a second conductivity type provided on the current spreading region; (d) a base contact region of the second conductivity type provided in a top part of the base region and having a higher impurity density than the base region; and (e) an electrode contact region of the first conductivity type provided in a top part of the base region that is laterally in contact with the base contact region, the electrode contact region having a higher impurity density than the drift layer, (f) wherein a density of a second conductivity type impurity element in the base contact region is at least two times as much as a density of a first conductivity type impurity element in the electrode contact region.
In another aspect, the present disclosure provides a method of manufacturing a semiconductor device, the method including: (a) epitaxially growing a first epitaxial layer of a first conductivity type on a top surface of a drift layer of the first conductivity type; (b) selectively implanting impurity ions of the first conductivity type into the first epitaxial layer so as to be of a higher impurity density than a impurity density of the first epitaxial layer, thereby forming a current spreading region in an active region and forming a channel stopper region on an outer edge of a termination region surrounding the active region; (c) epitaxially growing a base region of a second conductivity type on the first epitaxial layer; (d) selectively implanting second conductivity type impurity ions into the base region, thereby selectively embedding a base contact region of the second conductivity type in a top part of the base region with a higher impurity density than the base region; and (e) implanting first conductivity type impurity ions into an entire surface of the base region including the embedded base contact region at a dosage lower than a dosage of the second conductivity type impurity ions implanted to form the base contact region, thereby forming an electrode contact region of the first conductivity type in a top part of the base region that is laterally in contact with the base contact region.
The present invention makes it possible to provide a semiconductor device and a method of manufacturing the same that can prevent mask alignment deviations.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory, and are intended to provide further explanation of the invention as claimed.
Embodiment of the present invention will be described below with reference to the drawings. In the drawings, portions that are the same or similar will be assigned the same or similar reference characters and redundant explanations will be omitted. However, the drawings are schematic, and the relationship between thickness and planar dimensions, the ratio of the thickness of each layer, etc. may differ in practice. Furthermore, there can be parts for which the relationship between dimensions, ratios, etc. differ even among the drawings. Embodiment shown below illustratively indicates a device and method for carrying out the technical idea of the present invention, and the technical idea of the present invention is not limited to the material, shape, structure, arrangement, etc. of the constituent components described below.
In the present specification, “first main electrode region” means a semiconductor region serving as either a source region or a drain region in a field effect transistor (FET) or static induction transistor (SIT). In an insulated gate bipolar transistor (IGBT), “first main electrode region” means a semiconductor region serving as either an emitter region or a collector region. In a static inductor thyristor (SI thyristor) or gate turn-off thyristor (GTO), “first main electrode region” means a semiconductor region serving as either the anode region or cathode region. “Second main electrode region” means, in an FET or SIT, a semiconductor region serving as whichever of the source region or drain region that is not the first main electrode region. In an IGBT, “second main electrode region” means a region serving as whichever of the emitter region or collector region that is not the first main electrode region. In an SI thyristor or GTO, “second main electrode region” means a region serving as whichever of the anode region or cathode region that is not the first main electrode region. Thus, if the “first main electrode region” is the source region, then “second main electrode region” means the drain region. If the “first main electrode region” is the emitter region, then “second main electrode region” means the collector region. If the “first main electrode region” is the anode region, then “second main electrode region” means the cathode region. If the bias relationship is interchanged, then in an FET or the like, the function of the “first main electrode region” and the function of the “second main electrode region” are interchangeable.
In addition, the definition of directions such as up-down in the description below are merely definitions for convenience of explanation and do not limit the technical idea of the present invention. For example, if an object is observed after being rotated 90°, up-down is converted to left-right, and if observed after being rotated 180°, up-down is inversed. Further, in the description below, the first conductivity type is illustratively described as n-type and the second conductivity as p-type, which is the opposite conductivity type of the first conductivity type. However, an inverse relationship may be selected for the conductivity types, where the first conductivity type is p-type and the second conductivity type is n-type, which is the opposite conductivity type of the first conductivity type. A “+” or “−” attached to an “n” or “p” signifies that the semiconductor region has higher or lower impurity element density, respectively, than a semiconductor region not having the “+” or “−”. However, this does not mean that semiconductor regions that are both labelled “n” have exactly the same impurity densities.
As is described below, one characteristic of the present invention is preventing an increase in contact resistance caused by mask alignment deviation. In other words, the present invention exhibits marked effects in preventing an increase in forward voltage of a body diode and ON resistance of an insulated gate transistor such as a MOS transistor. The insulated gate transistor can also be more comprehensively referred to as a “MIS transistor,” but MIS transistor includes MISFETs, MISSITs, etc. There are also MIS composite type SI thyristors, and thus the present invention can also be applied to SI thyristors. Furthermore, it is also possible to prevent leakage current at the interface between the insulating film layer and the semiconductor layer, which serves as a high voltage withstand structure at the periphery of a power semiconductor device. In the description of the embodiment below, as shown in
As shown in
In the active region 40, an n+ current spreading region (CSL) (4a, 6a) is disposed with a higher impurity density than the drift layer 2 on the top surface of the drift layer 2. A base region 8 of a second conductivity type (p-type) is disposed on the top surface of the current spreading region (4a, 6a). The drift layer 2 and base region 8 are each formed by epitaxially grown layers made of SiC (hereinafter abbreviated as “epitaxial layers”). The current spreading region (4a, 6a) is formed by implantation layers 4a, 6a in which an n-type impurity has been ion implanted in an epitaxial layer.
A p+ base contact region 9 of a higher impurity density than the base region 8 is selectively provided in the top part of the base region 8. An n+ first main electrode region (source region) 10 of a higher impurity density than the current spreading region (4a, 6a) is selectively provided in the top part of the base region 8 so as to contact the base contact region 9. The base contact region 9 is provided via ion implantation of a p-type impurity such as aluminum (Al) at an impurity density of 1×1020 cm−3 to 10×1020 cm−3, for example, and the source region 10 is provided via ion implantation of an n-type impurity such as phosphorous (P) at an impurity density of 1×1019 cm−3 to 10×1019 cm−3, for example. It is desirable that the impurity density of the source region 10 be around ½ or less of the impurity density of the base contact region 9. The depth Dp between the top surface and bottom surface of the base contact region 9 is around 0.4 μm to 0.6 μm, and the depth Dn between the top surface and bottom surface of the main electrode region 10 is around 0.2 μm to 0.5 μm.
A trench 11 is provided going through the base region 8 from the top surface of the source region 10 and base region 8. A gate insulating film 12 is provided on the bottom surface and side surfaces of the trench 11. In addition to a silicon oxide film (SiO2 film), a single layer film of any one of a silicon oxynitride (SiON) film, strontium oxide (SrO) film, silicon nitride (Si3N4) film, aluminum oxide (Al2O3) film, magnesium oxide (MgO) film, yttrium oxide (Y2O3) film, hafnium oxide (HfO2) film, zirconium oxide (ZrO2) film, tantalum oxide (Ta2O5) film, and bismuth oxide (Bi2O3) film, or a composite film in which a plurality of these films are laminated, or the like may be used as the gate insulating film 12.
A gate electrode 13 is embedded in the trench 11 with the gate insulating film 12 interposed therebetween. The material of the gate electrode 13 can be a polysilicon layer (doped polysilicon layer) to which a high impurity density of an impurity such as phosphorous (P) has been added.
A p+ gate bottom protection region 5b is provided inside the current spreading region (4a, 6a) so as to contact the bottom of the trench 11. A first base bottom embedded region 5a is provided inside the current spreading region (4a, 6a), below the base contact region 9, at the same depth as the gate bottom protection region 5b, and separated from the gate bottom protection region 5b. A second base bottom embedded region 7a is provided in the top part of the current spreading region (4a, 6a) so as to be interposed between the top surface of the first base bottom embedded region 5a and the bottom surface of the base region 8.
A source electrode (not shown) is disposed on the top surface of the gate electrode 13 with an interlayer insulating film 14 interposed therebetween so as to be separated from a gate surface electrode (not shown) positioned in the depth of the sheet of drawing. The interlayer insulating film 14 can be a non-doped silicon oxide film (SiO2 film) that does not contain phosphorous (P) or boron (B), which is referred to as “NSG.” However, the interlayer insulating film 14 may be a silicon oxide film to which phosphorous has been added (PSG), a silicon oxide film to which boron has been added (BSG), a silicon oxide film to which boron and phosphorous have been added (BPSG), a silicon nitride film (Si3N4), or the like. A source contact layer 15, bottom barrier metal layer 16, and top barrier metal layer 17 are disposed in layers below the source electrode. The source contact layer 15 is disposed so as to metallurgically contact the source region 8 and the base contact region 9. For example, the source contact layer 15 can be a nickel (Ni) film, the bottom barrier metal layer 16 can be a titanium nitride (TiN) film, and the top barrier metal layer 17 can be a titanium (Ti)/TiN/Ti laminate structure. The source electrode can be an aluminum (Al) film, for example. The gate surface electrode can be the same material as the source electrode.
An n+ second main electrode region (drain region) 1 is disposed on the bottom surface of the drift layer 2. The drain region 1 is formed by a semiconductor substrate made of SiC (SiC substrate). A second main electrode region (drain region) 19 is disposed on the bottom surface of the drain region 1. The drain electrode 19 can be a single layer film made of gold (Au), a metal film in which Al, nickel (Ni), and Au have been laminated in the stated order, or the like, and a metal film such as molybdenum (Mo) or tungsten (W) may be further laminated on the bottommost layer thereof, for example.
Focusing on the termination region 42 side positioned on the right side of
As described above, in the semiconductor device according to the embodiment of the present invention, the impurity density in the base contact region 9 is always higher than the impurity density in the source region 10 in the region reaching the base region 8. Due to this, neither the base contact region 9 nor the source region 10 has high resistance caused by carrier compensation, and it is possible to suppress an increase in ON resistance and forward voltage of the body diode. In addition, the termination region 42 is provided with the relaxation region (5c, 7b) and spatial modulation parts 18a, 18b, 18c, and 18d; thus, it is possible to relax electric field concentration. Moreover, the outer edge of the termination region 42 is provided with the channel stopper region (4b, 6b); thus, it is possible to maintain a high voltage applied to the MOSFET. Accordingly, it is possible to improve the withstand voltage of the termination region 42 and to provide a high withstand voltage device.
Next, while referring to
First, an n+ semiconductor substrate (SiC substrate) to which an n-type impurity such as nitrogen (N) has been added is prepared. With this n+ SiC substrate as the drain region (not shown), then drift layer 2 is epitaxially grown on the top surface of the drain region. Next, the n-type mesa bottom surface layer 3 is epitaxially grown on the top surface of the drift layer 2. Photolithography and ion implantation or the like are used to implant p-type impurity ions while appropriately masking the vicinity of the outer edge of the termination region 42. Next, photolithography and ion implantation or the like are used to selectively implant n-type impurity ions. As shown in
A new growth layer 6 is epitaxially grown on the top surface of the ion-implanted mesa bottom surface layer 3. Next, photolithography and ion implantation or the like are used to selectively implant n-type impurity ions into the growth layer 6. As shown in
Next, photolithography and ion implantation or the like are used to selectively implant p-type impurity ions. As shown in
As shown in
Next, ion implantation or the like is used to implant the n-type impurity ions into the entire surface of the base region 8 where the base contact region 9 is formed without using a mask. As shown in
Photolithography and dry etching such as reactive ion etching (RIE) or the like are used to perform mesa etching of the termination section, and a portion of the semiconductor layer in the termination region 42 is removed to form a level-difference having a mesa inclined surface. As shown in
Photolithography and dry etching or the like are used to form the trench 11. Next, chemical vapor deposition (CVD) or the like is used to deposit an insulating film. Thereafter, photolithography and dry etching or the like are used to embed a polysilicon layer in the trench 11 to form a gate structure made of the gate insulating film 12 and gate electrode 13. Afterwards, photolithography and ion implantation or the like are used to provide the JTE region 18 having the spatial modulation parts 18a, 18b, 18c, 18d inside the growth layer 6 going from the bottom end of the mesa inclined surface formed in the termination region 42 toward the outer edge of the termination region 42.
Next, the interlayer insulating film 14 is formed on the gate structure and on an area from the mesa inclined surface to the outer edge of the termination region 42. Thereafter, the source contact layer 15, bottom barrier metal layer 16, and top barrier metal layer 17 are formed on the top surface, and the drain electrode 19 is formed on the rear surface, thus completing the MOSFET shown in
Next, while referring to
Photolithography and dry etching such as reactive ion etching (RIE) or the like are used to perform mesa etching of the termination section, and a portion of the semiconductor layer in the termination region 42 is removed to form a level-difference having a mesa inclined surface. As shown in
Thereafter, photolithography and ion implantation or the like are used to selectively implant the n-type impurity ions. As shown in
Photolithography and ion implantation or the like are used to selectively implant the p-type impurity ions. As shown in
Photolithography and dry etching or the like are used to form the trench 11. Next, chemical vapor deposition (CVD) or the like is used to deposit an insulating film. Thereafter, photolithography and dry etching or the like is used to embed a polysilicon layer in the trench 11 to form a gate structure made of the gate insulating film 12 and gate electrode 13. Afterwards, photolithography and ion implantation or the like are used to provide the JTE region 18 inside the growth layer 6 going from the bottom end of the mesa inclined surface formed in the termination region 42 toward the outer edge of the termination region 42. At such time, a p-type impurity is implanted into the mesa inclined surface with the ion implantation for the formation of the JTE region 18. The impurity density of the p-type ion implantation for forming the JTE region 18 is around 2×1017 cm−3, for example. The p-type base region 8 has an impurity density of around 4×1017 cm−3, and thus, after ion implantation for forming the JTE region 18, the p-type impurity density is around 6×1017 cm−3 and thus not a high impurity density.
As described above, the method of manufacturing the conventional MOSFET uses a mask in the source region 10 ion implantation step. On the other hand, in the method of manufacturing the MOSFET according to the present invention, ion implantation is performed on the entire surface to form the source region 10 without using a mask. Accordingly, the number of the mask layers is reduced, and mask alignment is also unnecessary. As a result, it is possible to shorten the manufacturing process and also to reduce manufacturing costs.
The present invention was described using the embodiment above, but the descriptions and drawings forming this part of the disclosure should not be construed as limiting the present invention. Various substitute embodiments, examples, and applied techniques should be clear to a person skilled in the art based on this disclosure.
In the embodiment of the present invention, a MISFET having a trench structure was shown as an example, but the present invention is not limited to this and can be applied to a semiconductor device having various types of trench structures such as an IGBT with a trench structure. The trench gate IGBT can be a structure in which the n+ source region 8 of the MISFET shown in
In the embodiment of the present invention, an example was shown in which the semiconductor device uses SiC, but the present invention can be applied to semiconductor devices using other wide bandgap semiconductors, such as gallium nitride (GaN) or diamond.
It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention. Thus, it is intended that the present invention cover modifications and variations that come within the scope of the appended claims and their equivalents. In particular, it is explicitly contemplated that any part or whole of any two or more of the embodiments and their modifications described above can be combined and regarded within the scope of the present invention.
| Number | Date | Country | Kind |
|---|---|---|---|
| 2017-234637 | Dec 2017 | JP | national |
This application is filed as a continuation application of U.S. patent application Ser. No. 17/037,209, filed Sep. 29, 2020, which is a continuation application of U.S. patent application Ser. No. 16/182,199, filed on Nov. 6, 2018, in the United States Patent and Trademark Office, which claims the priority benefit of Japanese Patent Application No. 2017-234637, filed on Dec. 6, 2017, in the Japanese Patent Office. The disclosures of U.S. patent application Ser. Nos. 17/037,209, 16/182,199 and Japanese Patent Application No. 2017-234637 are incorporated by reference herein in their entireties.
| Number | Date | Country | |
|---|---|---|---|
| Parent | 17037209 | Sep 2020 | US |
| Child | 18625430 | US | |
| Parent | 16182199 | Nov 2018 | US |
| Child | 17037209 | US |
