Patent Application
20080012081
The present invention relates to a semiconductor device and a method of manufacturing the same, more specifically a semiconductor device including a plurality of MIS transistors and a method of manufacturing the same.
Recently, the increasing demand of portable electronic devices rapidly expands the market of the LSI of the portable electronic devices. Most portable electronic devices are driven by batteries and, as operational requirements of the LSI of such portable electronic devices, the LSI is required to decrease the leak current of the electronic devices in stand-by to thereby decrease the electric power consumption thereof in addition to the high-speed operation.
Accordingly, the MOS transistors used in such electronic devices are required to decrease the leak current.
The present invention is directed to various embodiments of a semiconductor device and a method for manufacturing the semiconductor device having source diffused layers and drain diffused layers of a plurality of MIS transistors arranged side by side in the same direction, and with the gate electrodes as the mask, an impurity for forming pocket regions is implanted in one direction slanted toward the source sides with respect to the semiconductor substrate surface.
The leak current of the MOS transistor is explained with reference to
As illustrated, on a semiconductor substrate 100 of a first conduction type, a gate electrode 104 is formed with a gate insulating film 102 formed therebetween. A sidewall insulating film 106 is formed on the side walls of the gate electrode 104.
In the semiconductor substrate 100 on the source side of the gate electrode 104, a source diffused layer 112 of a second conduction type is formed of an LDD (Lightly Doped Drain) region 108 formed by self-alignment with the gate electrode 104 and an impurity diffused region 110 formed by self-alignment with the gate electrode 104 and the sidewall insulating film 106. In the semiconductor substrate 100 on the drain side of the gate electrode 104, a drain diffused layer 118 of the second conduction type is formed of an LDD region 114 formed by self-alignment with the gate electrode 104 and an impurity diffused region 116 formed by self-alignment with gate electrode 104 and the sidewall insulating film 106. A channel region 120 is between the source diffused layer 112 and the drain diffused layer 118.
Pocket regions 122 of the first conduction type are respectively formed between the source diffused layer 112 and the channel region 120 and between the drain diffused layer 118 and the channel region 120. When the gate length of the gate electrode 104 is decreased, the threshold voltage of the MOS transistor is lowered, and the operation is made unstable. For the purpose of preventing this, the pocket regions 122 are formed.
In such MOS transistor, as components of the leak current are known the sub-threshold leak (IS) which flows from the drain diffused layer 118 toward the source diffused layer 112, the gate induced drain leakage (GIDL) which flows from the drain diffused layer 118 toward the semiconductor substrate 100, and the gate leak (IG) which flows from the gate electrode 104 toward the semiconductor substrate 100.
The GIDL is generated in the interface between the LDD region 114 and the pocket region 122 at the end of the gate electrode 104 on the drain side. The GIDL increases when the concentrations of impurities implanted in the LDD region 114 and the pocket region 122 are higher.
As evident in the graph, the IS and the GIDL are dominant as the components of the leak current in both the NMOS transistor and the PMOS transistor. In contrast to these, the IG is sufficiently small in comparison with the IS and the GIDL and ignorable as a component of the leak current. For a 0.18 μm node, for example, the IG is smaller by about 2 places than the IS and the GIDL, although varying depending on process technique for the LSI. Accordingly, to decrease the leak current of the MOS transistors, it is important to decrease the IS or the GIDL of the respective components of the leak current.
Here, the pocket ion implantation made to form the pocket regions in the semiconductor device will be explained with reference to FIGS. 3 to 5.
As described above, the pocket regions 122 are formed for the end of preventing the operation of the MOS transistor becoming unstable when the gate length of the gate electrode 104 is small. However on the other hand, the pocket ion implantation, which increases the impurity concentration high in these regions, is one cause for increasing the GIDL.
As illustrated in
In contrast to this, as illustrated in
The angle θ by which the direction of the pocket ion implantation is slanted toward the source side or the drain side is set in the range of 0°<θ<90°.
In the semiconductor devices, however, due to the layout of a plurality of MOS transistors, the pocket ion implantation is made so that the impurity implanted by the pocket ion implantation becomes uniform among the plural MOS transistors.
Based on the circuit scale, the plural MOS transistors 124 of the semiconductor device are not arranged in a certain direction. Consequently, as illustrated in
The ion implantation, as of the pocket ion implantation, etc., is made in a plurality of directions so that impurities can be implanted uniformly in all of the plural MOS transistors.
As indicated by the arrows in the drawing, in the MOS transistors 124, the pocket ion implantation is made in the four directions.
As described above, in the semiconductor device including a plurality of MOS transistors, the layout directions of the source diffused layers and the drain diffused layers are not uniform. Accordingly, it is difficult to make the ion implantation selectively in all the plural MOS transistors from one of the source side and the drain side. When the pocket ion implantation is made in the four directions as illustrated in
The semiconductor device and the method of manufacturing the same according to a first embodiment of the present invention will be explained with reference to FIGS. 6 to 11.
First, the structure of the semiconductor device according to the present embodiment will be explained with reference to FIGS. 6 to 8.
In the semiconductor device according to the present embodiment, as illustrated in
The plural MOS transistors 12 include PMOS transistors and NMOS transistors. All the plural MOS transistors 12 may be PMOS transistors or NMOS transistors.
The source diffused layers 28 and the drain diffused layers 34 of the plural MOS transistors 12 are arranged side by side in the same direction.
In the semiconductor substrate 10, a device isolation film 14 defining an active region is formed.
In the semiconductor substrate 10 with the active region defined, a well 16 of a first conduction type is formed.
On the semiconductor substrate 10, the gate electrode 20 is formed with a gate insulating film 18 formed therebetween. A sidewall insulating film 22 is formed on the side walls of the gate electrode 20.
In the semiconductor substrate 10 on the source side of the gate electrode 20, the source diffused layer 28 of a second conduction type is formed of an LDD region 24 formed by self-alignment with the gate electrode 20, and an impurity diffused region 26 formed by self-alignment with the gate electrode 20 and the sidewall insulating film 22. In the semiconductor substrate 10 on the drain side of the gate electrode 20, the drain diffused layer 34 of the second conduction type is formed of an LDD region 30 formed by self-alignment with the gate electrode 20, and an impurity diffused region 32 formed by self-alignment with the gate electrode 20 and the sidewall insulating film 22. Between the source diffused layer 28 and the drain diffused layer 34 is a channel region 36 of a first conduction type.
A pocket region 38 of the first conduction type is formed between the source diffused layer 28 and the channel region 36. Between the drain diffused layer 34 and the channel region 36, however, no pocket region is formed. That is, between the drain diffused layer 34 and the channel region 36 is a region (pocket impurity-not-implanted region) 40 where the impurity by pocket ion implantation (pocket impurity) is not implanted due to the shadow effect of the gate electrode 20.
Silicide films 42 are formed on the gate electrode 20, the source diffused layer 28 and the drain diffused layer 34.
The semiconductor device according to the present embodiment is characterized mainly in that the source diffused layers 28 and the drain diffused layers 34 of a plurality of MOS transistors 12 are arranged side by side in the same direction, the pocket region 38 is formed selectively between the source diffused layer 28 and the channel region 36 of each MOS transistor 12, and between the drain diffused layer 34 and the channel region 36 is the pocket impurity not implanted region 40.
The source diffused layers 28 and the drain diffused layers 34 of a plurality of MOS transistors 12 are arranged side by side in the same direction, which permits the pocket ion implantation be made in one direction slanted toward the source side for the respective MOS transistors 12. Thus, the pocket region 38 is formed selectively between the source diffused layer 28 and the channel region 36 of each MOS transistor 12, and the pocket impurity not-implanted-region 40 can be formed between the drain diffused layer 34 and the channel region 36 of each MOS transistor 12. Accordingly, the GIDL of all the plural MOS transistors 12 can be decreased, and the electric power consumption of the semiconductor device in stand-by can be decreased.
As evident in the graph of
As evident in the graph of
As described above, according to the present embodiment, the leak current of the MOS transistors can be decreased without deteriorating the operational characteristics of the MOS transistors.
Next, the method of manufacturing the semiconductor device according to the present embodiment will be explained with reference to FIGS. 9 to 11.
First, in the semiconductor substrate 10 of, e.g., silicon, the device isolation film 14 is formed by, e.g., STI (Shallow Trench Isolation) method to define active regions where a plurality of MOS transistors 12 are to be formed (
Next, an impurity is implanted into the semiconductor substrate 10 by, e.g., ion implantation to form the well 16 of a prescribed conduction type. Into the region where PMOS transistor is to be formed in, phosphorus (P), for example, as an n-type impurity is ion-implanted under conditions, e.g., of a 500 keV acceleration energy and a 1×1013 cm−2 dose. As the n-type impurity, antimony (Sb), arsenic (As) or others may be used. Into the region where the NMOS transistor is to be formed, boron (B), for example, as a p-type impurity is implanted under conditions, e.g., of a 250 keV acceleration energy and a 1×1013 cm−2 dose. As the p-type impurity, iridium (In) or others etc. may be used.
In the ion implantation of the impurity for forming the well 16, a photoresist film prepared by lithography is used as the mask to implant the impurities respectively into the region where the PMOS transistor is to be formed in and the region where the NMOS transistor is to be formed in. This is the same with the ion implantations which will be made later.
Then, an impurity of a prescribed conduction type is implanted into the channel region 36 in the semiconductor substrate 10 by, e.g., ion implantation (
Then, on the semiconductor substrate 10, the gate insulating film 18 of, e.g., a 3 nm-thickness silicon oxide film is formed by, e.g., thermal oxidation (
Next, a 200 nm-thickness polysilicon film 20, for example, is formed by, e.g., thermal CVD (Chemical Vapor Deposition) method (
Then, by lithography and etching, the polysilicon film 20 is patterned to form the gate electrode 20 of the polysilicon film having, e.g., a 200 nm-gate length (
Then, with the gate electrode 20 as the mask, an impurity is implanted in the semiconductor substrate 10 on both sides of the gate electrode 20. Thus, the LDD regions 24, 30 are formed in the semiconductor substrate 10 on the source side and the drain side of the gate electrode 20 (
Then, with the gate electrode 20 as the mask, the pocket ion implantation is made in one direction slanted toward the source side with respect to the semiconductor substrate 10 surface to form the pocket region 38 (
The pocket ion implantation is made in one direction slated toward the source side with respect to the semiconductor substrate 10 surface, whereby between the drain diffused layer 34 and the channel region 36 is the pocket impurity-not-implanted-region 40 due to the shadow effect of the gate electrode 20. Thus, the pocket region 38 are formed selectively between the source diffused layer 28 and the channel region 36.
In the present embodiment, the source diffused layers 28 and the drain diffused layers 34 of a plurality of MOS transistors 12 are arranged side by side in the same direction, which allows the pocket ion implantation to be made in one direction slanted toward the source side for the respective plural MOS transistors 12. Thus, the pocket region 38 is formed selectively between the source diffused layer 28 and the channel region 36 of each MOS transistor 12, and the pocket impurity not-implanted-region 40 can be formed between the drain diffused layer 34 and the channel region 36 of each MOS transistor 12. Accordingly, the GIDL of all the plural MOS transistors 12 can be decreased, and the electric power consumption of the semiconductor device in stand-by can be decreased.
The incidence angle θ for the pocket ion implantation can be suitably set in the range of 0°<θ<90°, depending on a height of the gate electrode 20, etc.
Then, a 2 nm-thickness silicon oxide film, for example, is formed on the entire surface by, e.g., thermal CVD method and is anisotropically etched to form the sidewall insulating film 22 on the side walls of the gate electrode 20 (
Next, with the gate electrode 20 and the sidewall insulating film 22 as the mask, an impurity is implanted by, e.g., ion implantation into the semiconductor substrate 10 on both sides of the gate electrode 20 and the sidewall insulating film 22. Thus, the impurity diffused regions 26, 32 are formed in the semiconductor substrate 10 on the source side and the drain side of the gate electrode 20 and the sidewall insulating film 22 (
Thus, the source diffused layer 28 formed of the LDD region 24 and the impurity diffused region 26 is formed in the semiconductor substrate 10 on the source side of the gate electrode 20, and the drain diffused layer 34 formed of the LDD region 30 and the impurity diffused region 32 is formed in the semiconductor substrate 10 on the drain side of the gate electrode 20. The pocket region 38 is formed between the source diffused layer 28 and the channel region 36, but between the drain diffused layer 34 and the channel region 36 is the pocket impurity-not-implanted regions 40.
Next, by the usual salicide process, for example, the silicide films 42 formed of, e.g., cobalt silicide (CoSi) are formed on the gate electrode 20, the source diffused layer 28 and the drain diffused layer 34 (
Hereafter, on the semiconductor substrate 10 with the MOS transistor 12 formed on, interconnection layers are suitably formed by the usual semiconductor device manufacturing process.
Thus, the semiconductor device according to the present embodiment is manufactured.
As described above, according to the present embodiment, the source diffused layers 28 and the drain diffused layer 34 of a plurality of MOS transistors 12 are arranged side by side in the same direction, and the pocket ion implantation is made in one direction slanted toward the source side with respect to the semiconductor substrate 10 surface, whereby the pocket region 38 can be formed between the source diffused layer 28 and the channel region 36, while between the drain diffused layer 34 and the channel region 36 can be the pocket impurity-not-implanted regions 40, for the plurality of MOS transistors 12. Thus, the GIDL can be decreased, and the electric power consumption of the semiconductor device in stand-by can be decreased.
In the above, both in the NMOS transistor and the PMOS transistor, the pocket ion implantation is made in one direction slanted toward the source side, but the pocket ion implantation may be made in one direction slanted toward the source side in either of the NMOS transistor and the PMOS transistor.
The semiconductor device and the method of manufacturing the same according to a second embodiment of the present invention will be explained with reference to FIGS. 12 to 19.
First, the structure of the semiconductor device according to the present embodiment will be explained with reference to FIGS. 12 to 16.
In the present embodiment, as illustrated in
As illustrated in
The load transistor L1 and the driver transistor D1 form an inverter INV1. The load transistor L2 and the driver transistor D2 form an inverter INV2. The inverter INV1 and the inverter INV2 form a flip-flop circuit FF. The flip-flop circuit FF is controlled by the transfer transistors T1, T2 connected to the bit lines BL, /BL and the word line WL.
As illustrated in
In the load transistor part 52, the active region A1 where the load transistor L1 is formed, and the active region A2 where the load transistor L2 is formed are isolated from each other by a device isolation film 14. Thus, the neighboring load transistors L1, L2 are formed independent of each other, and the source diffused layers 28p and the drain diffused layers 34p of the load transistors L1, L2 are arranged side by side in the same direction. In the load transistors L1, L2, pocket regions are formed selectively between the source diffused layers 28p and the channel regions, and between the drain diffused layers 34p and the channel regions are pocket impurity-not-implanted regions 40a.
In the driver transistor part 54, the active region A3 where the driver transistor D1 is formed and the active region A4 where the driver transistor D2 is formed are isolated from each other by the device isolation film 14. Thus, the neighboring driver transistors D1, D2 are formed independent of each other, and the source diffused layers 28n and the drain diffused layers 34n of the driver transistors D1, D2 are arranged side by side in the same direction. In the driver transistors D1, D2, pocket regions are formed selectively between the source diffused layers 28n and the channel regions, and between the drain diffused layers 34n and the channel regions are pocket impurity-not-implanted regions 40b.
In the transfer transistor part 56, the active region A5 where the transfer transistor T1 is formed is connected to the active region A3 where the driver transistor D1 is formed. The active region A6 where the transfer transistor T2 is formed is connected to the active region A4 where the driver transistor D2.
The load transistor L1 and the driver transistor D2 have a common gate electrode 20a. The load transistor L2 and the driver transistor D2 have a common gate electrode 20b. The transfer transistors T1, T2 have a common gate electrode 20c.
The SRAM cell MC illustrated in
The SRAM cells MC neighboring row-wise have the load transistors L1, L2, the driver transistors D1, D2 and the transfer transistors T1, T2 arranged in the same direction. The transfer transistors T1, T2 of a plurality of the SRAM cells MC arranged row-wise have a common gate electrode 20c.
A pair of the SRAM cells MC neighboring column-wise have the load transistors L1, L2, the driver transistors D1, D2 and the transfer transistors T1, T2 arranged line symmetrical with each other with respect to the border line between both as a symmetry axis. A pair of the SRAM cells MC neighboring column-wise have the active regions A5 where the transfer transistors T1 are formed connected to each other and have the active regions A6 where the transfer transistors T2 are formed connected to each other.
The semiconductor device according to the present embodiment is characterized mainly in that in each SRAM cell, the neighboring load transistors L1, L2 are formed independent of each other and have the source diffused layers 28p and the drain diffused layers 34p arranged side by side in the same direction, and the neighboring driver transistors D1, D2 are formed independent of each other and have the source diffused layers 28n and the drain diffused layers 34n arranged side by side in the same direction.
In the conventional SRAM cell, the neighboring MOS transistors have the layout in which the neighboring MOS transistors have a source diffused layer or a drain diffused layer in common.
As illustrated in the conventional SRAM cell, the active regions A1, A2 are formed integral with each other, and the neighboring load transistors L1, L2 have the drain diffused layer 34p in common. The active regions A3, A4 are formed integral with each other, and the neighboring driver transistors D1, D2 have the source diffused layer 28n in common. That is, the source diffused layers 28p and the drain diffused layers 34p of the load transistors L1, L2 are not arranged side by side in the same direction, and the source diffused layers 28n and the drain diffused layers 34n of the driver transistors D1, D2 are not arranged side by side in the same direction.
Accordingly, the layout of the conventional SRAM cell makes it very difficult to make the pocket ion implantation to be made in one direction slanted toward the source side in the load transistors L1, L2 and the driver transistors D1, D2. Accordingly, it is difficult to decrease the GIDL and decrease the electric power consumption of the semiconductor device in stand-by.
In contrast to the conventional SRAM cell, in the SRAM cell MC of the semiconductor device according to the present embodiment, the neighboring load transistors L1, L2 are formed independent of each other and have the source diffused layers 28p and the drain diffused layers 34p arranged side by side in the same direction, and the neighboring driver transistors D1, D2 are formed independent of each other and have the source diffused layers 28n and the drain diffused layers 34n arranged side by side in the same direction.
Accordingly, in the load transistors L1, L2, the pocket ion implantation can be made in one direction slanted toward the source side with respect to the semiconductor substrate 10 surface. Consequently, in the semiconductor device according to the present embodiment, in both of the load transistors L1, L2, the pocket regions are formed selectively between the source diffused layers 28p and the channel regions, and between the drain diffused layer 34p and the channel regions are the pocket impurity-not-implanted regions 40a as illustrated in
In the driver transistors D1, D2 as well, the pocket ion implantation can be made in one direction slanted toward the source side with respect to the semiconductor substrate 10 surface. Consequently, in the semiconductor device according to the present embodiment, in both of the driver transistors D1, D2, the pocket regions are formed selectively between the source diffused layers 28n and the channel regions, and between the drain diffused layer 34n and the channel regions are the pocket impurity-not-implanted regions 40b as illustrated in
As described above, in the load transistors L1, L2 and the driver transistors D1, D2, the pocket ion implantation can be made in one direction slanted toward source side with respect to the semiconductor substrate 10 surface, whereby the GIDL can be decreased, and the electric power consumption of the semiconductor device in stand-by can be decreased.
Next, the method of manufacturing the semiconductor device according to the present embodiment will be explained with reference to FIGS. 17 to 19. In the present embodiment, the method of manufacturing the semiconductor device according to the first embodiment is used to form the load transistors L1, L2 and the driver transistors D1, D2, etc.
First, in the same way as in the step shown in
Next, in the same way as in the step shown in
That is, first, impurities are implanted into the semiconductor substrate 10 by, e.g., ion implantation to form the wells 16n, 16p of prescribed conduction types (
Next, impurities of prescribed conduction types are implanted in the channel regions of the semiconductor substrate 10 by, e.g., ion implantation (
With a photoresist film prepared by lithography as the mask, the well implantation and the channel implantation are made respectively into the region where the PMOS transistors are to be formed and into the region where the NMOS transistors are to be formed.
Then, in the same way as in the steps shown in
Next, in the same way as in the step shown in
Next, the pocket ion implantation is made for the driver transistors D1, D2.
That is, first, a photoresist film which covers the regions where the load transistors L1, L2 and the transfer transistors T1, T2 are to be formed and exposes the regions where the driver transistors D1, D2 are to be formed is formed by photolithography.
Next, in the same way as in the step shown in
Thus, the pocket ion implantation is made in one direction slanted toward the source side with respect to eh semiconductor substrate 10 surface, whereby in the driver transistors D1, D2, between the drain diffused layers 34n and the channel regions are the pocket impurity-not-implanted regions 40b due to the shadow effect of the gate electrodes 20a, 20b.
In the present embodiment, the neighboring driver transistors D1, D2 are formed independent of each other and have the source diffused layers 28n and the drain diffused layers 34n arranged side by side in the same direction, whereby for the driver transistors D1, D2, the pocket ion implantation can be made in one direction slanted toward the source side with respect to the semiconductor substrate 10 surface.
After the pocket ion implantation has been made for the drive transistors D1, D2, the photoresist film used as the mask is removed.
Next, the pocket ion implantation is made for the load transistors L1, L2.
That is, first, a photoresist film which covers the regions where the driver transistors D1, D2 and the transfer transistors T1, T2 are to be formed and exposes the regions where the load transistors L1, L2 are to be formed is formed by photolithography.
Next, in the same way as in the step shown in
Thus, the pocket ion implantation is made in one direction slanted toward the source side with respect to the semiconductor substrate 10 surface, whereby in the load transistors L1, L2, between the drain diffused layers 34p and the channel regions are the pocket impurity-not implanted regions 40a due to the shadow effect of the gate electrodes 20a, 20b.
In the present embodiment, the neighboring load transistors L1, L2 are formed independent of each other and have the source diffused layers 28p and the drain diffused layers 34p arranged side by side in the same direction, whereby for the load transistors L1, L2, the pocket ion implantation can be made in one direction slanted toward the source side with respect to the semiconductor substrate 10 surface.
After the pocket ion implantation for the load transistors L1, L2, the photoresist film used as the mask is removed.
Next, in the same way as in the step shown in
Next, in the same way as in the step shown in
Next, in the same way as in the step shown in
Hereafter, on the semiconductor substrate 10 with the load transistors L1, L2, the driver transistors D1, D2 and the transfer transistors T1, T2 formed on, interconnection layers are suitably formed by the usual semiconductor device manufacturing process.
Thus, the semiconductor device according to the present embodiment is manufactured.
As described above, according to the present embodiment, the load transistors L1, L2 and the driver transistors D1, D2 have the source diffused layers and the drain diffused layers arranged side by side in the same direction, which allows the pocket ion implantation to be made in one direction slanted toward the source side with respect to the semiconductor substrate 10 surface, whereby the GIDL can be decreased, and the electric power consumption of the semiconductor device in stand-by can be decreased.
In the above, in the semiconductor device of the circuit structure illustrated in
The layout of the SRAM cell array illustrated in
To be specific, as illustrated in
As illustrated, for the transfer transistors T1, T2, between the drain diffused layers and the channel regions are the pocket impurity-not-implanted regions 40c due to the shadow effect of the gate electrodes 20c.
As described above, for the transfer transistors T1, T2, the pocket ion implantation may be made in one direction slanted toward the source side with respect to the semiconductor substrate 10 surface. Thus, for the transfer transistors T1, T2, the GIDL can be decreased, and the electric power consumption of the semiconductor device in stand-by can be further decreased.
In the above, for the load transistors L1, L2 and the driver transistors D1, D2, the pocket ion implantation is made in one direction slanted toward the source side with respect to the semiconductor substrate 10 surface, but for either of the load transistors L1, L2 and the driver transistors D1, D2, the pocket ion implantation may be made in one direction slanted toward the source side with respect to the semiconductor substrate 10 surface.
All the SRAM cells MC may not have the source diffused layers and the drain diffused layers of the load transistors L1, L2 and the driver transistors D1, D2 arranged side by side in the same direction.
The semiconductor device and the method of manufacturing the same according to a third embodiment of the present invention will be explained with reference to
First, the structure of the semiconductor device according to the present embodiment will be explained with reference to
The basic constitution of the semiconductor device according to the present embodiment is substantially the same as that of the semiconductor device according to the first embodiment. In the semiconductor device according to the present embodiment, an impurity of the same conduction type as the source diffused layer and the drain diffused layer is further ion-implanted in one direction slanted toward the drain side with respect to the semiconductor substrate 10 surface. In the present embodiment, the MOS transistor 12 is an NMOS transistor 12n.
In a semiconductor substrate 10, a device isolation film 14 for defining an active region is formed.
In the semiconductor substrate 10 with the active region defined, a p-type well 16p is formed.
On the semiconductor substrate 10, a gate electrode 20 is formed with a gate insulating film 18 formed therebetween. A sidewall insulating film 22 is formed on the side walls of the gate electrode 20.
In the semiconductor substrate 10 on the source side of the gate electrode 20, an n-type source diffused layer 28n is formed of an LDD region 24n formed by self-alignment with the gate electrode 20 and an impurity diffused layer 26n formed by self-alignment with the gate electrode 20 and the sidewall insulating film 22. In the semiconductor substrate 10 on the drain side of the gate electrode 20, an n-type drain diffused layer 34n is formed of an LDD region 30n formed by self-alignment with the gate electrode 20 and an impurity diffused layer 32n formed by self-alignment with the gate electrode 20p and the sidewall insulating film 22. Between the source diffused layer 28n and the drain diffused layer 34n is a p-type channel region 36p.
A p-type pocket region 38p is formed between the source diffused layer 28n and the channel region 36p. Between the drain diffused layer 34n and the channel region 36p, no pocket region is formed. That is, between the drain diffused layer 34n and the channel region 36p is a pocket impurity-not-implanted region 40.
Furthermore, the drain diffused layer 34n includes an n-type impurity diffused region 58n which is shallower than the LDD region 30n and has the end on the gate electrode 20 side extended up to below the gate electrode 20.
Silicide films 42 are formed on the gate electrode 20, the source diffused layer 28n and the drain diffused layer 34n.
The semiconductor device according to the present embodiment is characterized mainly in that, as in the semiconductor device according to the first embodiment, the pocket region 38p is formed selectively between the source diffused layer 28n and the channel region 36p of the NMOS transistor 12n, and between the drain diffused layer 34n and the channel region 36p is the pocket impurity-not-implanted region 40. Thus, the GIDL of the NMOS transistor 12n can be decreased, and the electric power consumption of the semiconductor device in stand-by can be decreased.
Furthermore, the semiconductor device according to the present embodiment is also characterized mainly in that the drain diffused layer 34n includes the n-type impurity diffused region 58n which is shallower than the LDD region 30n and has the end on the gate electrode 20 side extended up to below the gate electrode 20. As will be described later, the n-type impurity diffused region 58n is formed by ion-implanting an n-type impurity in one direction slanted toward the drain side with respect to the semiconductor substrate 10 surface.
In the semiconductor device according to the present embodiment, the n-type impurity diffused region 58n shortens the effective channel length of the NMOS transistor 12n. Accordingly, the drive current of the n-MOS transistor 12n can be increased.
As evident in the graph of
Furthermore, as evident in the graph of
As described above, according to the present embodiment, the leak current of the NMOS transistor can be decreased, and the drive current of the NMOS transistor can be increased.
Next, the method of manufacturing the semiconductor device according to the present embodiment will be explained with reference to
First, in the same way as in forming the NMOS transistor by the method of manufacturing the semiconductor device according to the first embodiment illustrated in
Then, with the gate electrode 20 as the mask, the pocket ion implantation of a p-type impurity is made in one direction slanted toward the source side with respect to the semiconductor substrate 10 surface to form the pocket region 38p (
In the same way as in the method of manufacturing the semiconductor device according to the first embodiment, the pocket ion implantation is made in one direction slanted toward the source side with respect to the semiconductor substrate 10 surface, whereby the pocket region 38p is formed selectively between the source diffused layer 28n and the channel region 36p of the NMOS transistor 12n while between the drain diffused layer 34n and the channel region 36p can be the pocket impurity-not-implanted region 40. Accordingly, the GIDL of the NMOS transistor 12n can be decreased, and the electric power consumption of the semiconductor device in stand-by can be decreased.
The incidence angle θ1 for the pocket ion implantation can be suitably set in the range of 0°<θ1<90°, depending on a height of the gate electrode 20, etc.
Then, with the gate electrode 20 as the mask, the ion implantation of an n-type impurity is made in one direction slanted toward the drain side with respect to the semiconductor substrate 10 surface. Thus, in the semiconductor substrate 10 on the drain side of the gate electrode 20, the n-type impurity diffused region 58n which is shallower than the LDD region 30n and has the end on the gate electrode 20 side extended up to below the gate electrode 20 is formed (
The ion implantation of the n-type impurity is thus made in one direction slanted toward the drain side with respect to the semiconductor substrate 10 surface to thereby form the n-type impurity diffused regions 58n, whereby the effective channel length of the NMOS transistor 12n can be decreased. Accordingly, the drive current of the NMOS transistor 12n can be increased.
When it is assumed that the ion implantation of the n-type impurity is made in one direction slanted toward the source side with respect to the semiconductor substrate 10 surface, this n-type impurity and the p-type impurity implanted by the pocket ion implantation will compensate each other. Resultantly, the effective channel length cannot be decreased, and even the effect of the pocket ion implantation is lost. Accordingly, the ion implantation of the n-type impurity must be made in one direction slanted toward the drain side with respect to the semiconductor substrate 10 surface.
The incidence angle θ2 of the ion implantation for forming the n-type impurity diffused region 58n can be suitably set in the range of 0°<θ2<90° depending on a height of the gate electrode 20, etc.
The following steps are the same as the steps for forming the NMOS transistor of the method of manufacturing the semiconductor device according to the first embodiment as shown in
As described above, according to the present embodiment, the pocket ion implantation is made in one direction slanted toward the source side with respect to the semiconductor substrate 10 surface, whereby the pocket region 38p can be formed selectively between the source diffused layer 28n and the channel region 36p of the NMOS transistor 12n, while between the drain diffused layer 34n and the channel region 36p can be the pocket impurity-not-implanted region 40. Accordingly, the GIDL of the NMOS transistor 12n can be decreased, and the electric power consumption of the semiconductor device in stand-by can be decreased.
Furthermore, according to the present embodiment, the ion implantation of the n-type impurity is made in one direction slanted toward the drain side with respect to the semiconductor substrate 10 surface to thereby form in the semiconductor substrate 10 on the drain side of the gate electrode 20 the n-type impurity diffused region 58n having the end on the gate electrode 20 side extended up to below the gate electrode 20, whereby the effective channel length of the NMOS transistor 12n can be decreased. Accordingly, the drive current of the NMOS transistor 12n can be increased.
In the above, after the pocket ion implantation for forming the pocket region 38p has been made, the ion implantation for forming the n-type impurity diffused region 58n is made. However, the sequence of making these steps may be reversed. That is, after the ion implantation for forming the n-type impurity diffused region 58n has been made, the pocket ion implantation for forming the pocket region 38p may be made.
The semiconductor device and the method of manufacturing the same according to a fourth embodiment of the present invention will be explained with reference to FIGS. 24 to 26.
First, the structure of the semiconductor device according to the present embodiment will be explained with reference to
The basic constitution of the semiconductor device according to the present embodiment is substantially the same as that of the semiconductor device according to the first embodiment. In the semiconductor device according to the present embodiment, an impurity of the same conduction type as the source diffused layer and the drain diffused layer is further ion-implanted in one direction slanted toward the drain side with respect to the semiconductor substrate 10 surface. In the present embodiment, the MOS transistor 12 is a PMOS transistor 12p.
In a semiconductor substrate 10, a device isolation film 14 for defining an active region is formed.
In the semiconductor substrate 10 with the active region defined, an n-type well 16n is formed.
On the semiconductor substrate 10, a gate electrode 20 is formed with a gate insulating film 18 formed therebetween. A sidewall insulating film 22 is formed on the side walls of the gate electrode 20.
In the semiconductor substrate 10 on the source side of the gate electrode 20, a p-type source diffused layer 28p is formed of an LDD region 24p formed by self-alignment with the gate electrode 20 and an impurity diffused region 26p formed by self-alignment with the gate electrode 20 and the sidewall insulating film 22. In the semiconductor substrate 10 on the drain side of the gate electrode 20, a p-type drain diffused layer 34p is formed of an LDD region 30p formed by self-alignment with the gate electrode 20 and an impurity diffused region 32p formed by self-alignment with the gate electrode 20 and the sidewall insulating film 22. Between the source diffused layer 28p and the drain diffused layer 34p is an n-type channel region 36n.
An n-type pocket region 38n is formed between the source diffused layer 28p and the channel region 36n. Between the drain diffused layer 34p and the channel region 36n, no pocket region is formed. That is, between the drain diffused layer 34p and the channel region 36n is a pocket impurity-not-implanted region 40.
Furthermore, the drain diffused layer 34p includes a p-type impurity diffused region 58p which is shallower than the LDD region 30p and has the end on the gate electrode 20 side extended up to below the gate electrode 20.
Silicide films 42 are formed on the gate electrode 20, the source diffused layer 28p and the drain diffused layer 34p.
The semiconductor device according to the present embodiment is characterized mainly in that, as in the semiconductor device according to the first embodiment, the pocket region 38n is formed selectively between the source diffused layer 28p and the channel region 36n of the PMOS transistor 12p, and between the drain diffused layer 34p and the channel region 36n is the pocket impurity-not-implanted region 40. Thus, the GIDL of the PMOS transistor 12 can be decreased, and the electric power consumption of the semiconductor device in stand-by can be decreased.
Furthermore, the semiconductor device according to the present embodiment is also characterized mainly in that the drain diffused layer 34p includes the p-type impurity diffused region 58p which is shallower than the LDD region 30p and has the end on the gate electrode 20 side extended up to below the gate electrode 20. As will be described alter, the p-type impurity diffused region 58p is formed by ion-implanting a p-type impurity in one direction slanted toward the drain side with respect to the semiconductor substrate 10 surface.
In the semiconductor device according to the present embodiment, the p-type impurity diffused region 58p shortens the effective channel length of the PMOS transistor 12p. Accordingly, the drive current of the PMOS transistor 12p can be increased.
As evident in the graph of
Furthermore, as evident in the graph of
As described above, according to the present embodiment, the leak current of the PMOS transistor can be decreased and the drive current of the PMOS transistor can be increased.
Next, the method of manufacturing the semiconductor device according to the present embodiment will be explained with reference to
First, in the same way as in forming the PMOS transistor by the method of manufacturing the semiconductor device according to the first embodiment illustrated in
Then, with the gate electrode 20 as the mask, the pocket ion implantation of an n-type impurity is made in one direction slanted toward the source side with respect to the semiconductor substrate 10 surface to form the pocket region 38n (
In the same way as in the method of manufacturing the semiconductor device according to the first embodiment, the pocket ion implantation is made in one direction slanted toward the source side with respect to the semiconductor substrate 10 surface, whereby the pocket region 38n is formed selectively between the source diffused layer 28p and the channel region 36n of the PMOS transistor 12p while between the drain diffused layer 34p and the channel region 36n can be the pocket impurity-not-implanted region 40. Accordingly, the GIDL of the PMOS transistor 12p can be decreased, and the electric power consumption of the semiconductor device in stand-by can be decreased.
The incident angle θ1 for the pocket ion implantation can be suitably set in the range of 0°<θ1<90° depending on a height of the gate electrode 20, etc.
Then, with the gate electrode 20 as the mask, the ion implantation of a p-type impurity is made in one direction slanted toward the drain side with respect to the semiconductor substrate 10 surface. Thus, in the semiconductor substrate 10 on the drain side of the gate electrode 20, the p-type impurity diffused region 58p which is shallower than the LDD region 30p and has the end on the gate electrode 20 side extended up to below the gate electrode 20 is formed (
The ion implantation of the p-type impurity is thus made in one direction slanted toward the drain side with respect to the semiconductor substrate 10 surface to thereby form the p-type impurity diffused region 58p, whereby the effective channel length of the PMOS transistor 12p can be decreased. Accordingly, the drive current of the PMOS transistor 12p can be increased.
When it is assumed that the ion implantation of the p-type impurity is made in one direction slanted toward the source side with respect to the semiconductor substrate 10 surface, this p-type impurity and the n-type impurity implanted by the pocket ion implantation will compensate each other. Resultantly, the effective channel length cannot be decreased, and even the effect of the pocket ion implantation is lost. Accordingly, the ion implantation of the p-type impurity must be made in one direction slanted toward the drain side with respect to the semiconductor substrate 10 surface.
The incidence angle θ2 of the ion implantation for forming the p-type impurity diffused region 58p can be suitably set in the range of 0°<θ2<90° depending on a height of the gate electrodes 20, etc.
The following steps are the same as steps for forming the PMOS transistor of the method of manufacturing the semiconductor device according to the first embodiment as shown in
As described above, according to the present embodiment, the pocket ion implantation is made in one direction slanted toward the source side with respect to the semiconductor substrate 10 surface, whereby the pocket region 38n can be formed selectively between the source diffused layer 28p and the channel region 36n of the PMOS transistor 12p, while between the drain diffused layer 34p and the channel region 36n can be the pocket impurity-not-implanted region 40. Accordingly, the GIDL of the PMOS transistor 12p can be decreased, and the electric power consumption of the semiconductor device in stand-by can be decreased.
Furthermore, according to the present embodiment, the ion implantation of the p-type impurity is made in one direction slanted toward the drain side with respect to the semiconductor substrate 10 surface to thereby form in the semiconductor substrate 10 on the drain side of the gate electrode 20 the p-type impurity diffused region 58p having the end on the gate electrode 20 side extended up to below the gate electrode 20, whereby the effective channel length of the PMOS transistor 12p can be decreased. Accordingly, the drive current of the PMOS transistor 12p can be increased.
In the above, after the pocket ion implantation for forming the pocket region 38n has been made, the ion implantation for forming the p-type impurity diffused region 58p is made. However, the sequence of making these steps may be reversed. That is, after the ion implantation for forming the p-type impurity diffused region 58p has been made, the pocket ion implantation for forming the pocket region 38n may be made.
The semiconductor device and the method of manufacturing the same according to a fifth embodiment of the present invention will be explained with reference to FIGS. 27 to 29.
First, the structure of the semiconductor device according to the present embodiment will be explained with reference to
The basic constitution of the semiconductor device according to the present embodiment is substantially the same as that of the semiconductor device according to the second embodiment. The semiconductor device according to the present embodiment uses the NMOS transistors 12n according to the third embodiment as the driver transistors D1, D2 forming an SRAM cell MC and uses the PMOS transistors 12p according to the fourth embodiment as the load transistors L1, L2 forming the SRAM cell MC.
As illustrated, in the SRAM cell MC of the semiconductor device according to the present embodiment, as in the semiconductor device according to the second embodiment, the neighboring load transistors L1, L2 are formed independent of each other and have the source diffused layers 28p and the source diffused layers 34p arranged side by side in the same direction, and the neighboring driver transistors D1, D2 are formed independent of each other and have the source diffused layers 28n and the drain diffused layers 34n arranged side by side in the same direction.
That is, in the load transistor part 52, the active region A1 where the load transistor L1 is formed and the active region A2 where the load transistor L2 is formed are isolated from each other by the device isolation film 14. The neighboring load transistors L1, L2 are formed thus independent of each other and have the source diffused layers 28p and the drain diffused layers 34p arranged side by side in the same direction. In the load transistors L1, L2, pocket regions are formed selectively between the source diffused layers 28p and the channel regions, and between the drain diffused layers 34p and the channel regions are pocket impurity-not-implanted regions 40a.
Furthermore, in the load transistors L1, L2, as in the PMOS transistor 12p according to the fourth embodiment, the drain diffused layer 34p includes the p-type impurity diffused region 58p which is shallower than the LDD region 30p and has the end on the gate electrode 20 side extended up to below the gate electrode 20 (refer to
In the driver transistor part 54, the active region A3 where the driver transistor D1 is formed and the active region A4 where the driver transistor D2 is formed are isolated from each other by the device isolation film 14. The neighboring driver transistors D1, D2 are formed thus independent of each, other and has the source diffused layers 28n and the drain diffused layers 34n arranged side by side in the same direction. In the driver transistors D1, D2, pocket regions are formed selectively between the source diffused layers 38n and the channel regions, and between the drain diffused layers 34n and the channel regions are pocket impurity-not-implanted regions 40b.
Furthermore, in the driver transistors D1, D2, as in the NMOS transistor 12n according to the third embodiment, the drain diffused layer 34n includes the n-type impurity diffused region 58n which is shallower than the LDD region 30n and has the end of the gate electrode 20 side extended up to below the gate electrode 20 (refer to
In the transfer transistor part 56, the active region A5 where the transfer transistor T1 is formed is connected to the active region A3 where the driver transistor D1 is formed. The active region A6 where the transfer transistor T2 is formed is connected to the active region A4 where the driver transistor D2 is formed.
The load transistor L1 and the driver transistor D1 have a gate electrode 20a in common. The load transistor L2 and the driver transistor D2 have a gate electrode 20b in common. The transfer transistors T1, T2 have a gate electrode 20c in common.
The SRAM cell MC illustrated in
The semiconductor device according to the present embodiment is characterized mainly in that, as in the semiconductor device according to the second embodiment, in the SRAM cell MC, the neighboring load transistors L1, L2 are formed independent of each other and have the source diffused layers 28 and the drain diffused layers 34p arranged side by side in the same direction, and the neighboring driver transistors D1, D2 are formed independent of each other and have the source diffused layers 28n and the drain diffused layers 34n arranged side by side in the same direction. This allows the pocket ion implantation to be made in one direction slanted toward the source side with respect to the semiconductor substrate 10 surface for the load transistors L1, L2 and the driver transistors D1, D2, whereby the GIDL can be decreased, and the electric power consumption of the semiconductor device in stand-by can be decreased.
Furthermore, the semiconductor device according to the present embodiment is characterized mainly in that, the drain diffused layer 34p of the load transistors L1, L2 includes the p-type impurity diffused region 58p which is shallower than the LDD region 30p and has the end on the gate electrode 20 side extended up to below the gate electrode 20 (refer to
In the semiconductor device according to the present embodiment, as described above, the load transistors L1, L2 and the driver transistors D1, D2 have the source diffused layers and the drain diffused layers arranged side by side in the same direction. This allows, the ion implantation of a p-type impurity for the load transistors L1, L2 and the ion implantation of an n-type impurity for the driver transistors D1, D2 to be made in one direction slanted toward the drain side with respect to the semiconductor substrate 10 surface to respectively form the p-type impurity diffused regions 58p and the n-type impurity diffused regions 58n. Thus, the effective channel length of the load transistors L1, L2 and the driver transistors D1, D2 can be decreased, and the dive current can be increased.
Next, the method of manufacturing the semiconductor device according to the present embodiment will be explained with reference to
First, in the same way as in the method of manufacturing the semiconductor device according to the second embodiment shown in
Next, for the load transistors L1, L2, the driver transistors D1, D2 and the transfer transistors T1, T2, ion implantation is made to form the LDD regions. The ion implantation for forming the LDD regions is made with a photoresist film prepared by lithography as the mask respectively into the region where the PMOS transistors are to be formed and the region where the NMOS transistors are to be formed. The ion implantation for forming the LDD regions may be made in one direction slanted toward the source side or the drain side with respect to the semiconductor substrate 10 surface.
Next, the pocket ion implantation is made for the driver transistors D1, D2.
That is, first, a photoresist film which covers the regions where the load transistors L1, L2 and the transfer transistors T1, T2 are to be formed and exposes the regions where the drive transistors D1, D2 are to be formed is formed by photolithography.
Next, in the same way as in the step shown in
Thus, the pocket ion implantation is made in one direction slanted toward the source side with respect to the semiconductor substrate 10 surface, whereby in the driver transistors D1, D2, between the drain diffused layers 34n and the channel regions are the pocket impurity-not-implanted regions 40b due to the shadow effect due to the gate electrodes 20a, 20b.
In the present embodiment, the neighboring driver transistors D1, D2 are formed independent of each other and have the source diffused layers 28n and the drain diffused layers 34n arranged side by side in the same direction, whereby for the driver transistors D1, D2, the pocket ion implantation can be made in one direction slanted toward the source side with respect to the semiconductor substrate 10 surface.
Then, in the same way as in the step shown in
The ion implantation of the n-type impurity is thus made in one direction slanted toward the drain side with respect to the semiconductor substrate 10 surface to thereby form the n-type impurity diffused regions 58n, whereby the effective channel length of the driver transistors D1, D2 can be decreased. Accordingly, the drive current of the driver transistors D1, D2 can be increased.
After the pocket ion implantation of the p-type impurity and the ion implantation of the n-type impurity have been made for the driver transistors D1, D2, the photoresist film used as the mask is removed.
Then, the pocket ion implantation is made for the load transistors L1, L2.
That is, first, a photoresist film which covers the regions where the driver transistors D1, D2 and the transfer transistors T1, T2 are to be formed and exposes the regions where the load transistors L1, L2 are to be formed is formed by photolithography.
Then, in the same way as in the step of
Thus, the pocket ion implantation is made in one direction slanted toward the source side with respect to the semiconductor substrate 10 surface, whereby in the load transistors L1, L2, between the drain diffused layers 34p and the channel regions are the pocket impurity-not-implanted regions 40a due to the shadow effect of the gate electrodes 20a, 20b.
In the present embodiment, the neighboring load transistors L1, L2 are formed independent of each other and have the source diffused layers 28p and the drain diffused layer 34p arranged side by side in the same direction, whereby for the load transistors L1, L2, the pocket ion implantation can be made in one direction slanted toward the source side with respect to the semiconductor substrate 10 surface.
Then, in the same way as in the step shown in
The ion implantation of the p-type impurity is thus made in one direction slanted toward the drain side with respect to the semiconductor substrate 10 surface to thereby form the p-type impurity diffused regions 58p, whereby the effective channel length of the load transistors L1, L2 can be decreased. Accordingly, the drive current of the load transistors L1, L2 can be increased.
After the pocket ion implantation of the n-type impurity and the ion implantation of the p-type impurity have been made for the load transistors L1, L2, the photoresist film used as the mask is removed.
The following steps including the step of forming a sidewall insulating film and after the step of forming the sidewall insulating film are the same as those of the method of manufacturing the semiconductor device according to the second embodiment, and their explanation is not repeated.
As described above, according to the present embodiment, the load transistors L1, L2 and the driver transistors D1, D2 have the source diffused layers and the drain diffused layers arranged side by side in the same direction, which allows the pocket ion implantation to be made in one direction slanted toward the source side with respect to the semiconductor substrate 10 surface, whereby the GIDL can be decreased, and the electric power consumption of the semiconductor device in stand-by can be decreased.
Furthermore, according to the present embodiment, for the load transistors L1, L2, the ion implantation of a p-type impurity is made in one direction slanted toward the drain side with respect to the semiconductor substrate 10 surface to thereby form the p-type impurity diffused regions having the ends on the gate electrode sides extended up to below the gate electrodes, and for the driver transistors D1, D2, the ion implantation of an n-type impurity is made to thereby form the n-type impurity diffused regions having the ends on the gate electrode sides extended up to below the gate electrodes, whereby the effective channel length of the load transistors L1, L2 and the driver transistors D1, D2 can be decreased, and drive current can be increased.
In the above, the present invention is applied to the SRAM circuit as in the second embodiment, but the present invention is applicable to a logic circuit, a CPU circuit, a peripheral circuit, etc.
As in the modification of the second embodiment shown in
The present invention is not limited to the above-described embodiments and can cover other various modifications.
For example, in the above-described embodiments, the pocket ion implantation is made in one direction slanted toward the source side with respect to the semiconductor substrate 10 surface but may be made in one direction slanted toward the drain side with respect to the semiconductor substrate 10 surface, depending on application, etc. of the MOS transistors. For example, for the load transistors L1, L2, the pocket ion implantation may be made in one direction slanted toward the drain side with respect to the semiconductor substrate 10 surface, which can increase the drive current of the load transistors L1, L2.
In the above-described embodiments, the pocket ion implantation for forming the pocket region is made in one direction slanted toward the source side with respect to the semiconductor substrate 10 surface, but the ion implantation for forming the LDD region may be made in one direction slanted toward the source side or the drain side with respect to the semiconductor substrate 10 surface. The ion implantation for forming the LDD region is made in one direction slanted toward the source side with respect to the semiconductor substrate 10 surface, whereby the LDD region can be formed selectively only in the source diffused layer. The LDD region is thus formed, whereby the GIDL can be decreased, and the electric power consumption of the semiconductor device in stand-by can be decreased.
In the above-described embodiments, the present invention is applied to the MOS transistor having the source/drain diffused layers of the LDD structure but is also applicable to the MIS transistor having the so-called extension source/drain structure and MIS transistors having other diffused layer structures.
The foregoing is considered as illustrative only of the principles of the present invention. Further, since numerous modifications and changes will readily occur to those skilled in the art, it is not desired to limit the invention to the exact construction and applications shown and described, and accordingly, all suitable modifications and equivalents may be regarded as falling within the scope of the invention in the appended claims and their equivalents.
| Number | Date | Country | Kind |
|---|---|---|---|
| 2005-081798 | Mar 2005 | JP | national |
This application is a Continuation of International Application No. PCT/JP2006/305522, with an international filing date of Mar. 20, 2006, which designating the United States of America, the entire contents of which are incorporated herein by reference. This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2005-081798, filed on Mar. 22, 2005, the entire contents of which are incorporated herein by reference.
| Number | Date | Country | |
|---|---|---|---|
| Parent | PCT/JP06/05522 | Mar 2006 | US |
| Child | 11902246 | Sep 2007 | US |
