Patent Application
20240290791
The disclosure of Japanese Patent Application No. 2023-028326 filed on Feb. 27, 2023 including the specification, drawings and abstract is incorporated herein by reference in its entirety.
The present invention relates to a semiconductor device and a method of manufacturing the same, for example, a semiconductor device using an SOI substrate and a method of manufacturing the same.
As a technology for a semiconductor device for low power consumption, there is the technology of forming a metal insulator semiconductor field effect transistor (MISFET) on a silicon on insulator (SOI) substrate including a semiconductor substrate, an insulating layer formed on the semiconductor substrate, and a silicon layer formed on the insulating layer. The MISFET formed on the SOI substrate has high soft error resistance, and can reduce a parasitic capacitance caused by a diffusion region formed in the silicon layer. Therefore, it is possible to achieve both the improvement in operation speed and the reduction in power consumption of the MISFET.
There are disclosed techniques listed below.
Patent Document 1 discloses the technology of forming a MISFET on an SOI substrate and applying a back gate potential to a well region located immediately below an insulating layer. An ON operation and an OFF operation of the MISFET are controlled by a gate potential applied to a gate electrode and the back gate potential.
In Patent Document 2, a bulk region is formed by removing a part of a silicon layer and an insulating layer of an SOI substrate. A low withstand voltage MISFET is formed on the SOI substrate, and a high withstand voltage MISFET is formed in the bulk region.
The inventors of this application have been studying the formation of not only a low withstand voltage MISFET but also a high withstand voltage MISFET on an SOI substrate. An ON operation and an OFF operation of each of the low withstand voltage MISFET and the high withstand voltage MISFET can be controlled by a gate potential and a back gate potential.
However, the study by the inventors of this application has revealed the problem that a voltage applied to an insulating layer increases and the TDDB life of the insulating layer is likely to be degraded if both the gate potential and the back gate potential are used. As a result, there is a problem that the reliability of a semiconductor device is lowered.
Other problems and novel features will be apparent from the description of this specification and the accompanying drawings.
An outline of representative embodiments disclosed in this application will be briefly described as follows.
A semiconductor device according to an embodiment includes a first region in which a first MISFET of a first conductivity type is formed and a second region in which a second MISFET of the first conductivity type is formed. The semiconductor device includes: an SOI substrate including a semiconductor substrate, an insulating layer formed on the semiconductor substrate, and a semiconductor layer formed on the insulating layer; a first well region formed in the semiconductor substrate in the first region, a conductivity type of the first well region being a second conductivity type opposite the first conductivity type; a first gate insulating film formed on the semiconductor layer in the first region; a first gate electrode formed on the first gate insulating film; a first impurity region formed in the semiconductor layer located beside the first gate electrode, a conductivity type of the first impurity region being the first conductivity type; a second well region formed in the semiconductor substrate in the second region, a conductivity type of the second well region being the second conductivity type; a second gate insulating film formed on the semiconductor layer in the second region; a second gate electrode formed on the second gate insulating film; and a second impurity region formed in the semiconductor layer located beside the second gate electrode, a conductivity type of the second impurity region being the first conductivity type. A thickness of the second gate insulating film is larger than a thickness of the first gate insulating film, a gate length of the second gate electrode is longer than a gate length of the first gate electrode, an ON operation and an OFF operation of the first MISFET are controlled by a first gate potential to be supplied to the first gate electrode and a first back gate potential to be supplied to the first well region, an ON operation and an OFF operation of the second MISFET are controlled by a second gate potential to be supplied to the second gate electrode in a state where the second well region is electrically floating, and an absolute value of a second power supply potential to be supplied to the second impurity region is larger than an absolute value of a first power supply potential to be supplied to the first impurity region.
A method of manufacturing a semiconductor device according to an embodiment is a method of manufacturing a semiconductor device including a first region in which a first MISFET of a first conductivity type is formed and a second region in which a second MISFET of the first conductivity type is formed. The method of manufacturing the semiconductor device includes steps of: (a) preparing an SOI substrate including a semiconductor substrate, an insulating layer formed on the semiconductor substrate, and a semiconductor layer formed on the insulating layer; (b) forming a first well region in the semiconductor substrate in the first region, a conductivity type of the first well region being a second conductivity type opposite the first conductivity type; (c) forming a second well region in the semiconductor substrate in the second region, a conductivity type of the second well region being the second conductivity type; (d) forming a second gate insulating film on the semiconductor layer in the second region; (e) forming a first gate insulating film on the semiconductor layer in the first region; (f) forming a first gate electrode on the first gate insulating film; (g) forming a second gate electrode on the second gate insulating film; (h) forming a first impurity region in the semiconductor layer located beside the first gate electrode by ion implantation, a conductivity type of the first impurity region being the first conductivity type; and (i) forming a second impurity region in the semiconductor layer located beside the second gate electrode by ion implantation, a conductivity type of the second impurity region being the first conductivity type. A thickness of the second gate insulating film is larger than a thickness of the first gate insulating film, a gate length of the second gate electrode is longer than a gate length of the first gate electrode, and an energy of the ion implantation in the step (i) is higher than an energy of the ion implantation in the step (h).
According to an embodiment, the reliability of the semiconductor device can be improved.
Hereinafter, embodiments will be described in detail with reference to the drawings. Note that, in all the drawings for describing the embodiments, members having the same function are denoted by the same reference characters, and repetitive description thereof will be omitted. In addition, in the following embodiments, descriptions of the same or similar parts will not be repeated in principle unless particularly necessary.
A structure of a semiconductor device according to a first embodiment will be described below with reference to
The low withstand voltage MISFET 1Q is a semiconductor element intended to be driven with low power consumption and to be driven at a higher speed than the high withstand voltage MISFET 2Q. The high withstand voltage MISFET 2Q is a semiconductor element that has a higher withstand voltage than the low withstand voltage MISFET 1Q and is driven at a higher power supply potential than the low withstand voltage MISFET 1Q.
Note that a p-type low withstand voltage MISFET is also formed on the SOI substrate 10 in the region 1A, and a p-type high withstand voltage MISFET is also formed on the SOI substrate 10 in the region 2A. The structures of the p-type low withstand voltage MISFET and the p-type high withstand voltage MISFET are equivalent to those obtained by reversing the conductivity types of the structures included in the n-type low withstand voltage MISFET 1Q and the n-type high withstand voltage MISFET 2Q, respectively. Here, a detailed description thereof will be omitted.
Furthermore, as illustrated in
In the low withstand voltage MISFET 1Q and the high withstand voltage MISFET 2Q formed on the SOI substrate 10, a gate voltage used during an operation is relatively low, and thus, thresholds thereof are likely to vary as compared with the high withstand voltage MISFETs 4Qn and 4Qp. Therefore, in the first embodiment, an ON operation and an OFF operation of each of the low withstand voltage MISFET 1Q and the high withstand voltage MISFET 2Q are controlled using not only a gate potential but also a back gate potential. As a result, the leakage current can be easily suppressed, and driving with low power consumption can be easily performed.
On the other hand, in each of the high withstand voltage MISFETs 4Qn and 4Qp, a gate voltage used during an operation is relatively high, and thus, thresholds thereof are less likely to vary as compared with the low withstand voltage MISFET 1Q and the high withstand voltage MISFET 2Q. Therefore, in the first embodiment, an ON operation and an OFF operation of each of the high withstand voltage MISFETs 4Qn and 4Qp are controlled using a gate potential without using a back bias potential. As a result, the current can be cut off during the OFF operation. Furthermore, since a thickness of the insulating layer BOX used in the first embodiment is 10-plus nm and is very thin, the TDDB life of the insulating layer BOX is significantly degraded if the high withstand voltage MISFETs 4Qn and 4Qp are formed on the SOI substrate 10. Furthermore, when the back bias potential is also used, the insulation resistance of the insulating layer BOX cannot be maintained. Therefore, the high withstand voltage MISFETs 4Qn and 4Qp are preferably formed in the bulk region.
Since main features of the first embodiment are in the low withstand voltage MISFET 1Q and the high withstand voltage MISFET 2Q formed on the SOI substrate 10, structures and manufacturing methods thereof will be mainly described in the following description.
As illustrated in
The semiconductor substrate SUB is made of, for example, p-type single crystal silicon. The insulating layer BOX is made of, for example, silicon oxide. A thickness of the insulating layer BOX is, for example, 10 nm or more and 20 nm or less. The semiconductor layer SL is made of single crystal silicon. A thickness of the semiconductor layer SL is, for example, 10 nm or more and 20 nm or less. Note that the semiconductor layer SL is an intrinsic semiconductor layer into which n-type or p-type impurities are not introduced by ion implantation or the like. Even if p-type impurities are introduced into the semiconductor layer SL, the impurity concentration thereof is 1×1013/cm3 or less.
A plurality of element isolation portions STI is formed in the SOI substrate 10. Each of the element isolation portions STI penetrates the semiconductor layer SL and the insulating layer BOX. A bottom portion of the element isolation portion STI is located inside the semiconductor substrate SUB. The element isolation portion STI is composed of a trench formed in the SOI substrate 10 and an insulating film embedded in the trench. The insulating film is, for example, a silicon oxide film.
In the semiconductor substrate SUB in the region 1A and the region 2A, an n-type well region DNW is formed. In the well region DNW in the region 1A, a p-type well region PW1 is formed. In the well region DNW in the region 2A, a p-type well region PW2 is formed. The element isolation portion STI and the well region DNW are formed between the well region PW1 and the well region PW2, and the well region PW1 and the well region PW2 are electrically isolated.
In the region 1A and the region 2A, the bulk region from which the semiconductor layer SL and the insulating layer BOX have been removed is provided. The bulk region in the region 1A functions as a power supply region SR1 for supplying a back gate potential to the well region PW1. The bulk region in the region 2A functions as a power supply region SR2 for supplying a back gate potential to the well region PW2.
Although described in detail later, the back gate potential may not be used in the high withstand voltage MISFET 2Q. Namely, the well region PW2 formed in the region 2A may be set in an electrically floating state. In that case, the bulk region (power supply region SR2) may not be provided in the region 2A. As a result, an area of the region 2A can be reduced, and the semiconductor device can be downsized.
Furthermore, the surface and its vicinity of each of the well region PW1 and the well region PW2 in contact with the insulating layer BOX are a region having the highest impurity concentration in the well region PW1 and the well region PW2, and is referred to as a ground plane layer, but illustration of the ground plane layer is omitted here.
A gate insulating film GI1 is formed on the semiconductor layer SL in the region 1A. A gate electrode GE1 is formed on the gate insulating film GI1. The gate insulating film GI1 is, for example, a silicon oxide film. The gate electrode GE1 is a conductive film, for example, a polycrystalline silicon film into which n-type impurities are introduced. In the semiconductor layer SL, a portion located immediately below the gate electrode GE1 serves as a channel region of the low withstand voltage MISFET 1Q.
On a side surface of the gate electrode GE1, a sidewall spacer SW2 is formed via an offset spacer OS. The offset spacer OS is an insulating film, for example, a silicon oxide film. The sidewall spacer SW2 is an insulating film, for example, a silicon nitride film.
In the semiconductor layer SL located beside the gate electrode GE1, a low-concentration n-type impurity region LDD1 is formed. Note that the “semiconductor layer SL located beside the gate electrode GE1” is a portion of the semiconductor layer SL located next to a portion (a portion to be a channel region) located immediately below the gate electrode GE1. In other words, the impurity region LDD1 is formed in a portion of the semiconductor layer SL immediately below the offset spacer OS and the sidewall spacer SW2.
An epitaxial layer EP is formed on the semiconductor layer SL located beside the sidewall spacer SW2. Note that the “semiconductor layer SL located beside the sidewall spacer SW2” is a portion of the semiconductor layer SL located next to the impurity region LDD1. In the epitaxial layer EP and the semiconductor layer SL, an n-type diffusion region (impurity region) ND1 is formed. Namely, the epitaxial layer EP and the diffusion region ND1 are formed at positions farther from the gate electrode GE1 than the impurity region LDD1 is. The diffusion region ND1 has an impurity concentration higher than that of the impurity region LDD1. The impurity region LDD1 and the diffusion region ND1 constitute a source region or a drain region of the low withstand voltage MISFET 1Q.
Although the semiconductor layer SL and the epitaxial layer EP are actually integrated, these layers are illustrated so as to be separated by broken lines for easy understanding of the description.
A silicide film SI is formed on the gate electrode GE1 and the epitaxial layer EP. The silicide film SI is made of, for example, nickel platinum silicide, nickel silicide, or cobalt silicide. Furthermore, the silicide film SI is also formed on an upper surface of the well region PW1 serving as the power supply region SR1.
Note that the other sidewall spacer SW2 is also formed on the element isolation portion STI and covers the side surface of the semiconductor layer SL. Furthermore, the sidewall spacer SW2 rides on a part of the epitaxial layer EP, and the silicide film SI is formed at a portion exposed from the sidewall spacer SW2 and the offset spacer OS.
A gate insulating film GI2 is formed on the semiconductor layer SL in the region 2A. A gate electrode GE2 is formed on the gate insulating film GI2. The gate insulating film GI2 is, for example, a silicon oxide film. The gate electrode GE2 is a conductive film, for example, a polycrystalline silicon film into which n-type impurities are introduced. In the semiconductor layer SL, a portion located immediately below the gate electrode GE2 serves as a channel region of the high withstand voltage MISFET 2Q.
On a side surface of the gate electrode GE2, the sidewall spacer SW2 is formed via the offset spacer OS. In the semiconductor layer SL located beside the gate electrode GE2, a low-concentration n-type impurity region LDD2 is formed. Note that the “semiconductor layer SL located beside the gate electrode GE2” is a portion of the semiconductor layer SL located next to a portion (a portion to be a channel region) located immediately below the gate electrode GE2. In other words, the impurity region LDD2 is formed in a portion of the semiconductor layer SL immediately below the offset spacer OS and the sidewall spacer SW2.
An epitaxial layer EP is formed on the semiconductor layer SL located beside the sidewall spacer SW2. Note that the “semiconductor layer SL located beside the sidewall spacer SW2” is a portion of the semiconductor layer SL located next to the impurity region LDD2. In the epitaxial layer EP and the semiconductor layer SL, an n-type diffusion region (impurity region) ND2 is formed. Namely, the epitaxial layer EP and the diffusion region ND2 are formed at positions farther from the gate electrode GE2 than the impurity region LDD2 is. The diffusion region ND2 has an impurity concentration higher than that of the impurity region LDD2. The impurity region LDD2 and the diffusion region ND2 constitute a source region or a drain region of the high withstand voltage MISFET 2Q.
A silicide film SI is formed on the gate electrode GE2 and the epitaxial layer EP. Furthermore, the silicide film SI is also formed on an upper surface of the well region PW2 serving as the power supply region SR2.
As illustrated in
In the semiconductor substrate SUB in the region 4A, an n-type well region DNW is formed. In the well region DNW in the region 4A, a p-type well region PW4 and an n-type well region NW4 are formed.
On the well region PW4, a gate electrode GE4n is formed via a gate insulating film GI4. The gate insulating film GI4 is, for example, a silicon oxide film. The gate electrode GE4n is a conductive film, for example, a polycrystalline silicon film into which n-type impurities are introduced. In the well region PW4, a portion located below the gate electrode GE4n serves as a channel region of the high withstand voltage MISFET 4Qn.
On a side surface of the gate electrode GE4n, the sidewall spacer SW2 is formed via the offset spacer OS. A low-concentration n-type impurity region LDD4n is formed in the well region PW4 located beside the gate electrode GE4n. An n-type diffusion region (impurity region) ND4 is formed in the well region PW4 located beside the sidewall spacer SW2. The diffusion region ND4 has an impurity concentration higher than that of the impurity region LDD4n. The impurity region LDD4n and the diffusion region ND4 constitute a source region or a drain region of the high withstand voltage MISFET 4Qn.
On the well region NW4, a gate electrode GE4p is formed via the gate insulating film GI4. The gate electrode GE4p is a conductive film, for example, a polycrystalline silicon film into which p-type impurities are introduced. In the well region NW4, a portion located below the gate electrode GE4p serves as a channel region of the high withstand voltage MISFET 4Qp.
On a side surface of the gate electrode GE4p, the sidewall spacer SW2 is formed via the offset spacer OS. In the well region NW4 located beside the gate electrode GE4p, a low-concentration p-type impurity region LDD4p is formed. A p-type diffusion region (impurity region) PD4 is formed in the well region NW4 located beside the sidewall spacer SW2. The diffusion region PD4 has an impurity concentration higher than that of the impurity region LDD4p. The impurity region LDD4p and the diffusion region PD4 constitute a source region or a drain region of the high withstand voltage MISFET 4Qp.
The silicide film SI is formed on an upper surface of each of the gate electrode GE4n, the diffusion region ND4, the gate electrode GE4p, and the diffusion region PD4.
The low withstand voltage MISFET 1Q is a semiconductor element having the thinnest gate insulating film in the semiconductor device, and is a semiconductor element whose gate length is shortest in the semiconductor device. The high withstand voltage MISFET 2Q is a semiconductor element whose gate insulating film is thicker than that of the low withstand voltage MISFET 1Q, and is a semiconductor element whose gate length is longer than that of the low withstand voltage MISFET 1Q. Note that each of the high withstand voltage MISFETs 4Qn and 4Qp is a semiconductor element whose gate insulating film is thicker than that of the high withstand voltage MISFET 2Q, and is a semiconductor element whose gate length is longer than that of the high withstand voltage MISFET 2Q.
As illustrated in
A gate length of the gate electrode GE1 is, for example, 30 nm or more and 60 nm or less, and preferably 40 nm or 45 nm. A gate length of the gate electrode GE2 is longer than the gate length of the gate electrode GE1, for example, 200 nm or more and 300 nm or less, and preferably 250 nm.
During the ON operation and the OFF operation of the low withstand voltage MISFET 1Q, a gate potential Vg1 is supplied to the gate electrode GE1, a source potential Vs1 is supplied to the source region, a power supply potential Vd1 is supplied to the drain region, and a back gate potential Vbn1 is supplied to the well region PW1. Note that each of the source region and the drain region of the low withstand voltage MISFET 1Q is composed of the impurity region LDD1 and the diffusion region ND1. Furthermore, the source potential Vs1 is, for example, a ground potential (GND).
During the ON operation and the OFF operation of the high withstand voltage MISFET 2Q, a gate potential Vg2 is supplied to the gate electrode GE2, a source potential Vs2 is supplied to the source region, and a power supply potential Vd2 is supplied to the drain region. Note that each of the source region and the drain region of the high withstand voltage MISFET 2Q is composed of the impurity region LDD2 and the diffusion region ND2. Furthermore, the source potential Vs2 is, for example, a ground potential (GND).
In the high withstand voltage MISFET 2Q, it is also possible to supply a back gate potential Vbn2 to the well region PW2, but no potential is supplied to the well region PW2 (Open) in the first embodiment. In other words, the well region PW2 is in an electrically floating state.
Specifically, the ON operation and the OFF operation of the low withstand voltage MISFET 1Q are controlled by the gate potential Vg1 and the back gate potential Vbn1. On the other hand, the ON operation and the OFF operation of the high withstand voltage MISFET 2Q are controlled by the gate potential Vg2, but are not controlled by the back gate potential.
Furthermore, the high withstand voltage MISFET 2Q operates at a higher power supply potential than the low withstand voltage MISFET 1Q. An absolute value of the power supply potential Vd2 is larger than an absolute value of the power supply potential Vd1. During the ON operation, the power supply potential Vd2 is, for example, 1.8 V, and the power supply potential Vd1 is, for example, 0.79 V. Moreover, each of the high withstand voltage MISFETs 4Qn and 4Qp operates at a higher power supply potential than the high withstand voltage MISFET 2Q. An absolute value of the power supply potential to be supplied to the drain region of each of the high withstand voltage MISFETs 4Qn and 4Qp is larger than an absolute value of the power supply potential Vd2, and is, for example, 3.3 V.
Here, the study by the inventors of this application has revealed that the TDDB life of the insulating layer BOX of the high withstand voltage MISFET 2Q is likely to be degraded if the gate potential Vg2 and the back gate potential Vbn2 are used for the ON operation and the OFF operation of the high withstand voltage MISFET 2Q. This is because the power supply potential Vd2 of the high withstand voltage MISFET 2Q is high.
Specifically, although the insulating layers BOX having the same thickness are used in the low withstand voltage MISFET 1Q and the high withstand voltage MISFET 2Q, the higher voltage is applied to the insulating layer BOX of the high withstand voltage MISFET 2Q because the power supply potential Vd2 is high in the high withstand voltage MISFET 2Q. Therefore, there is a problem that the TDDB life of the insulating layer BOX of the high withstand voltage MISFET 2Q is likely to be degraded and the reliability of the semiconductor device is lowered.
Therefore, in the first embodiment, the back gate potential Vbn2 is not supplied to the well region PW2 (power supply region SR2) of the high withstand voltage MISFET 2Q. In this way, the degradation of the TDDB life of the insulating layer BOX of the high withstand voltage MISFET 2Q can be suppressed, so that the reliability of the semiconductor device can be improved.
On the other hand, although the power supply potential Vd1 of the low withstand voltage MISFET 1Q is relatively low, the TDDB life of the insulating layer BOX may be degraded even in the low withstand voltage MISFET 1Q because the back gate potential Vbn1 is used.
As a result of the study by the inventors of this application, it has been found that the TDDB life of the insulating layer BOX varies by changing the energy of ion implantation and varying the damage amount of the ion implantation into the insulating layer BOX. In the first embodiment, the energy of ion implantation of the diffusion regions ND1 and ND2 is lower than that in the related art, and the ion implantation is performed under the conditions shown in
Furthermore, in the first embodiment, the energy of ion implantation of the impurity region LDD1 is also lower than that in the related art, and the ion implantation is performed under the conditions shown in
In a case where the back gate potential Vbn2 is used in the high withstand voltage MISFET 2Q, from the viewpoint of further suppressing the degradation of the TDDB life of the high withstand voltage MISFET 2Q, the energy of the ion implantation of the impurity region LDD2 is preferably set to the same level as the energy of the ion implantation of the impurity region LDD1. However, in the high withstand voltage MISFET 2Q of the first embodiment, the degradation of the TDDB life of the insulating layer BOX can be suppressed by not using the back gate potential Vbn2 as described above.
Also, since the high withstand voltage MISFET 2Q is driven at the power supply potential Vd2 higher than that of the low withstand voltage MISFET 1Q, a problem tends to be more remarkable in the high withstand voltage MISFET 2Q than in the low withstand voltage MISFET 1Q. For example, since a high electric field is generated in the vicinity of the drain region in the high withstand voltage MISFET 2Q, the deterioration of the gate insulating film GI2 over time due to hot carrier injection tends to be a problem.
Therefore, in the first embodiment, the energy of the ion implantation of the impurity region LDD2 is made higher than the energy of the ion implantation of the impurity region LDD1. In this way, an impurity concentration peak of the impurity region LDD2 is brought close to the insulating layer BOX and away from the gate insulating film GI2. Preferably, the ion implantation is set such that a position of the impurity concentration peak of the impurity region LDD2 is located in the insulating layer BOX.
Since a portion where a high electric field is likely to be generated, that is, a portion where hot carriers are likely to be generated is brought away from the gate insulating film GI2, hot carriers are less likely to be injected into the gate insulating film GI2. Therefore, the deterioration of the gate insulating film GI2 over time is suppressed.
The energy of the ion implantation of the impurity region LDD2 is higher than the energy of the ion implantation of the impurity region LDD1, and the impurity concentration peak of the impurity region LDD2 is located closer to the insulating layer BOX than the impurity concentration peak of the impurity region LDD1 is, and is preferably located in the insulating layer BOX.
Therefore, as illustrated in
As described above, in the semiconductor device according to the first embodiment, the degradation of the TDDB life of the insulating layer BOX can be suppressed in the low withstand voltage MISFET 1Q and the high withstand voltage MISFET 2Q, and the deterioration of the gate insulating film GI2 over time due to hot carrier injection can be suppressed in the high withstand voltage MISFET 2Q. Therefore, the reliability of the semiconductor device can be improved.
From the viewpoint of suppressing the leakage current and facilitating the driving with low power consumption, it is preferable to use the back gate potential Vbn2 also in the high withstand voltage MISFET 2Q. However, in the high withstand voltage MISFET 2Q, the gate length is sufficiently long and the thickness of the gate insulating film GI2 is sufficiently large as compared with the low withstand voltage MISFET 1Q. Therefore, since the influence of the leakage current and the like is smaller in the high withstand voltage MISFET 2Q than in the low withstand voltage MISFET 1Q, the high withstand voltage MISFET 2Q can be operated without deteriorating the performance of the high withstand voltage MISFET 2Q even if the back gate potential Vbn2 is not used. In the case of placing emphasis on the suppression of the degradation of the TDDB life of the insulating layer BOX as in the first embodiment, it is preferable not to use the back gate potential Vbn2.
Furthermore, although the n-type low withstand voltage MISFET 1Q and the n-type high withstand voltage MISFET 2Q are exemplified in the first embodiment, the p-type low withstand voltage MISFET is also formed on the SOI substrate 10 in the region 1A and the p-type high withstand voltage MISFET is also formed on the SOI substrate 10 in the region 2A as described above. The technology described in the first embodiment can also be applied to the p-type low withstand voltage MISFET and the p-type high withstand voltage MISFET, and equivalent effects can be obtained.
Each manufacturing step included in a method of manufacturing the semiconductor device according to the first embodiment will be described below with reference to
As illustrated in
Next, an insulating film IF1 made of, for example, silicon oxide is formed on the semiconductor layer SL by, for example, the chemical vapor deposition (CVD) method. A thickness of the insulating film IF1 is, for example, 10 nm or more and 20 nm or less. Next, for example, a silicon nitride film is formed on the insulating film IF1 by, for example, the CVD method. A thickness of the silicon nitride film is, for example, 80 nm or more and 120 nm or less. Next, the silicon nitride film is patterned by the photolithography technique and the anisotropic etching process. As a result, a hard mask HM made of the silicon nitride film is formed.
Next, the anisotropic etching process using the hard mask HM as a mask is performed to form a plurality of trenches penetrating the insulating film IF1, the semiconductor layer SL, and the insulating layer BOX and reaching the inside of the semiconductor substrate SUB. Next, for example, a silicon oxide film is formed inside the plurality of trenches and on the hard mask HM by, for example, the CVD method. Next, the silicon oxide film formed on the hard mask HM is removed by the polishing process using, for example, the chemical mechanical polishing (CMP) method. In this way, a plurality of the element isolation portions STI is formed inside the plurality of trenches, respectively.
As illustrated in
Next, the n-type well region DNW is formed in the semiconductor substrate SUB in the region 1A and the region 2A by using the photolithography technique and the ion implantation method. Next, by using the photolithography technique and the ion implantation method, the p-type well region PW1 is selectively formed in the well region DNW in the region 1A, and the p-type well region PW2 is selectively formed in the well region DNW in the region 2A.
As illustrated in
As illustrated in
As illustrated in
The thin silicon oxide film on the semiconductor layer SL in the region 1A serves as the gate insulating film GI1 of the low withstand voltage MISFET 1Q, and the thick silicon oxide film on the semiconductor layer SL in the region 2A serves as the gate insulating film GI2 of the high withstand voltage MISFET 2Q.
Next, a conductive film CF1 made of, for example, a polycrystalline silicon film is formed on the gate insulating film GI1 and the gate insulating film GI2 by, for example, the CVD method. Next, impurities exhibiting n-type conductivity are selectively introduced into the conductive films CF1 in the region 1A and the region 2A by using the photolithography technique and the ion implantation method. Next, an insulating film IF2 made of, for example, a silicon nitride film is formed on the conductive film CF1 by, for example, the CVD method.
As illustrated in
As illustrated in
Next, a resist pattern RP2 that selectively covers the power supply regions SR1 and SR2 is formed. Next, the anisotropic etching process using the resist pattern RP2 as a mask is performed on the insulating film IF4 and the insulating film IF3 to form the sidewall spacer SW1 and the offset spacer OS on the side surfaces of the gate electrode GE1 and the gate electrode GE2, respectively. Note that the sidewall spacer SW1 is formed on the side surface of each of the gate electrodes GE1 and GE2 via the offset spacer OS. Furthermore, the power supply regions SR1 and SR2 are covered with the insulating films IF4 and IF3. Thereafter, the resist pattern RP2 is removed by the ashing process.
As illustrated in
As illustrated in
The ion implantation in
Note that, since the epitaxial layer EP is thick, ions do not reach the entire semiconductor layer SL located beside the gate electrode GE1 in the ion implantation mentioned above. Therefore, the impurity region LDD1 is formed in a part of the semiconductor layer SL in the region 1A.
As illustrated in
The ion implantation in
As described with reference to
Note that, since the epitaxial layer EP is thick, ions do not reach the entire semiconductor layer SL located beside the gate electrode GE2 in the ion implantation mentioned above. Therefore, the impurity region LDD2 is formed in a part of the semiconductor layer SL in the region 2A.
Furthermore, the order of the ion implantation of the impurity region LDD1 and the ion implantation of the impurity region LDD2 is not particularly limited.
As illustrated in
As illustrated in
The ion implantation in
As described above, the low withstand voltage MISFET 1Q is formed in the region 1A and the high withstand voltage MISFET 2Q is formed in the region 2A.
Thereafter, the structure illustrated in
A semiconductor device according to a second embodiment will be described below with reference to
As illustrated in
In the semiconductor substrate SUB in the region 3A, the n-type well region DNW is formed. In the well region DNW in the region 3A, an n-type well region NW3 is formed.
In the semiconductor layer SL in the region 3A, a low-concentration p-type impurity region LDD3 is formed. The epitaxial layer EP is formed on the semiconductor layer SL in the region 3A. In the epitaxial layer EP and the semiconductor layer SL, a p-type diffusion region (impurity region) PD3 is formed. The diffusion region PD3 has an impurity concentration higher than that of the impurity region LDD3.
An insulating film IF5 is formed so as to cover a part of the epitaxial layer EP and the semiconductor layer SL in the region 3A. The insulating film IF5 is formed immediately before the step of forming the silicide film SI, and is provided to protect a region where the silicide film SI is not desired to be formed. The insulating film IF5 is, for example, a silicon oxide film. The silicide film SI is formed on the epitaxial layer EP exposed from the insulating film IF5.
A portion of the semiconductor layer SL where the impurity region LDD3 is formed is a low resistance portion and constitutes a main portion of the resistance element 3Q. Two diffusion regions PD3 (two epitaxial layers EP) sandwiching the impurity region LDD3 constitute both terminals Vin and Vout of the resistance element 3Q. Note that, although not illustrated here, a part of the well region NW3 constitutes a power supply region such as the power supply regions SR1 and SR2, and a back gate potential Vb3 can be supplied from this power supply region to the well region NW3.
However, if the back gate potential Vb3 is used when a current flows between the terminal Vin and the terminal Vout, a voltage applied to the insulating layer BOX of the resistance element 3Q increases, and the TDDB life of the insulating layer BOX of the resistance element 3Q may be degraded. Therefore, in the second embodiment, the back gate potential Vb3 is not supplied to the well region NW3 (Open). Namely, the well region NW3 is in an electrically floating state. As a result, the degradation of the TDDB life of the insulating layer BOX of the resistance element 3Q can be suppressed.
Furthermore, in the second embodiment, for the same reason as in the first embodiment, the energy of ion implantation of each of the impurity region LDD3 and the diffusion region PD3 is lower than that in the related art.
The ion implantation of the impurity region LDD3 is performed using boron difluoride (BF2) under the conditions that an implantation energy is 5 keV or less and a dose amount is 4.0×1014/cm2. At this time, the ion implantation is set such that a position of the impurity concentration peak of the impurity region LDD3 is located in the semiconductor layer SL.
The ion implantation of the diffusion region PD3 is performed using boron (B) under the conditions that an implantation energy is 2 keV and a dose amount is 4.0×1015/cm2. At this time, the ion implantation is set such that a position of the impurity concentration peak of the diffusion region PD3 is located in the epitaxial layer EP.
The energy of the ion implantation of the impurity region LDD3 is lower than the energy of the ion implantation of the impurity region LDD2, similarly to the impurity region LDD1. Therefore, the degradation of the TDDB life of the insulating layer BOX of the resistance element 3Q can be further suppressed.
By lowering the energy of the ion implantation of the impurity region LDD3, the impurity concentration peak of the impurity region LDD3 is located farther from the insulating layer BOX than the impurity concentration peak of the impurity region LDD2 is. Therefore, the amount of the damaged layer 20 present in the insulating layer BOX located immediately below the impurity region LDD3 is smaller than the amount of the damaged layer 20 present in the insulating layer BOX located immediately below the impurity region LDD2.
As described above, in the semiconductor device according to the second embodiment, the degradation of the TDDB life of the insulating layer BOX of the resistance element 3Q can be suppressed, and the reliability of the semiconductor device can be improved.
Note that the step of performing the ion implantation of the impurity region LDD3 can be performed using a resist pattern having a pattern that selectively opens the region 3A after the step of
A semiconductor device according to a third embodiment will be described below with reference to
In the first embodiment, the impurity regions LDD1 and LDD2 are formed after the epitaxial layer EP is formed. In the third embodiment, the epitaxial layer EP is formed after the impurity regions LDD1 and LDD2 are formed.
The manufacturing process of the third embodiment is the same as that of the first embodiment until the structure in
As illustrated in
Next, the resist pattern RP3 similar to that in
Note that, since the epitaxial layer EP is not formed at this stage, the impurity region LDD1 is formed in the entire semiconductor layer SL located beside the gate electrode GE1 in the ion implantation mentioned above.
As illustrated in
Note that, since the epitaxial layer EP is not formed at this stage, the impurity region LDD2 is formed in the entire semiconductor layer SL located beside the gate electrode GE2 in the ion implantation mentioned above.
Furthermore, the order of the ion implantation of the impurity region LDD1 and the ion implantation of the impurity region LDD2 is not particularly limited.
As illustrated in
Next, the resist pattern RP2 similar to that in
As illustrated in
As illustrated in
As described above, the low withstand voltage MISFET 1Q is formed in the region 1A, and the high withstand voltage MISFET 2Q is formed in the region 2A.
Thereafter, the insulating films IF4 and IF3 formed in the power supply regions SR1 and SR2 are selectively removed, and then the silicide film SI similar to that of the first embodiment is formed.
In the third embodiment, similarly to the first embodiment, the energy of the ion implantation of the impurity region LDD2 is higher than the energy of the ion implantation of the impurity region LDD1, and the impurity concentration peak of the impurity region LDD2 is located closer to the insulating layer BOX than the impurity concentration peak of the impurity region LDD1 is, and is preferably located in the insulating layer BOX.
Therefore, as illustrated in
Also in the third embodiment, the degradation of the TDDB life of the insulating layer BOX can be suppressed in the low withstand voltage MISFET 1Q and the high withstand voltage MISFET 2Q, and the deterioration of the gate insulating film GI2 over time due to hot carrier injection can be suppressed in the high withstand voltage MISFET 2Q. Therefore, the reliability of the semiconductor device can be improved.
Note that, in the first embodiment, the impurity regions LDD1 and LDD2 are formed in a part of the semiconductor layer SL located beside the gate electrodes GE1 and GE2. On the other hand, in the third embodiment, the impurity regions LDD1 and LDD2 are formed in the entire semiconductor layer SL located beside the gate electrodes GE1 and GE2. Namely, since the impurity regions LDD1 and LDD2 are also formed in the semiconductor layer SL below the epitaxial layer EP, resistance can be reduced in the semiconductor layer SL below the epitaxial layer EP. Therefore, in the third embodiment, the resistance of the source region and the drain region of each of the low withstand voltage MISFET 1Q and the high withstand voltage MISFET 2Q can be reduced as compared with the first embodiment.
Furthermore, the resistance values of the entire source and drain regions can be adjusted to the same level as in the first embodiment. For example, the impurity concentration of each of the impurity regions LDD1 and LDD2 may be made lower than that of the first embodiment. Namely, the dose amount of the ion implantation of each of the impurity regions LDD1 and LDD2 may be made smaller than the condition of
Furthermore, in the high withstand voltage MISFET 2Q, the impurity concentration of the impurity region LDD2 decreases, so that the electric field in the vicinity of the drain region can be relaxed. Therefore, hot carriers are less likely to be injected into the gate insulating film GI2, and the deterioration of the gate insulating film GI2 over time can be further suppressed.
Note that the impurity concentration of the impurity region LDD2 may be lowered only in the high withstand voltage MISFET 2Q. Namely, the impurity concentration of the impurity region LDD2 may be lower than the impurity concentration of the impurity region LDD1.
In the foregoing, the present invention has been specifically described based on the embodiments, but the present invention is not limited to the embodiments described above and various modifications can be made within the range not departing from the gist thereof.
| Number | Date | Country | Kind |
|---|---|---|---|
| 2023-028326 | Feb 2023 | JP | national |
